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2.1i COREGEN, C_IP1, FOUNDATION: "Line: 3 Wrong number of fields BUS" on modules during symbol generation


Record #7151

Product Family: Software

Product Line: Coregen

Product Part: Coregen

Product Version: 2.1

Problem Title:

2.1i COREGEN, C_IP1, FOUNDATION:  "Line: 3   Wrong number of fields BUS" on modules during
symbol generation



Problem Description:
Urgency: hot

General Description:
There is a problem with Foundation symbol generation for the following
BaseBLOX modules (mux_bus, gate_bus, register, latch ). The problem is
associated with single-bit input buses. A 1-bit input bus causes the following message to appear in a pop-up when the F2.1i NET2SYM interface program
is invoked by the CORE Generator when the module is being generated:

   Line <line_number>
   Wrong number of fields
   BUS

The result is that neither a symbol nor an ALR file is generated for the
module. (Note that a single-bit Select Bus would also be inferred when only
two input buses are requested for a MUX Bus module).

The problem is that the newer version of the NET2SYM interrface
supplied with Foundation 2.1i expects a different format for specifying
single bit buses.

In pre-2.1i versions of Foundation, the required XSF format for
a single bit bus was:

   BUS, <busname>, 0

In the 2.1i version of Foundation, NET2SYM expects:

   BUS, <busname>, 0, 0

The reference to "wrong number of fields" refers to the fact that
the parser in NET2SYM is expecting 4 comma-delimited fields
instead of the 3 specified in the netlist.

Sample XSF snippet (note the single bit buses MA, MB, MC, MD,
ME, MF and Q):

  LCANET, 5
  SYM, I1, mux61
  BUS, MA, 0
  BUS, MB, 0
  BUS, MC, 0
  BUS, MD, 0
  BUS, ME, 0
  BUS, MF, 0
  BUS, S, 2, 1, 0
  BUS, Q, 0
  PIN, MA<0>, I, MA<0>
  ....





Solution 1:

This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/



Solution 2:

If the Service Pack is unavailable to you, you can use the following
workaround:

1. Edit the XSF file produced by CORE Generator and add the additional
",0" to the end of each single bit BUS record

2. Next, run net2sym to create the required symbol and .ALR interface files.

   a. Double click on $XILINX\active\exe\net2sym.exe
   b. Enter the name of the module in the Symbol Name field
   c. Enter the name of the XSF file in the Symbol Netlist field
   d. Browse to the associated Foundation PDF file to file in
        the "Project PDF file" field.
   e. Click on OK to generate the symbol

Verify that the following properties are present on the symbol
by double clicking on it:

   $BUSDELIMITER=<
   $EXPORT=NO
   $FILE=<modulename>.XSF






End of Record #7151 - Last Modified: 11/22/99 10:23

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