Contents of /pub/applications/xapp
Application design files for XAPP Application Notes
See http://www.xilinx.com/apps/xapp.htm for more information.
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Filename Size File Description
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i2c_customer_pack.zip
503 Kb Uploaded: 01-04-2000
ZIP file containing VHDL source files, VHDL test
benches, and CoolRunner CPLD compilation and
fitter files for the I2C Controller Design
For All Platforms
io_lvds.tar.gz
35 Kb Uploaded: 02-23-2000
HDL files supporting the use of registers for
LVDS and LVPECL I/O. Includes Verilog, VHDL and
Edif versions, as well as Synopsys and Synplify
formats.
Solution #: XAPP133
For All Unix
io_lvds.zip
130 Kb Uploaded: 02-23-2000
HDL files supporting the use of registers for
LVDS and LVPECL I/O. Includes Verilog, VHDL and
Edif versions, as well as Synopsys and Synplify
formats.
Solution #: XAPP133
For All Windows
xap4001v.zip 149KB 60 MHz Counters, 8 to 24 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4002v.zip 273KB Loadable Up/Down Counters, 8 to 24 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4003v.zip 196KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4004v.zip 350KB Loadable Binary Counters, 16, 32 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4005v.zip 101KB Register-Based FIFO for XC3000
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4006v.zip 84KB RAM-Based FIFO for XC4000
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4007v.zip 29KB Boundary Scan Emulator for XC3000
Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4009v.zip 40KB Frequency Synthesizer, FSK Modulator
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4021v.zip 114KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000.
V.1.00, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xapp001o.zip 100KB 60 MHz Counters, 8 to 24 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp002o.zip 187KB Loadable Up/Down Counters, 8 to 24 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp002v.zip 197KB Loadable Up/Down Counters, 8 to 24 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp003o.zip 311KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp003v.zip 375KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp004o.zip 225KB Loadable Binary Counters, 16, 32 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp004v.zip 282KB Loadable Binary Counters, 16, 32 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp005o.zip 68KB Register-Based FIFO for XC3000
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp005v.zip 87KB Register-Based FIFO for XC3000
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp006v.zip 84KB RAM-Based FIFO for XC4000
V.1.10, Implemented in Viewdraw-LCA
Unified Libraries
xapp007o.zip 26 Kb Boundary Scan Emulator for XC3000 v2.03,
Implemented in OrCAD 386+ V1.10 Unified
Libraries
Uploaded: 09-17-96
xapp007v.zip 33 Kb Boundary Scan Emulator for XC3000 v2.03,
Implemented in Viewdraw-LCA Unified Libraries
Uploaded: 09-17-96
xapp009o.zip 26KB Frequency Synthesizer, FSK Modulator
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp009v.zip 31KB Frequency Synthesizer, FSK Modulator
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp014o.zip 70KB Ultra-Fast Synchronous Counters v1.02,
Implemented in OrCAD 386+ V1.10 Unified
Libraries
Uploaded: 09-17-96
xapp014v.zip 61KB Ultra-Fast Synchronous Counters
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp021o.zip 90KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000. V.2.01, Implemented in OrCAD
386+ V1.10. Unified Libraries
xapp021v.zip 107KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000.
V.2.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp022o.zip 12KB Adders, Subtractors, and Accumulators in
XC3000. V.1.01, Implemented in OrCAD 386+
V1.10. Unified Libraries
xapp022v.zip 17KB Adders, Subtractors, and Accumulators in
XC3000. V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp023o.zip 64KB Accelerating Loadable Counters in XC4000
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp023v.zip 78KB Accelerating Loadable Counters in XC4000
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp026o.zip 23KB Multiplexers and Barrel Shifters in XC3000.
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp026v.zip 32KB Multiplexers and Barrel Shifters in XC3000.
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp028o.zip 5KB Frequency/Phase Comparator for Phase-Locked
Loops. V.1.01, Implemented in OrCAD 386+ V1.
Unified Libraries
xapp028v.zip 6KB Frequency/Phase Comparator for Phase-Locked
Loops. V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp029o.zip 6KB Serial Code Conversion Between BCD and Binary
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp029v.zip 8KB Serial Code Conversion Between BCD and Binary
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp036a.zip 6KB DRAM Controller for XC7200
ABEL and .pld Behavioral design files
for a 4-port memory controller. Fits
in an XC7236.
xapp044o.zip 39KB High-Performance RAM based FIFO
V.1.00, Implemented in Orcad 386+ V1.10
xapp048o.zip 39KB Xilinx Guided Tour for XACT 5.0
V.1.00, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp048v.zip 37KB Xilinx Guided Tour for XACT 5.0
V.1.00, Implemented in Viewdraw-LCA
Unified Libraries
xapp049a.zip 18KB Pentium/Synchronous DRAM Controller
Behavioral Design Example for EPLDs
ABEL files, V.1.00
xapp050o.zip 417KB Crossbar Switch in XC4000
V.1.00, Implemented in Orcad 386+ V1.10
xapp050v.zip 362KB Crossbar Switch in XC4000
V.1.00, Implemented in Viewdraw-LCA
Unified Libraries
xapp058.zip
2995 Kb Uploaded: 08-01-2001
This is the real .zip file with the reference
design information for XAPP058 "embedded
microprocessor ISP"
For All Platforms
xapp079.zip
8 Kb Uploaded: 08-14-2000
Xapp079 - VHDL/Verilog Design files and
testbench for 9500 device. Configuration utility
uploaded.
For All Platforms
SW Release: All
Category: Documentation, App Note
xapp131.zip
25 Kb Uploaded: 09-05-2002
This is the latest file for the reference design
for XAPP131. Only changes in fifoctlr_cc.v and
tb_x131v_cc.v
For All Platforms
xapp132.tar.gz
4 Kb Uploaded: 09-06-2000
This is the latest version of reference design
files for XAPP132 "DLL"
For All Unix
xapp132.zip
9 Kb Uploaded: 09-06-2000
This is the latest version of reference design
files for XAPP132 "DLL"
For All Windows
xapp134_verilog.tar.Z
830 Kb Uploaded: 10-16-2002
This is the reference design for XAPP134:Virtex
Synthesizable High Performance SDRAM Controller
it is the Verilog file for UNIX users
For All Unix
xapp134_verilog.zip
405 Kb Uploaded: 10-09-2002
This is the latest reference design file for
XAPP134. It is the verilog code for the app
note, please refer to the VHDL code if
necessary.
For All Platforms
xapp134_vhdl.tar.Z
4161 Kb Uploaded: 10-16-2002
This is the reference design for XAPP134:Virtex
Synthesizable High Performance SDRAM Controller
it is the VHDL file for UNIX users
For All Unix
xapp134_vhdl.zip
2567 Kb Uploaded: 10-09-2002
This is the latest reference design file for
XAPP134. It is the VHDL code for the app note,
please refer to the verilog code if necessary.
For All Platforms
xapp136.tar.gz
6 Kb Uploaded: 04-30-2002
This file contains both the pipelined and
flowthrough files for the ZBT SRAM reference
design for XAPP136.
For All Unix
xapp136.zip
13 Kb Uploaded: 04-30-2002
This file contains both the pipelined and
flowthrough files for the ZBT SRAM reference
design for XAPP136.
For All Platforms
xapp136_vhdl.tar.gz
6 Kb Uploaded: 08-31-1999
XAPP136 VHDL Design files for pipelined and
flowthrough ZBTSRAM controller.
For All Platforms
Category: Documentation, App Note
Dependencies: NONE
xapp136_vhdl.zip
9 Kb Uploaded: 08-31-1999
XAPP136 VHDL Design files for pipelined and
flowthrough ZBTSRAM controller.
For All Platforms
Category: Documentation, App Note
Dependencies: NONE
xapp137.zip
176 Kb Uploaded: 01-03-2000
This archive contains the following PromMAP
design source files for xapp137. These files are
meant to be used seperately from each other and
require no other dependency files. prom_map.v --
Verilog file. prom_map.vhd -- VHDL file.
Prommap.zip -- Foundation Schematic Project
Archive
For All Windows
Dependencies: none
xapp153.zip
8 Kb Uploaded: 06-04-1999
16-bit Status and Control Semaphore register
using Virtex Partial Reconfiguration (XAPP153),
implemented in PERL, Verilog and VHDL.
For All Platforms
SW Release: A1.5i/F1.5i
Category: Documentation, App Note
xapp154.tar.Z
3 Kb Uploaded: 05-04-2000
This is the reference design for XAPP154 in a
UNIX format. This is the Verilog version.
For All Unix
xapp154.zip
2 Kb Uploaded: 05-04-2000
This is the reference design for XAPP154 in a PC
format. This is the Verilog version.
For All Windows
xapp155.tar.Z
5 Kb Uploaded: 05-04-2000
This is the reference design for XAPP155 in a
UNIX format. This is the Verilog version.
For All Unix
xapp155.zip
4 Kb Uploaded: 05-04-2000
This is the reference design for XAPP155 in a PC
format. This is the Verilog version.
For All Windows
xapp164.tar.Z
69 Kb Uploaded: 08-11-1999
Tcl scripts for Using Xilinx and Synplify for
Incremental Designing (ECO)
For All Platforms
SW Release: A2.1i
Category: Documentation, App Note
xapp164.zip
46 Kb Uploaded: 08-11-1999
Tcl scripts for Using Xilinx and Synplify for
Incremental Designing (ECO)
For All Platforms
SW Release: A2.1i
Category: Documentation, App Note
xapp165.tar.Z
9 Kb Uploaded: 08-27-1999
Tcl scripts for using Xilinx and Exemplar for
Incremental Design (ECO)
For All Unix
SW Release: A2.1i
Category: Documentation, App Note
xapp165.zip
6 Kb Uploaded: 08-27-1999
Tcl scripts for using Xilinx and Exemplar for
Incremental Design (ECO)
For All Windows
SW Release: A2.1i
Category: Documentation, App Note
xapp166.tar.Z
2 Kb Uploaded: 02-22-2000
This is the perl script pad_stamp.pl to go along
with XAPP166, which must be donwloaded
seperately.
For All Platforms
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp166.zip
2 Kb Uploaded: 02-22-2000
This is the perl script pad_stamp.pl to go along
with XAPP166, which must be donwloaded
seperately.
For All Platforms
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp174.tar.Z
8 Kb Uploaded: 08-29-2000
XAPP174 Using Delay Locked Loops in Spartan-II
FPGAs, VHDL and Verilog CLKDLL examples.
For All Unix
SW Release: All
Category: Documentation, App Note
xapp174.zip
9 Kb Uploaded: 02-11-2002
XAPP174 Using Delay Locked Loops in Spartan-II
FPGAs, VHDL and Verilog CLKDLL examples.
For All Windows
SW Release: All
Category: Documentation, App Note
xapp175.tar.Z
19 Kb Uploaded: 12-13-1999
High Speed FIFOs In Spartan-II FPGAs (XAPP175),
implemented in VHDL and Verilog
For All Unix
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp175.zip
13 Kb Uploaded: 12-13-1999
High Speed FIFOs In Spartan-II FPGAs (XAPP175),
implemented in VHDL and Verilog
For All Platforms
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp192.zip
51 Kb Uploaded: 12-15-2000
This is the reference design for XAPP192
"Interfacing a Virtex-E device to a MIPs
Processor"
For All Platforms
xapp196.zip
61 Kb Uploaded: 12-15-2000
This is the second version in a day of XAPP196's
reference design. Interfacing a Virtex-E device
to a pentium processor.
For All Platforms
xapp197.zip
26 Kb Uploaded: 10-22-2001
This is the reference design files for XAPP197
"Triple Mode Redundancy Design Techniques for
Virtex FPGAs" VHDL only
For All Platforms
xapp198.zip
42 Kb Uploaded: 05-03-2001
This is the reference design for the
Synthesizable FPGA Interface for Retrieving ROM
Number from 1-Wire Devices.
For All Platforms
xapp199.tar.gz
9 Kb Uploaded: 08-07-2001
Design files for XAPP 199 - Writing efficient
testbenches. Vhdl and Verilog
For All Platforms
SW Release: All
xapp199.zip
15 Kb Uploaded: 08-07-2001
Design files for XAPP 199 - Writing efficient
testbenches. Vhdl and Verilog
For All Platforms
SW Release: All
xapp200.tar.gz
1596 Kb Uploaded: 09-07-2000
This is the 64 bit file for application note
XAPP200 "DDR SDRAM for Virtex Devices"
For All Unix
xapp200.zip
1689 Kb Uploaded: 09-07-2000
This is the 64 bit file for application note
XAPP200 "DDR SDRAM for Virtex Devices"
For All Windows
xapp200_16.tar.gz
947 Kb Uploaded: 09-07-2000
This is the 16 bit file for application note
XAPP200 "DDR SDRAM for Virtex Devices"
For All Unix
xapp200_16.zip
983 Kb Uploaded: 09-07-2000
This is the 16 bit file for application note
XAPP200 "DDR SDRAM for Virtex Devices"
For All Windows
xapp202.zip
20 Kb Uploaded: 01-13-2001
This is the new reference design for XAPP202
Designing Flexible, Fast CAMs with Virtex slices
For All Platforms
xapp203.tar.Z
62 Kb Uploaded: 12-11-1999
This is the UNIX version of both the VHDL &
Verilog Reference Designs for XAPP203
For All Unix
xapp203.zip
60 Kb Uploaded: 12-11-1999
This is the PC version of both the VHDL &
Verilog Reference Designs for XAPP203
For All Windows
xapp204.tar.Z
58 Kb Uploaded: 08-11-2000
This is the latest file for XAPP204 "CAM in
Block RAM". This replaces files from 9/99.
For All Unix
xapp204.zip
54 Kb Uploaded: 08-11-2000
This is the latest file for XAPP204 "CAM in
Block RAM". This replaces files from 9/99.
For All Windows
xapp205.zip
48 Kb Uploaded: 08-13-2002
This is the latest reference design file for
XAPP205: Data-Width Conversion FIFOs using
Virtex Block SelectRAM Memory
For All Platforms
xapp208.tar.gz
7 Kb Uploaded: 08-31-1999
The reference design for XAPP208 is in this
file. XAPP208 is the IDCT implementation in
Virtex Devices for MPEG Video Applications.
For All Unix
xapp208.zip
9 Kb Uploaded: 08-31-1999
The reference design for XAPP208 is in this
file. XAPP208 is the IDCT implementation in
Virtex Devices for MPEG Video Applications.
For All Windows
xapp209.tar.gz
6 Kb Uploaded: 07-22-2002
The latest .tar.gz files for XAPP209 "IEEE 802.3
Cyclic Redundancy Check"
For All Unix
xapp209.zip
11 Kb Uploaded: 07-22-2002
The latest .zip files for XAPP209 "IEEE 802.3
Cyclic Redundancy Check"
For All Platforms
xapp211.tar.gz
65 Kb Uploaded: 03-21-2000
This is the reference design file for the PN
Generator application note XAPP211. It includes
VHDL and Verilog code.
For All Unix
xapp211.zip
69 Kb Uploaded: 03-21-2000
This is the reference design file for the PN
Generator application note XAPP211. It includes
VHDL and Verilog code.
For All Windows
xapp212.tar.gz
2 Kb Uploaded: 05-08-2000
This is the Matched Filter implementation files
for XAPP212. This is VHDL code
For All Unix
xapp212.zip
3 Kb Uploaded: 05-08-2000
This is the VHDL implementation code for XAPP212
Matched Filters. See application note for
further details
For All Windows
xapp213.zip
237 Kb Uploaded: 12-16-2002
This is the file for XAPP213 "PicoBlaze 8-Bit
MicroController for Virtex-E and Spartan II/IIE
Devices" These are VHDL files only.
For All Platforms
xapp214_vhdl.tar.Z
18 Kb Uploaded: 07-26-2000
This is the vhdl reference design files for
XAPP214 "Quad Data Rate (QDR) SRAM Interface
For All Unix
xapp214_vhdl.zip
11 Kb Uploaded: 07-26-2000
This is the vhdl reference design files for
XAPP214 "Quad Data Rate (QDR) SRAM Interface
For All Windows
xapp215.tar.gz
5 Kb Uploaded: 08-03-2000
This is the newest file for XAPP215 "Design Tips
for HDL Implementation of Arithmetic Functions"
For All Unix
xapp215.zip
9 Kb Uploaded: 08-03-2000
This is the newest file for XAPP215 "Design Tips
for HDL Implementation of Arithmetic Functions"
For All Windows
xapp217.tar.gz
3 Kb Uploaded: 01-09-2001
This is an updated version of the Gold Code
Generator reference design for XAPP217
For All Unix
xapp217.zip
4 Kb Uploaded: 01-09-2001
This is an updated version of the Gold Code
Generator reference design for XAPP217
For All Windows
xapp219.tar.gz
49 Kb Uploaded: 02-13-2001
This file has Matlab additions for XAPP219 "
Transposed Form FIR Filters"
For All Unix
xapp219.zip
50 Kb Uploaded: 02-13-2001
This file has Matlab additions for XAPP219 "
Transposed Form FIR Filters"
For All Windows
xapp220.tar.gz
4 Kb Uploaded: 01-12-2001
This is the tar.gz file for xapp220 "Linear
Feedback Shift Registers for Wireless
Applications"
For All Unix
xapp220.zip
6 Kb Uploaded: 12-12-2000
This is the reference design file for XAPP220
"LFSRs as funtional blocks in Wireless
applications".
For All Platforms
xapp222.zip
15 Kb Uploaded: 09-27-2000
This is the reference design for XAPP222.
Designing Convolutional Interleavers with Virtex
Devices
For All Windows
xapp224.zip
45 Kb Uploaded: 03-28-2002
This is version 21 of the reference design for
XAPP224 "data recovery" version 2.1
For All Platforms
xapp225.zip
44 Kb Uploaded: 04-24-2002
This is the latest version to go with XAPP225
v1.1 of the application note "Data to Clock
Phase Alignment"
For All Platforms
xapp228.zip
30 Kb Uploaded: 09-24-2002
This is the reference design for XAPP228 "Quad-
Port Memories in Virtex Devices"
For All Platforms
xapp233.zip
316 Kb Uploaded: 12-20-2000
This is the reference design file for XAPP233
and includes XAPP238's information.
For All Platforms
xapp242.tar.gz
22 Kb Uploaded: 08-01-2001
This is the latest vhdl and verilog files for
XAPP242 "LARA CAM interface"
For All Unix
xapp242.zip
28 Kb Uploaded: 08-01-2001
This is the latest vhdl and verilog files for
XAPP242 "LARA CAM interface"
For All Platforms
xapp246.zip
286 Kb Uploaded: 12-15-2000
This is the reference design for XAPP246
"PowerPC 60X Bus Interface to a Virtex-E Device"
For All Platforms
xapp248.zip
228 Kb Uploaded: 01-07-2002
This is the reference design file for XAPP248
"digital video test pattern generators"
For All Platforms
xapp250.zip
8 Kb Uploaded: 10-21-2002
This is the reference design file in Verilog
only for XAPP250 "Clock and Data Recovery With
Coded Data Streams" The VHDL file will be posted
in 11/02
For All Platforms
xapp253.zip
45 Kb Uploaded: 07-16-2002
This is the reference design file for XAPP253
version 2.0 "Synthesizable 400Mb/s DDR SDRAM
controller
For All Platforms
xapp254.zip
32 Kb Uploaded: 01-13-2001
This is the reference design file for XAPP254
"The Virtex-II SiberBridge"
For All Platforms
xapp256.zip
7 Kb Uploaded: 06-07-2001
This is the reference design file for xapp256
"Sync FIFO in a Shift Register"
For All Platforms
xapp258.zip
25 Kb Uploaded: 09-05-2002
This is the latest file for the reference design
for XAPP258. Only changes in fifoctlr_cc_v2.v
and tb_x258v_cc.v.
For All Platforms
xapp260.zip
56 Kb Uploaded: 11-30-2001
This is the reference design for XAPP260 Virtex-
II block RAMs for high performance read/write
CAMs
For All Platforms
xapp261.zip
49 Kb Uploaded: 12-12-2002
This is the latest file with updated VHDL for
XAPP261"Data-width Conversion FIFOs using the
Virtex-II Block RAM Memory".
For All Platforms
xapp262.zip
56 Kb Uploaded: 12-12-2002
Added glbl.v file and some unisims primitives
for simulation purposes. Changed synchronous R_n
and W_n path. Changed testbench timing. Fixed
address synch in Verilog. Verified 5.1i SP2.
For All Platforms
xapp265.zip
325 Kb Uploaded: 07-05-2002
This is the latest reference design file for
XAPP265 "High-Speed Data Serialization and
Deserialization (840 Mb/x LVDS)
For All Platforms
xapp266.zip
49 Kb Uploaded: 02-26-2002
This is the reference design file for XAPP266
"Synthesizable FCRAM Controller" v1.0
For All Platforms
xapp267.zip
12 Kb Uploaded: 07-18-2002
This is the latest file for XAPP267 "Parity
Generation and Validation in Virtex-II Devices"
For All Platforms
xapp268.zip
39 Kb Uploaded: 01-10-2003
This is a new reference design update for
XAPP268 Active Phase Alignment
For All Platforms
xapp270.zip
32 Kb Uploaded: 08-03-2001
This is the reference design files for XAPP270
"High-Speed DES and Triple DES
Encryptor/Decryptor".
For All Platforms
xapp283.zip
107 Kb Uploaded: 07-23-2002
This is the reference design file for XAPP283
"Color space converter".
For All Platforms
xapp284.zip
60 Kb Uploaded: 07-23-2002
This is the reference design files for XAPP 284
"3x3 Matrix Multiplier for 3D Graphics and
Video" v1.0
For All Platforms
xapp288.zip
67 Kb Uploaded: 10-25-2001
This is the reference design file for XAPP288 "
SDI Video Decoder" it includes both VHDL and
Verilog versions
For All Platforms
xapp289.zip
32 Kb Uploaded: 04-01-2002
this is a new file for the CSIX application note
XAPP289. It has be updated to include Virtex-II
Pro simulations.
For All Platforms
xapp290.zip
8151 Kb Uploaded: 05-10-2002
These are the reference design files for XAPP290
"Two flows for partial reconfiguration: Module
based and small bit manipulations"
For All Platforms
xapp291.zip
27 Kb Uploaded: 12-10-2002
Latest file for XAPP291 "Self-addressing FIFO"
very minor changes, and tidied up a bit.
For All Platforms
xapp298.zip
75 Kb Uploaded: 11-02-2001
This is the reference design file for XAPP298
"Serial Digital Interface (SDI) Video Encoder"
in both VHDL and Verilog
For All Platforms
xapp299.zip
201 Kb Uploaded: 05-16-2002
This is the reference design for XAPP299 "SDI:
Ancillary Data and EDH Processors"
For All Platforms
xapp409.tar.gz
139 Kb Uploaded: 09-20-2001
Design file for XAPP 409 - Simulating a 3.1i
Core Generator VHDL Design.
For All Unix
SW Release: A3.1i/F3.1i
Category: Documentation, App Note
xapp409.zip
160 Kb Uploaded: 09-20-2001
Design Files for XAPP409 - Simulating a 3.1i
Core Generator VHDL Design
For All Windows
SW Release: A3.1i/F3.1i
Category: Documentation, App Note
xapp410.tar.gz
104 Kb Uploaded: 09-20-2001
Design files for XAPP410 - Simulating a 3.1i
Core Generator Verilog Design
For All Unix
SW Release: A3.1i/F3.1i
Category: Documentation, App Note
xapp410.zip
109 Kb Uploaded: 09-20-2001
Design Files for XAPP410 - Simulating a 3.1i
Core Generator Verilog Design
For All Windows
SW Release: A3.1i/F3.1i
Category: Documentation, App Note
xapp411.tar.gz
3 Kb Uploaded: 10-31-2001
PrimeTime and TCL scripts to be used in
conjunction with Xilinx application note #411
For All Unix
SW Release: F4.1i
Category: Documentation, App Note
xapp416.zip
176 Kb Uploaded: 08-06-2002
Example project directory for XAPP416 which
descibes how to use the RPM Grid feature to
create an RPM macro to control BLKRAM to FF
timing paths.
For All Platforms
xapp502.zip
14 Kb Uploaded: 01-08-2002
The reference design for "Using a Microprocessor
to Configure Xilinx FPGAs via Slave Serial or
SelectMap Mode"
For All Platforms
xapp606.zip
123 Kb Uploaded: 12-20-2001
This file is a revised version of the reference
design for XAPP606 "XGMII"
For All Platforms
xapp607.zip
30 Kb Uploaded: 05-29-2002
This is the most recent file for XAPP607
"Virtex-II Connection to a High Speed Serial
Device (TLK2501)"
For All Platforms
xapp608.zip
175 Kb Uploaded: 07-01-2002
This is the reference design file for XAPP608
"DDR SDRAM DIMM Interface for Virtex-II devices"
For All Platforms
xapp610.zip
65 Kb Uploaded: 03-06-2002
This is the reference design file for XAPP610
"DCT Spatial to Transform Domain"
For All Platforms
xapp611.zip
54 Kb Uploaded: 03-20-2002
This is the reference design files for XAPP611
"IDCT Transform to Spatial Domain"
For All Platforms
xapp622.zip
63 Kb Uploaded: 07-09-2002
This is the latest reference design file with
all the missing files attached for XAPP622.
For All Platforms
xapp623.zip
5 Kb Uploaded: 08-08-2002
This is the Spice model file referenced in
XAPP623 "Power Distribution System (PDS) Design:
using bypass/decoupling capacitors
For All Platforms
xapp625.zip
91 Kb Uploaded: 03-12-2002
This is the reference design file for XAPP625
"SDI: Video Decoder Flywheel"
For All Platforms
xapp626.zip
169 Kb Uploaded: 05-13-2002
This is the corrected reference design file for
XAPP626 "Velio SerDes Interface"
For All Platforms
xapp627.zip
202 Kb Uploaded: 12-16-2002
This is the file for XAPP627 "PicoBlaze 8-Bit
MicroController for Virtex-II Series Devices"
These are VHDL files only.
For All Platforms
xapp634.zip
50 Kb Uploaded: 06-24-2002
This reference design is for application note
XAPP634 "Analog Devices TigerSHARC Link"
For All Platforms
xapp636.zip
19 Kb Uploaded: 11-01-2002
This is the latest ref. design file for XAPP636
"Optimal Pipelining of the I/O Ports of Virtex-
II multipliers"
For All Platforms
xapp637.zip
402 Kb Uploaded: 09-12-2002
This is the reference design file for XAPP637
"Color Space Converter RGB to YCBCR"
For All Platforms
xapp639.zip
247 Kb Uploaded: 01-13-2003
XAPP639 is the reference design for the
HyperTransport Lite Interface for Virtex-II
FPGAs.
For All Platforms
xapp640.zip
9502 Kb Uploaded: 07-29-2002
The Reference Design for XAPP640. This design
must be used with the V2PDK. All of the
supporting files are in the V2PDK.
For All Platforms
SW Release: F4.1i
Category: Documentation, App Note
xapp642.zip
39 Kb Uploaded: 10-21-2002
This is the reference design file for XAPP642
"Relocating code and data for embedded systems"
For All Platforms
xapp644.zip
13606 Kb Uploaded: 08-01-2002
This is the reference design for XAPP644 "PLB
vs. OCM Comparison Using the Packet Processor
Software" v1.0
For All Platforms
xapp649.zip
6 Kb Uploaded: 05-14-2002
This is the XAPP649 "SONET Rate Conversion in
Virtex-II Pro Devices" version 1.1
For All Platforms
xapp651.zip
81 Kb Uploaded: 11-12-2002
The lastest XAPP651 reference design file for
SONET and OTU Scramblers/Descramblers
For All Platforms
xapp652.zip
46 Kb Uploaded: 11-15-2002
This is the reference design file for XAPP652
"Word Alignment and SONET/SDH Deframing"
For All Platforms
xapp655.zip
53 Kb Uploaded: 11-19-2002
This is the reference design for XAPP655 "Mixed
Version IP Router (MIR).
For All Platforms
xapp657.zip
128 Kb Uploaded: 08-15-2002
This is the reference design file for XAPP657
"Virtex-II Pro RAID-5 Parity and Data
Regeneration Controller" v1.0
For All Platforms
xapp660.zip
129 Kb Uploaded: 01-10-2003
This is the reference design file for XAPP660:
Partial Reconfiguration of RocketIO Pre-emphasis
and Differential Swing Control Attributes
For All Platforms
xapp661.zip
165 Kb Uploaded: 01-10-2003
This is the reference design file for both
XAPP661:RocketIO Transceiver Bit-Error Rate
Tester and XAPP662:In-Circuit Partial
Reconfiguration of RocketIO Attributes"
For All Platforms