1. Overrall Structure

--  Context Clauses

--  Library Clause

--  Use Clause

--	Library Units

--  Package Declaration (optional)

--  Package Body (optional)

--  Entity Declaration

--  Architecture Body

2. Full Design : Counter

-- MAX+plus II VHDL Template

-- Clearable loadable enablable counter

ENTITY __entity_name IS

PORT

(

__data_input_name	: IN	INTEGER RANGE 0 TO __count_value;

__clk_input_name	: IN	STD_LOGIC;

__clrn_input_name	: IN	STD_LOGIC;

__ena_input_name	: IN	STD_LOGIC;

__ld_input_name	: IN	STD_LOGIC;

__count_output_name	: OUT	INTEGER RANGE 0 TO __count_value

);

END __entity_name;

ARCHITECTURE a OF __entity_name IS

SIGNAL	__count_signal_name	: INTEGER RANGE 0 TO __count_value;

BEGIN

PROCESS (__clk_input_name, __clrn_input_name)

BEGIN

IF __clrn_input_name = '0' THEN

__count_signal_name <= 0;

ELSIF (__clk_input_name'EVENT AND __clk_input_name = '1') THEN

IF __ld_input_name = '1' THEN

__count_signal_name <= __data_input_name;

ELSE

IF __ena_input_name = '1' THEN

ount_signal_name <= __count_signal_name + 1;

ELSE

__count_signal_name <= __count_signal_name;

END IF;

END IF;

END IF;

END PROCESS;

__count_output_name <= __count_signal_name;

END a;

3. Full Design : Flipflop

-- MAX+plus II VHDL Template

-- Clearable flipflop with enable

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY __entity_name IS

PORT

(

__d_input_name	: IN	STD_LOGIC;

__clk_input_name	: IN	STD_LOGIC;

__clrn_input_name	: IN	STD_LOGIC;

__ena_input_name	: IN	STD_LOGIC;

__q_output_name	: OUT	STD_LOGIC

);

END __entity_name;

ARCHITECTURE a OF __entity_name IS

SIGNAL	__q_signal_name	: STD_LOGIC;

BEGIN

PROCESS (__clk_input_name, __clrn_input_name)

BEGIN

IF __clrn_input_name = '0' THEN

__q_signal_name <= '0';

ELSIF (__clk_input_name'EVENT AND __clk_input_name = '1') THEN

IF __ena_input_name = '1' THEN

__q_signal_name <= __d_input_name;

ELSE

__q_signal_name <= __q_signal_name;

END IF;

END IF;

END PROCESS;

__q_output_name <= __q_signal_name;

END a;

4. Full Design :  Tri-State Buffer

-- MAX+plus II VHDL Template

-- Tri-State Buffer

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY __entity_name IS

PORT

(

__oe_input_name	: IN	STD_LOGIC;

__data_input_name	: IN	STD_LOGIC;

__tri_output_name	: OUT	STD_LOGIC

);

END __entity_name;

ARCHITECTURE a OF __entity_name IS

BEGIN

PROCESS (__oe_input_name, __data_input_name)

BEGIN

IF __oe_input_name = '0' THEN

__tri_output_name <= 'Z';

ELSE

__tri_output_name <= __data_input_name;

END IF;

END PROCESS;

END a;

5. Architecture Body

ARCHITECTURE a OF __entity_name IS

SIGNAL __signal_name : STD_LOGIC;

SIGNAL __signal_name : STD_LOGIC;

BEGIN

--  Process Statement

--  Concurrent Procedure Call

--  Concurrent Signal Assignment

--  Conditional Signal Assignment

--  Selected Signal Assignment

--  Component Instantiation Statement

--  Generate Statement

END a;

6. Case Statement

CASE __expression IS

WHEN __constant_value =>

__statement;

__statement;

WHEN __constant_value =>

__statement;

__statement;

WHEN OTHERS =>

__statement;

__statement;

END CASE;

7. Component Declaration

COMPONENT __component_name

PORT(

__input_name, __input_name	: IN	STD_LOGIC;

__bidir_name, __bidir_name	: INOUT	STD_LOGIC;

__output_name, __output_name	: OUT	STD_LOGIC);

END COMPONENT;

8. Component Instantiation Statement

__instance_name: __component_name

PORT MAP (	__formal_parameter => __actual_parameter,

__formal_parameter => __actual_parameter);

9. Concurrent Procedure Call

__label: __procedure_name(__actual_parameter, __actual_parameter);

10. Concurrent Signal Assignment Statement

__signal <= __expression;

11. Conditional Signal Assignment

__label:

__signal <= __expression WHEN __boolean_expression ELSE

__expression WHEN __boolean_expression ELSE

__expression;

12. Constant Declaration

CONSTANT __constant_name : __type_name := __constant_value;

13. Entity Declaration

ENTITY __entity_name IS

PORT(

__input_name, __input_name             :  IN           STD_LOGIC;

__input_vector_name         :  IN   STD_LOGIC_VECTOR(__high downto __low);

__bidir_name, __bidir_name	:  INOUT	STD_LOGIC;

__output_name, __output_name   :  OUT	STD_LOGIC);

END __entity_name;

14. For Statement

__loop_label:

FOR __index_variable IN __range LOOP

__statement;

__statement;

END LOOP __loop_label;

15. Generate Statment ( For Statement)

__generate_label:

FOR __index_variable IN __range GENERATE

__statement;

__statement;

END GENERATE;

16. Generate Statment ( If Statement)

__generate_label:

IF __expression GENERATE

__statement;

__statement;

END GENERATE;

17. If Statement

IF __expression THEN

__statement;

__statement;

ELSIF __expression THEN

__statement;

__statement;

ELSE

__statement;

__statement;

END IF;

18. Library Clause

LIBRARY __library_name;

19. Package Declaration

PACKAGE __package_name IS

--  Type Declaration

--  Subtype Declaration

--  Constant Declaration

--  Signal Declaration

--  Component Declaration

END __package_name;

20. Procedure Call Statement

__procedure_name(__actual_parameter, __actual_parameter);

21. Process (Combinatorial Logic)

__process_label:

PROCESS (__signal_name, __signal_name, __signal_name)

VARIABLE __variable_name : STD_LOGIC;

VARIABLE __variable_name : STD_LOGIC;

BEGIN

--  Signal Assignment Statement

--  Variable Assignment Statement

--  Procedure Call Statement

--  If Statement

--  Case Statement

--  Loop Statement

END PROCESS __process_label;

22. Process (Sequential Logic)

__process_label:

PROCESS

VARIABLE __variable_name : STD_LOGIC;

VARIABLE __variable_name : STD_LOGIC;

BEGIN

WAIT UNTIL __clk_signal = '1';

--  Signal Assignment Statement

--  Variable Assignment Statement

--  Procedure Call Statement

--  If Statement

--  Case Statement

--  Loop Statement

END PROCESS __process_label;

23. Selected Signal Assignment Statement

__label:

WITH __expression SELECT

__signal <= __expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value;

24. Signal Declaration

SIGNAL __signal_name : __type_name;

25. Signal Assignment Statement

__signal_name <= __expression;

26. State Machine with Asynch. Reset

ENTITY __machine_name IS

PORT(

clk	: IN	STD_LOGIC;

reset	: IN	STD_LOGIC;

__input_name, __input_name	: IN	STD_LOGIC;

__output_name, __output_name	: OUT	STD_LOGIC);

END __machine_name;

ARCHITECTURE a OF __machine_name IS

TYPE STATE_TYPE IS (__state_name, __state_name, __state_name);

SIGNAL state: STATE_TYPE;

BEGIN

PROCESS (clk)

BEGIN

IF reset = '1' THEN

state <= _state_name;

ELSIF clk'EVENT AND clk = '1' THEN

CASE state IS

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

END CASE;

END IF;

END PROCESS;

WITH state SELECT

__output_name	<=	__output_value	WHEN	__state_name,

__output_value	WHEN	__state_name,

__output_value	WHEN	__state_name;

END a;

27. State Machine without Asynch. Reset

ENTITY __machine_name IS

PORT(

clk	: IN	STD_LOGIC;

__input_name, __input_name	: IN	STD_LOGIC;

__output_name, __output_name	: OUT	STD_LOGIC);

END __machine_name;

ARCHITECTURE a OF __machine_name IS

TYPE STATE_TYPE IS (__state_name, __state_name, __state_name);

SIGNAL state: STATE_TYPE;

BEGIN

PROCESS (clk)

BEGIN

IF clk'EVENT AND clk = '1' THEN

CASE state IS

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

WHEN __state_name =>

IF __condition THEN

state <= __state_name;

END IF;

END CASE;

END IF;

END PROCESS;

WITH state SELECT

__output_name	<=	__output_value	WHEN	__state_name,

__output_value	WHEN	__state_name,	__output_value	WHEN	__state_name;

END a;

28. Subtype

SUBTYPE __subtype_name IS __type_name RANGE __low_value TO __high_value;

SUBTYPE __array_subtype_name IS __array_type_name(__high_index DOWNTO __low_index);

29. Type

TYPE __enumerated_type_name IS (__name, __name, __name);

TYPE __range_type_name IS RANGE __integer TO __integer;

TYPE __array_type_name IS ARRAY (INTEGER RANGE <>) OF __type_name;

TYPE __array_type_name IS ARRAY (__integer DOWNTO __integer) OF __type_name;

30. Use Clause

USE __library_name.__package_name.ALL;

31. Wait Statement

WAIT UNTIL __clk_name = '1';

32. Variable Declaration Statement

VARIABLE __variable_name : __type_name;

33. Variable Assignment Statement

__variable_name := __expression;

34. While Statement

__loop_label:

WHILE __boolean_expression LOOP

__statement;

__statement;

END LOOP __loop_label;

위에 있는 것들은 VHDL에 사용할 문법들입니다. 조금 많아보이죠. 이것은 Altera의 문법들입니다. VHDL이 하드웨어 표준 언어이지만 각 회사들마다 조금씩 문법의 차이는 있습니다. 그것은 숙지하시고 문법은 맞는데 컴파일이 되지 않는다고 불평하지 마세요. 실예로 Lodecap에서 모든 컴파일과 시뮬레이션을 마친 상태에서 그 소스를 Altera에서 실행한 적이 있습니다. 그런데 상태 이름이 Next였습니다. 그런데 MaxPlusⅡ에서는 Next가 Reserved word였습니다. 그래서 몇 일을 고생한 적이 있습니다. 자기가 사용하는 툴에 대해서는 어느 정도의 지식이 있어야 합니다. 툴에 대한 설명은 제가 할 수 있는 것이 못됩니다.

그러니 각 회사 사이트에 접속하면 Manual을 구할 수 있습니다. 그리고 공개용 버전도 어느 정도 구할 수 있을 것입니다. 직접 접속해 보시는 것도 좋은 방법입니다.

위에 있는 문법들을 한 번 잘살펴 보시고 다음 시간부터 사용되는 문법들과 잘 적용해 보시기를 바랍니다.