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Some of the LPM functions (primarily the memory functions) and all of the non-LPM megafunctions have been moved to the megafun file.


Megafunctions/LPM

MAX+PLUS II offers a variety of megafunctions, including LPM functions and other parameterized functions.

Use the following descriptions to understand the functionality of the megafunctions and LPMs in the MAX+PLUS II software. For terminology, see the Altera MAX+PLUS help.

For the exact FPGA Compiler II / FPGA Express port and parameter definitions, see this file  in your installed directory:
 lpm_components.vhd text file\Synopsys\FPGA_Compiler_II/FPGA_Express\lib\packages\LPM.

Megafunctions are listed here by function. Functions indicated by an asterisk (*) are provided for backward compatibility only.

Gates

lpm_and	lpm_inv
lpm_bustri	lpm_mux
lpm_clshift	lpm_or
lpm_constant	lpm_xor
lpm_decode	mux
busmux
Arithmetic Components

divide*	lpm_compare
lpm_abs	lpm_counter
lpm_add_sub	lpm_divide
lpm_mult
Storage Components

altdpram*	lpm_latch
csfifo	lpm_shiftreg
dcfifo*	lpm_ram_dp
scfifo*	lpm_ram_dq
csdpram	lpm_ram_io
lpm_ff	lpm_rom
lpm_fifo	lpm_dff*
lpm_fifo_dc	lpm_tff*
Other Functions

clklock	pll
ntsc
Altera also offers a variety of MegaCore/OpenCore functions. These functions are available from Altera’s world-wide web site at http://www.altera.com.


lpm_abs (Parameterized Absolute Value Megafunction)
lpm_abs (Absolute Value)

Parameterized Absolute Value Megafunction

Altera recommends using the lpm_abs function to replace all other types of absolute value functions, including old-style macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_abs (data[LPM_WIDTH-1..0])

WITH (LPM_WIDTH, ADDERTYPE)

RETURNS (result[LPM_WIDTH-1..0], overflow);

VHDL Component Declaration:

COMPONENT lpm_abs

GENERIC (LPM_WIDTH : POSITIVE;

LPM_TYPE: STRING := "LPM_ABS";

LPM_HINT: STRING := "UNUSED");

port (DATA : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

overflow: OUT STD_LOGIC);

END COMPONENT;

The ADDERTYPE parameter is supported only for backward compatibility with pre-MAX+PLUS II version 8.1 designs, but should be not be used in newer projects.

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	Yes	Signed number.	Input port LPM_WIDTH wide.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Absolute value of data[].	Output port LPM_WIDTH wide.
overflow	No	High if data = -2 ^ (LPM_WIDTH-1).	Two’s complement allows one more negative number than positive. The overflow port detects that singular instance and goes high to indicate that no positive equivalent exists.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and result[] ports.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Inputs	|	Outputs

data[LPM_WIDTH-1..0]	|	result[LPM_WIDTH-1..0]	overflow

>= 0	|	data[LPM_WIDTH-1..0]	0

< 0	|	data[LPM_WIDTH-1..0]	0

100...	|	100...	1

Resource Usage:

The following table summarizes the resource usage for an lpm_abs function used to implement a 16-bit absolute value converter with an up/down control and an overflow output.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	23	31.6 	Note (1)

Speed	|	16	17	19.4 	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	17 (0)	12.5 	Note (1)

Numbers of shared expanders used are shown in parentheses ( ).

See also:

Megafunctions/LPM


Note (1)

Worst-case pin-to-pin speed.


lpm_add_sub (Parameterized Adder/Subtractor Megafunction)
lpm_add_sub (Adder/Subtractor)

Parameterized Adder/Subtractor Megafunction

Altera recommends using the lpm_add_sub function to replace all other types of adder/subtractor functions, including old-style adder/subtractor macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

1.	In MAX+PLUS II version 7.0, the implementation of the lpm_add_sub function changed so that the carry chain that generates the cout output is no longer terminated with a logic cell, in order to improve performance. However, if the cout pin feeds logic that subsequently causes the Compiler to ignore carry chains, the lpm_add_sub function’s performance may decrease. If the Compiler indicates that it has ignored carry chains and the circuit performance decreases, you should feed the cout signal through an LCELL buffer to preserve the carry chain.

2.	The default value for the LPM_REPRESENTATION parameter used in the lpm_add_sub function changed in MAX+PLUS II version 6.2 from UNSIGNED to SIGNED. The value of this parameter has an effect only if you use the overflow output. If your pre-version 6.2 design(s) use the overflow output and you did not specify an explicit parameter value for LPM_REPRESENTATION, you should explicitly set it to UNSIGNED to obtain the same functionality.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_add_sub (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0], add_sub, clock, aclr, clkn)

WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION, ONE_INPUT_IS_CONSTANT, LPM_PIPELINE, MAXIMIZE_SPEED)

RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

VHDL Component Declaration:

COMPONENT lpm_add_sub

GENERIC (LPM_WIDTH: POSITIVE;

LPM_REPRESENTATION: STRING := "SIGNED";

LPM_DIRECTION: STRING := "UNUSED";

LPM_PIPELINE: INTEGER := 0;

LPM_TYPE: STRING := "LPM_ADD_SUB";

LPM_HINT: STRING := "UNUSED");

PORT (dataa, datab: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

aclr, clock, cin: IN STD_LOGIC := '0';

add_sub: IN STD_LOGIC := '1';

clken: IN STD_LOGIC := '1';

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

cout, overflow: OUT STD_LOGIC);

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
cin	No	Carry-in to the low-order bit.	If omitted, the default is 0.
dataa[]	Yes	Augend/Minuend.	Input port LPM_WIDTH wide.
datab[]	Yes	Addend/Subtrahend.	Input port LPM_WIDTH wide.
add_sub	No	If the signal is high, the operation = dataa[]+datab[] +cin. If the signal is low, the operation = dataa[]-datab[] +cin-1.	If the LPM_DIRECTION parameter is used, add_sub cannot be used. If omitted, the default is "ADD". Altera recommends that you use the LPM_DIRECTION parameter to specify the operation of the lpm_add_sub function, rather than assigning a constant to the add_sub port.
clock	No	Clock for pipelined usage.	The clock port provides pipelined operation for the lpm_add_sub function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.
clken	No	Clock enable for pipelined usage.	If omitted, the default is 1.
aclr	No	Asynchronous Clear for pipelined usage.	The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0’s, asynchronously to the clock signal.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	dataa[] +datab[] +cin or dataa[] -datab[] +cin-1.	Output port LPM_WIDTH wide.
cout	No	Carry-out (borrow-in) of the MSB. Note 1	If overflow is used, cout cannot be used. The cout port has a physical interpretation as the carry-out (borrow-in) of the MSB. cout is most meaningful for detecting overflow in "UNSIGNED" operations.
overflow	No	Result exceeds available precision. Note 2	If overflow is used, cout cannot be used. The overflow port has a physical interpretation as the XOR of the carry-in to the MSB with the carry-out of the MSB. overflow is meaningful only when the LPM_REPRESENTATION parameter value is "SIGNED".

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the dataa[], datab[], and result[] ports.
LPM_DIRECTION	String	No	Values are "ADD", "SUB", and "UNUSED". If omitted, the default is "DEFAULT", which directs the parameter to take its value from the add_sub port. The add_sub port cannot be used if LPM_DIRECTION is used. Altera recommends that you use the LPM_DIRECTION parameter to specify the operation of the lpm_add_sub function, rather than assigning a constant to the add_sub port.
LPM_REPRESENTATION	String	No	Type of addition performed: "SIGNED", "UNSIGNED", or "UNUSED". If omitted, the default is "SIGNED".
LPM_PIPELINE	Integer	No	Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
ONE_INPUT_IS_CONSTANT	String	No	Altera-specific parameter. Values are "YES", "NO", and "UNUSED". Provides greater optimization if one input is constant. If omitted, the default is "NO".
MAXIMIZE_SPEED	Integer	No	Altera-specific parameter. You can specify a value between 0 and 10. If used, MAX+PLUS II attempts to optimize a specific instance of the lpm_add_sub function for speed rather than area, and overrides the setting of the Optimize option in the Global Project Logic Synthesis dialog box (Assign menu). If MAXIMIZE_SPEED is unused, the value of the Optimize option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the Compiler will optimize lpm_add_sub megafunctions for higher speed; if the setting is 5 or less, the Compiler will optimize for smaller area.

Function:

UNSIGNED

Inputs	|	Outputs

add_sub	dataa[LPM_WIDTH-1..0]	datab[LPM_WIDTH-1..0]	|	cout, result[LPM_WIDTH-1..0]	|	overflow

1	a	b	|	a + b + cin	|	cout

0	a	b	|	a - b + cin -1	|	!cout

SIGNED

Inputs	|	Outputs

add_sub	dataa[LPM_WIDTH-1..0]	datab[LPM_WIDTH-1..0]	|	cout, sum[LPM_WIDTH-1..0]	|	overflow

1	a	b	|	a + b + cin 	|	a >= 0 and b >= 0 and

|	|	sum < 0

|	|	or a < 0 and b < 0 and

|	|	sum >= 0

|	|

0	a	b	|	a - b +cin -1	|	a >= 0 and b < 0 and

|	|	sum < 0

|	|	or a < 0 and b >= 0 and

|	|	sum >= 0

Resource Usage:

The following table summarizes the resource usage for an lpm_add_sub megafunction used to implement a 16-bit unsigned adder with a carry-in input and a carry-out output. Logic cell usage scales linearly in proportion to adder width.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	45	53	Note (1)

Speed	|	16	18	17	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	28 (22)	23	Note (2)

Numbers of shared expanders used are shown in parentheses ( ).

See also:

Megafunctions/LPM


Note (1)

Speed estimates are for an EPF8282A-2 device.


Note (2)

Speed estimates are for an EPM7128E-7 device.


Note (1)

Value	ADD Operation	SUB Operation

"UNSIGNED"	dataa + datab + cin) > 2 ^ (LPM_WIDTH-1)-1	Normal subtract. However, if cout = 0, then (DATAA - DATAB - CIN) < 0.
"SIGNED"	Normal result of adding two negative numbers, or possible overflow.	Normal result when subtracting a positive number from a negative number, or possible overflow.


Note (2)

Value	ADD Operation	SUB Operation

"UNSIGNED"	Not meaningful.	Not meaningful.
"SIGNED"	(dataa + datab + cin) > 2 ^ (LPM_WIDTH-1)-1 or: (dataa + datab + cin) < -2 ^ (LPM_WIDTH-1)	(dataa - datab - cin) > 2 ^ (LPM_WIDTH-1)-1 or: (dataa - datab - cin) < -2 ^ (LPM_WIDTH-1)


lpm_and (Parameterized AND Gate Megafunction)
lpm_and (AND Gate)

Parameterized AND Gate Megafunction

Altera recommends using AND primitives or operators rather than lpm_and for easier implementation and to improve compilation time. However, lpm_and may be useful if you need parameterized inputs.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_and (data[LPM_SIZE-1..0][LPM_WIDTH-1..0])

WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[LPM_WIDTH-1..0])

VHDL Component Declaration:

COMPONENT lpm_and

GENERIC (LPM_WIDTH: POSITIVE;

LPM_SIZE: POSITIVE;

LPM TYPE: STRING := "LPM_AND";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[][]	Yes	Data input to the AND gate.	Input port LPM_SIZE x LPM_WIDTH wide.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Each result[] bit is the result of the AND operators.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[][] and result[] ports. Number of AND gates.
LPM_SIZE	Integer	Yes	Number of inputs to each AND gate. Number of input buses.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Each lpm_and function defines LPM_WIDTH AND gates. Each AND gate has the following function:

Function:

Inputs	|	Outputs

data[LPM_SIZE-1]_[LPM_WIDTH-1] Note (1)	|	result[LPM_WIDTH-1]

0XXX...	|	0

X0XX...	|	0

XX0X...	|	0

...	|	...

1111...	|	1

Resource Usage:

Simple lpm_and gates use approximately one logic cell per gate.

See also:

Megafunctions/LPM


Note (1)

The LPM 2.1.0 standard uses 'x' characters to separate bit numbers in dual-range groups. These 'x' characters are automatically translated into underscores (_) in MAX+PLUS II.


lpm_bustri (Parameterized Tri-State Buffer Megafunction)
lpm_bustri (Buffer)

Parameterized Tri-State Buffer

Altera recommends using TRI primitives rather than lpm_bustri for easier implementation and to improve compilation time. However, the lpm_bustri function may be useful for controlling both unidirectional and bidirectional I/O bus controllers.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

If the result[] output feeds logic, and does not feed a BIDIR pin, the enabletr signal must be tied to VCC or an error message will result.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_bustri (data[LPM_WIDTH-1..0], enabletr, enabledt)

WITH (LPM_WIDTH)

RETURNS (tridata[LPM_WIDTH-1..0], result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_bustri

GENERIC (LPM_WIDTH: POSITIVE;

LPM_TYPE: STRING := "LPM_BUSTRI";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

enabledt: IN STD_LOGIC := '0';

enabletr: IN STD_LOGIC := '0';

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)

tridata: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	Yes	Data input to the tridata[] bus.	Input port LPM_WIDTH wide. Either data[] or result[] must be used. Both may be used.
enabletr	No	If high, enables tridata[] onto the result bus.	Required if result[] is present (default = 0).
enabledt	No	If high, enables data onto the tridata[] bus.	Required if data[] is present (default = 0).

OUTPUTS

Port Name	Required	Description	Comments
result[]	No	Output from the tridata[] bus.	Output port LPM_WIDTH wide. Either data[] or result[] must be used. Both can be used.

BIDIRECTIONAL PORTS

Port Name	Required	Description	Comments
tridata[]	Yes	Bidirectional bus signal.	Bidirectional port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[], result[], and tridata[] ports.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Some of the input and output ports of the lpm_bustri function are optional. The following three configurations are valid:

1.	Only the input ports data[LPM_WIDTH-1..0] and enabledt are present, and only the output ports tridata[LPM_WIDTH-1..0] are present. This configuration has the following function:

Input	|	Output

enabledt	|	tridata[LPM_WIDTH-1..0]

0	|	Z

1	|	DATA[LPM_WIDTH-1..0]

2.	Only the input ports tridata[LPM_WIDTH-1..0] and enabletr are present, and only the output ports result[LPM_WIDTH-1..0] are present. This configuration has the following function:

Input	|	Output

enabletr	|	result[LPM_WIDTH-1..0]

0	|	Z

1	|	tridata[LPM_WIDTH-1..0]

3.	All ports are present: input ports data[LPM_WIDTH-1..0], enabledt, and enabletr; output ports result[LPM_WIDTH-1..0]; and bidirectional ports tridata[LPM_WIDTH-1..0]. This configuration has the following function:

Inputs	|	Bidirectional	|	Output

enabledt	enabletr	|	tridata[LPM_WIDTH-1..0]	|	result[LPM_WIDTH-1..0]

0	0	|	Z (input)	|	Z

0	1	|	Z (input)	|	tridata[LPM_WIDTH-1..0]

1	0	|	data[LPM_WIDTH-1..0]	|	Z

1	1	|	data[LPM_WIDTH-1..0]	|	data[LPM_WIDTH-1..0]

Resource Usage:

Uses one I/O cell or one logic cell per bit.

See also:

Megafunctions/LPM


lpm_clshift (Parameterized Combinatorial Logic Shifter or Barrel Shifter Megafunction)
lpm_clshift (Shifter)

Parameterized Combinatorial Logic Shifter or Barrel Shifter Megafunction

Altera recommends using the lpm_clshift function instead of any other type of shifter, including old-style shifter macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_clshift (data[LPM_WIDTH-1..0], distance[LPM_WIDTHDIST-1..0], direction)

WITH (LPM_WIDTH, LPM_WIDTHDIST, LPM_SHIFTTYPE)

RETURNS (result[LPM_WIDTH-1..0], underflow, overflow);

VHDL Component Declaration:

COMPONENT lpm_clshift

GENERIC (LPM_WIDTH: POSITIVE;

LPM_WIDTHDIST: POSITIVE;

LPM_TYPE: STRING := "LPM_CLSHIFT";

LPM_SHIFTTYPE: STRING := "LOGICAL";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

distance: IN STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 DOWNTO 0);

direction: IN STD_LOGIC := '0';

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

underflow, overflow: OUT STD_LOGIC);

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	Yes	Data to be shifted.	Input port LPM_WIDTH wide.
distance[]	Yes	Number of positions to shift data[] in the direction specified by the direction port.	Input port LPM_WIDTHDIST wide.
direction	No	Direction of shift. Low = left (toward the MSB), high = right (toward the LSB).	Default value is 0 (low) = left (toward the MSB).

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Shifted data.	Output port LPM_WIDTH wide.
underflow	No	Logical or arithmetic underflow.	If "ROTATE" is specified as the LPM_SHIFTTYPE parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined (X) logic levels.
overflow	No	Logical or arithmetic overflow.	If "ROTATE" is specified as the LPM_SHIFTTYPE parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined (X) logic levels.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and result[] ports. Any positive integer > 1.
LPM_WIDTHDIST	Integer	Yes	Width of the distance[] input port. The LPM_WIDTHDIST parameter specifies the width of the distance port. The values on the distance port normally range from 0, which is “no shift,” to (LPM_WIDTH-1) which is the maximum meaningful shift. The typical value assigned to LPM_WIDTHDIST is “the smallest integer not less than log-base-2(LPM_WIDTH)” or [log-base-2(LPM_WIDTH)]. Any value on the distance port greater than LPM_WIDTH-1 results in an undefined (X) logic level.
LPM_SHIFTTYPE	String	No	Type of shifter: "LOGICAL", "ROTATE", "ARITHMETIC", or "UNUSED". If omitted, the default is "LOGICAL". The sign bit is extended for "ARITHMETIC". For a "LOGICAL" right shift, 0’s are always shifted into the MSB.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

The lpm_clshift megafunction acts like a barrel shifter. It contains entirely combinatorial logic.

Overflow occurs when the shifted result exceeds the precision of the result bus. For "LOGICAL" values, overflow occurs when all 1’s have been shifted out. For "ARITHMETIC" values, overflow occurs when a significant digit is shifted into or past the sign bit. Underflow occurs when the shifted result contains no significant digits.

Operation of the LOGICAL shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs	|	Outputs

direction	distance[1..0]	data[3..0]	|	overflow	|	result[3..0]	|	underflow

X	0	dcba	|	0	|	dcba	|	0

0	1	dcba	|	d	|	cba0	|	0

0	2	dcba	|	d # c	|	ba00	|	0

0	3	dcba	|	d # c # b	|	a000	|	0

1	1	dcba	|	0	|	0dcb	|	!d & !c & !b & a

1	2	dcba	|	0	|	00dc	|	!d & !c & (b # a)

1	3	dcba	|	0	|	000d	|	!d & (c # b # a)

Operation of the ARITHMETIC shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs	|	Outputs

direction	distance[1..0]	data[3..0]	|	overflow	|	result[3..0]	|	underflow

X	0	dcba	|	0	|	dcba	|	0

0	1	0cba	|	c	|	cba0	|	0

0	1	1cba	|	!c	|	cba0	|	0

0	2	0cba	|	c # b	|	ba00	|	0

0	2	1cba	|	c! # b!	|	ba00	|	0

0	3	0cba	|	c # b # a	|	a000	|	0

0	3	1cba	|	!c # !b # !a	|	a000	|	0

1	1	0cba	|	0	|	00cb	|	!c & !b & a

1	1	1cba	|	0	|	11cb	|	c & b & !a

1	2	0cba	|	0	|	000c	|	!c & (b # a)

1	2	1cba	|	0	|	111c	|	c & (!b # !a)

1	3	0cba	|	0	|	0000	|	(c # b # a)

1	3	1cba	|	0	|	1111	|	(!c # !b # !a)

Operation of the ROTATE shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs	|	Outputs

direction	distance[1..0]	data[3..0]	|	result[3..0]

X	0	dcba	|	dcba

0	1	dcba	|	cbad

0	2	dcba	|	badc

0	3	dcba	|	adcb

1	1	dcba	|	adcb

1	2	dcba	|	badc

1	3	dcba	|	cbad

Resource Usage:

The following table summarizes the resource usage for an lpm_clshift function used to implement a 16-bit bidirectional arithmetic shifter. Logic cell usage scales slightly faster than linearly in proportion to shifter width.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	142	51	Note (1)

Speed	|	16	141	45	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	76 (18)	28	Note (2)

Speed	|	16	85 (10)	22	Note (2)

Numbers of shared expanders used are shown in parentheses ( ).

See also:

Megafunctions/LPM


lpm_compare (Parameterized Comparator Megafunction)
lpm_compare (Comparator)

Parameterized Comparator Megafunction

Altera recommends that you use the lpm_compare function instead of any other type of comparator, including old-style comparator macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_compare (dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0], clock, aclr)

WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_PIPELINE, CHAIN_SIZE, ONE_INPUT_IS_CONSTANT)

RETURNS (alb, aeb, agb, ageb, aneb, aleb);

1.	In order to comply with the LPM 2.1.0 specification, the clock and aclr ports were added to the lpm_compare function in MAX+PLUS II version 6.2. Therefore, any pre-version 6.2 designs that instantiate lpm_compare using an AHDL in-line logic function reference with positional port association will compile differently. Altera recommends using named port association in in-line references for all LPM functions and other megafunctions.

2.	The clken signal is supported only for VHDL, but you must include the port declaration or a placeholder " ," when using this function in AHDL.

VHDL Component Declaration:

COMPONENT lpm_compare

GENERIC (LPM_WIDTH: POSITIVE;

LPM_REPRESENTATION: STRING := "UNSIGNED";

LPM_PIPELINE: INTEGER := 0;

LPM_TYPE: STRING := "LPM_COMPARE";

LPM_HINT: STRING := "UNUSED");

PORT (dataa, datab: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

aclr, clock: IN STD_LOGIC := '0';

clken: IN STD_LOGIC := '1';

agb, ageb, aeb, aneb, alb, aleb: OUT STD_LOGIC);

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
dataa[]	Yes	datab[] is compared to this value.	Input port LPM_WIDTH wide.
datab[]	Yes	Value to be compared to dataa[].	Input port LPM_WIDTH wide.
clock	No	Clock for pipelined usage.	The clock port provides pipelined operation for the lpm_compare function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.
clken	No	Clock enable for pipelined usage.	Available for VHDL only.
aclr	No	Asynchronous Clear for pipelined usage.	The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0’s, asynchronously to the clock signal.

OUTPUTS

Port Name	Required	Description	Comments
alb	No	High (1) if dataa[] < datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aeb	No	High (1) if dataa[] == datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.
agb	No	High (1) if dataa[] > datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.
ageb	No	High (1) if dataa[] >= datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aneb	No	High (1) if dataa[] != datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.
aleb	No	High (1) if dataa[] <= datab[].	One of alb, aeb, agb, ageb, aleb, or aneb must be present.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the dataa[] and datab[] ports.
LPM_REPRESENTATION	String	No	Type of comparison performed: "SIGNED", "UNSIGNED", or "UNUSED". If omitted, the default is "UNSIGNED".
LPM_PIPELINE	Integer	No	Specifies the number of Clock cycles of latency associated with the alb, aeb, agb, ageb, aleb, or aneb output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default value is 0 (non-pipelined).
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
CHAIN_SIZE	Integer	No	Altera-specific parameter. Maximum allowable length of carry chains or cascade chains in FLEX 6000, FLEX 8000, or FLEX 10K devices. If omitted, the default is 8. This value overrides the value of the Max. Auto Length option for the Carry Chain or Cascade Chain logic option(s) in the global project logic synthesis style, which is specified with the Global Project Logic Synthesis dialog box (Assign menu). For all other device families, varying this parameter provides different size/speed combinations; smaller values of CHAIN_SIZE generally result in faster and larger comparators, and vice versa. For more information, contact Altera Applications.
ONE_INPUT_IS_CONSTANT	String	No	Altera-specific parameter.Values are "YES", "NO", or "UNUSED". Provides greater optimization if an input is constant. If omitted, the default is "NO".

Function:

Inputs	|	Outputs

dataa[LPM_WIDTH-1..0]	datab[LPM_WIDTH-1..0]	|	alb	aeb	agb	ageb	aleb	aneb

a	b	|	a < b	a == b	a > b	a >= b	a <= b	a != b

Resource Usage:

The following table summarizes the resource usage for an lpm_compare function used to implement a 16-bit unsigned comparator. Logic cell usage scales linearly in proportion to shifter width.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	25	45	Note (1)

Speed	|	16	17	23	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	16 (19)	50	Note (2)

Numbers of shared expanders used are shown in parentheses ( ).

See also:

Megafunctions/LPM


lpm_constant (Parameterized Constant Generator Megafunction)
lpm_constant (Constant Generator)

Parameterized Constant Generator Megafunction

Altera recommends using the CONSTANT primitive or AHDL Constant Statements rather than lpm_constant for easier implementation and to improve compilation time. However, lpm_constant may be useful if you need to convert a parameter into a constant.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_constant ( )

WITH (LPM_WIDTH, LPM_CVALUE)

RETURNS (result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_constant

GENERIC (LPM_WIDTH: POSITIVE;

LPM_CVALUE: NATURAL;

LPM_TYPE: STRING := "LPM_CONSTANT";

LPM_STRENGTH: STRING := "UNUSED";

LPM_HINT: STRING := "UNUSED");

PORT (result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Value specified by the argument to LPM_CVALUE.	Output port LPM_WIDTH bits wide. LPM_CVALUE is truncated or sign-extended to LPM_WIDTH bits.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the result[] port.
LPM_CVALUE	Integer	Yes	Constant value to be driven out on the result[] port. If LPM_CVALUE cannot be represented in LPM_WIDTH bits, the result[] port drives the value LPM_CVALUE mod 2 ^ LPM_WIDTH.The LPM_CVALUE parameter is limited to a maximum of 32 bits.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Inputs	|	Outputs

(none)	|	result[LPM_WIDTH-1..0]

|	LPM_CVALUE

result = LPM_CVALUE

Resource Usage:

Uses no resources (i.e., 0 logic cells). The constant outputs are absorbed by other logic.

See also:

Megafunctions/LPM


lpm_counter (Parameterized Counter Megafunction)
lpm_counter (Counter)

Parameterized Counter Megafunction

The lpm_counter megafunction is a binary counter that features an up, down, or up/down counter with optional synchronous or asynchronous Clear, set, and load ports.

Altera recommends using the lpm_counter function instead of any other type of binary counter, including old-style counter macrofunctions.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_counter (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, updown, cin, aclr, aset, aconst, aload, sclr, sset, sconst, sload)

WITH (LPM_WIDTH, LPM_DIRECTION, LPM_MODULUS, LPM_AVALUE, LPM_SVALUE, CARRY_CNT_EN, LABWIDE_SCLR)

RETURNS (q[LPM_WIDTH-1..0], cout, eq[15..0]);

The sconst and aconst ports are provided only for backward compatibility with MAX+PLUS II version 6.0 designs and LPM 2.0.1, but should be left unconnected in newer projects.

VHDL Component Declaration:

COMPONENT lpm_counter

GENERIC (LPM_WIDTH: POSITIVE;

LPM_MODULUS: NATURAL := '0';

LPM_DIRECTION: STRING := "UNUSED";

LPM_AVALUE: STRING := "UNUSED";

LPM_SVALUE: STRING := "UNUSED";

LPM_PVALUE: STRING := "UNUSED";

LPM_TYPE: STRING := "LPM_COUNTER";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');

clock: IN STD_LOGIC;

cin: IN STD_LOGIC := '0';

clk_en: IN STD_LOGIC := '1';

cnt_en: IN STD_LOGIC := '1';

updown: IN STD_LOGIC := '1';

sload: IN STD_LOGIC := '0';

sset: IN STD_LOGIC := '0';

sclr: IN STD_LOGIC := '0';

aload: IN STD_LOGIC := '0';

aset: IN STD_LOGIC := '0';

aclr: IN STD_LOGIC := '0';

cout: OUT STD_LOGIC := '0';

q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	No	Parallel data input to the counter.	Input port LPM_WIDTH wide. Uses aload or sload.
clock	Yes	Positive-edge-triggered Clock.
clk_en	No	Clock Enable input. Enables all synchronous activities.	Default = 1 (enabled).
cnt_en	No	Count Enable input. Disables the count when low (0) without affecting sload, sset, or sclr.	Default = 1 (enabled).
updown	No	Controls the direction of the count. High (1) = count up. Low (0) = count down.	Default = up (1). If the LPM_DIRECTION parameter is used, the updown port cannot be connected. If LPM_DIRECTION is not used, the updown port is optional.
cin	No	Carry-in to the low-order bit.	If omitted, the default is 0.
aclr	No	Asynchronous Clear input.	Default = 0 (disabled). If both aset and aclr are used and asserted, aclr overrides aset.
aset	No	Asynchronous set input.	Default = 0 (disabled). Sets q[] outputs to all 1’s, or to the value specified by LPM_AVALUE. If both aset and aclr are used and asserted, aclr overrides aset.
aload	No	Asynchronous load input. Asynchronously loads the counter with the value on the data input.	Default = 0 (disabled). If aload is used, data[] must be connected.
sclr	No	Synchronous Clear input. Clears the counter on the next active Clock edge.	Default = 0 (disabled). If both sset and sclr are used and asserted, sclr overrides sset.
sset	No	Synchronous set input. Sets the counter on the next active Clock edge.	Default = 0 (disabled). Sets q outputs to all 1’s, or to the LPM_SVALUE value . If both sset and sclr are used and asserted, sclr overrides sset.
sload	No	Synchronous load input. Loads the counter with data[] on the next active Clock edge.	Default = 0 (disabled). If sload is used, data[] must be connected.

OUTPUTS

Port Name	Required	Description	Comments
q[]	No	Data output from the counter.	Output port LPM_WIDTH wide. Either q[] or at least one of the eq[15..0] ports must be connected.
eq[15..0]	No	Counter decode output Active high when the counter reaches the specified count value.	(AHDL only) Either the q[] port or eq[] port must be connected. Up to c eq ports can be used (0 <= c <= 15). Only the 16 lowest count values are decoded. When the count value is c, the, the eqc output is set high (1). For example, when the count is 0, eq0 = 1, when the count is 1, eq1 = 1. Decoded output for count values of 16 or greater require external decoding. The eq[15..0] outputs are asynchronous to the q[] output.
cout	No	Carry-out (borrow-in) of the MSB.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	The number of bits in the count, or the width of the q[] and data[] ports, if they are used.
LPM_DIRECTION	String	No	Values are "UP", "DOWN", and "UNUSED". If the LPM_DIRECTION parameter is used, the updown port cannot be connected. When the updown port is not connected, the default for the LPM_DIRECTION parameter is "UP".
LPM_MODULUS	Integer	No	The maximum count, plus one. Number of unique states in the counter’s cycle. If the load value is larger than the LPM_MODULUS parameter, the behavior of the counter is not specified.
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high. If the value specified is larger than <modulus>, the behavior of the counter is an undefined (X) logic level, where <modulus> is LPM_MODULUS, if present, or 2 ^ LPM_WIDTH. The LPM_AVALUE parameter is limited to a maximum of 32 bits.
LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of clock when either sset or sconst is high. Must be used if sconst is used.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
CARRY_CNT_EN	String	No	Altera-specific parameter. Values are "SMART", "ON", "OFF", or "UNUSED". Enables the lpm_counter function to propagate the cnt_en signal through the carry chain. In some cases, the CARRY_CNT_EN parameter setting may have a slight impact on the speed, so you may wish to turn it off. The default value is "SMART", which provides the best trade-off between size and speed.
LABWIDE_SCLR	String	No	Altera-specific parameter. Values are "ON", "OFF", or "UNUSED". Default value is "ON". Allows you to disable the use of the LAB-wide sclr feature found in FLEX 6000 devices. Turning this option off increases the chances of fully using the partially filled LABs, and thus may allow higher logic density when SCLR does not apply to a complete LAB.
Altera’s implementation of the lpm_counter function does not include the LPM_PVALUE parameter.

Function:

Inputs	|	Outputs	|	Function

aclr	aload	clock	sset	cnt_en	|	|

aset	clk_en	sclr	sload	updown	|	q[LPM_WIDTH-1..0]	|

1	X	X	X	X	X	X	X	X	X	|	000...	|

0	1	X	X	X	X	X	X	X	X	|	111...	|

0	1	X	X	X	X	X	X	X	X	|	LPM_AVALUE	|	Asynchronous set to value

|	|	specified for LPM_AVALUE

0	0	1	X	X	X	X	X	X	X	|	data[]	|	Asynchronous load from

|	|	data[] input

0	0	0	0	X	X	X	X	X	X	|	q[]	|	Hold current count value

0	0	0	1	~	1	X	X	X	X	|	000...	|	Synchronous Clear

0	0	0	1	~	0	1	X	X	X	|	111...	|	Synchronous set

0	0	0	1	~	0	1	X	X	X	|	LPM_SVALUE	|	Synchronous set to value

|	|	specified for LPM_SVALUE

0	0	0	1	~	0	0	0	0	0	|	q[]	|	Hold current count value

0	0	0	1	~	0	0	1	X	X	|	data[]	|	Synchronous load from

|	|	data[] input

0	0	0	1	~	0	0	0	1	1	|	q[]+1	|	Count up

0	0	0	1	~	0	0	0	1	0	|	q[]-1	|	Count down

Typical Implementation:

The lpm_counter function offers four different modes that allow you to force the count value to a specific number. You can use each of the modes either synchronously (port names starting with an “s”) or asynchronously (port names starting with an “a”). You can also combine the modes.

Mode:	Description:

Setting (forcing to all 1’s)	Asserting the sset or aset signal forces the count value to all 1’s.

Clearing (setting to all 0’s)	Asserting the sclr or aclr pin forces the count value to all 0’s.

Loading (from data bus)	Asserting the aload or sload signal loads the count value from the data input.

Loading (to a predetermined value)	Asserting the sset or aset signal loads the count value to the number specified

by the LPM_SVALUE or LPM_AVALUE parameter, respectively.

Resource Usage:

The following table summarizes the resource usage for an lpm_counter function used to implement a 16-bit counter with an up/down control, a count enable input, a synchronous load input, and an asynchronous Clear input. Logic cell usage scales linearly in proportion to counter width.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	46	33 MHz	Note (1)

Speed	|	16	17	125 MHz	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	16	125 MHz	Note (2)

See also:

Megafunctions/LPM


lpm_decode (Parameterized Decoder Megafunction)
lpm_decode (Decoder)

Parameterized Decoder Megafunction

Altera recommends using lpm_decode for data input widths less than or equal to 8, and using old-style decoder macrofunctions for data input widths greater than 8. In addition, if your project uses only a few sparse outputs of the decoder, Altera recommends using lpm_compare with one input set to a fixed value, instead of lpm_decode.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_decode (data[LPM_WIDTH-1..0], enable, clock, aclr)

WITH (LPM_WIDTH, LPM_DECODES, LPM_PIPELINE)

RETURNS (eq[LPM_DECODES-1..0]);

VHDL Component Declaration:

COMPONENT lpm_decode

GENERIC (LPM_WIDTH: POSITIVE;

LPM_TYPE: STRING := "LPM_DECODE";

LPM_PIPELINE: INTEGER := 0;

LPM_DECODES: POSITIVE;

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

aclr, clock: IN STD_LOGIC := '0';

clken, enable: IN STD_LOGIC := '1';

eq: OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	Yes	Data input. Treated as an unsigned binary encoded number.	Input port LPM_WIDTH wide.
enable	No	Enable. All outputs low when not active.	If absent, the default value is active (high).
clock	No	Clock for pipelined usage.	The clock port provides pipelined operation for the lpm_decode function. For LPM_PIPELINE parameter values other than 0 (default value), the clock port must be connected.
clken	No	Clock enable for pipelined usage.	Available for VHDL only.
aclr	No	Asynchronous Clear for pipelined usage.	The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0’s asynchronously to the clock signal.

OUTPUTS

Port Name	Required	Description	Comments
eq[]	Yes	Decoded output.	Output port LPM_DECODES wide. If data[] >= LPM_DECODES, all eq[] are 0.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] port, or the input value to be decoded.
LPM_DECODES	Integer	Yes	Number of explicit decoder outputs. LPM_DECODES <= 2 ^ LPM_WIDTH.
LPM_PIPELINE	Integer	No	Specifies the number of Clock cycles of latency associated with the eq[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Inputs	|	Outputs

enable	data[LPM_WIDTH-1..0]	|	eq[LPM_DECODES-1..0]

0	X	|	0000...00

1	LPM_DECODES-1	|	1000...00

1	LPM_DECODES-2	|	0100...00

...	...	|	...

1	1	|	0000...10

1	0	|	0000...01

The enable input port is optional. When enable is omitted, the decoder is permanently enabled.

Resource Usage:

Uses one logic cell per output for up to 16 outputs, and 2 logic cells per output for more than 16 outputs.

See also:

Megafunctions/LPM


lpm_ff (Parameterized D- or T-Type Flipflop Megafunction)
lpm_ff (D- or T-type Flipflop)

Parameterized Flipflop Megafunction

The lpm_ff function is useful if features are needed that are not available in the DFF, DFFE, TFF, and TFFE primitives, such as synchronous or asynchronous set, Clear, and load inputs.

Altera recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_ff (data[LPM_WIDTH-1..0], clock, enable, sclr, sset, sload, aclr, aset, aload)

WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE, LPM_FFTYPE)

RETURNS (q[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_ff

GENERIC (LPM_WIDTH: POSITIVE;

LPM_AVALUE: STRING := "UNUSED";

LPM_PVALUE: STRING := "UNUSED";

LPM_FFTYPE: STRING := "DFF";

LPM_TYPE: STRING := "LPM_FF";

LPM_SVALUE: STRING := "UNUSED";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

clock: IN STD_LOGIC;

enable: IN STD_LOGIC := '1';

sload: IN STD_LOGIC := '0';

sclr: IN STD_LOGIC := '0';

sset: IN STD_LOGIC := '0';

aload: IN STD_LOGIC := '0';

aclr: IN STD_LOGIC := '0';

aset: IN STD_LOGIC := '0';

q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	No	T-type flipflop: Toggle enable D-type flipflop: Data input	Input port LPM_WIDTH wide. If the data[] input is not used, at least one of the aset, aclr, sset, or sclr ports must be used. Unused data inputs default to GND.
clock	Yes	Positive-edge-triggered Clock.
enable	No	Clock Enable input.	Default = 1.
sclr	No	Synchronous Clear input.	If both sset and sclr are used and both are asserted, sclr is dominant.
sset	No	Synchronous set input.	Sets q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1’s. If both sset and sclr are used and both are asserted, sclr is dominant.
sload	No	Synchronous load input. Loads the flipflop with the value on the data input on the next active Clock edge.	Default = 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high (1) or unconnected. The sload port is ignored when the LPM_FFTYPE parameter is set to "DFF".
aclr	No	Asynchronous Clear input.	If both aset and aclr are used and both are asserted, aclr is dominant.
aset	No	Asynchronous set input.	Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1’s.
aload	No	Asynchronous load input. Asynchronously loads the flipflop with the value on the data input.	Default = 0. If aload is used, data must be used.

OUTPUTS

Port Name	Required	Description	Comments
q[]	Yes	Data output from D or T flipflops.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q[] ports.
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high. If omitted, defaults to all 1’s. The LPM_AVALUE parameter is limited to a maximum of 32 bits.
LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1’s.
LPM_FFTYPE	String	No	Values are "DFF", "TFF", and "UNUSED". Type of flipflop. If omitted, the default is "DFF". When the LPM_FFTYPE parameter is set to "DFF", the sload port is ignored.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
LPM_PVALUE	String	No	Value loaded at power on.

Function:

The following table is an example of the T-Type flipflop behavior in lpm_ff:

Inputs	|	Outputs

aclr	enable	sclr	sload	|

aset	clock	sset	|	Q[LPM_WIDTH-1..0]

1	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	|	111... or LPM_AVALUE

0	0	0	X	X	X	X	|	q[LPM_WIDTH-1..0]

0	0	1	~	1	X	X	|	000...

0	0	1	~	0	1	X	|	111... or LPM_SVALUE

0	0	1	~	0	0	1	|	data[LPM_WIDTH-1..0]

0	0	1	~	0	0	0	|	q[LPM_WIDTH-1..0] xor data[LPM_WIDTH-1..0]

Resource Usage:

Uses one logic cell per bit.

See also:

Megafunctions/LPM


lpm_shiftreg (Parameterized Shift Register Megafunction)
lpm_shiftreg (Universal Shift Register)

Parameterized Shift Register Megafunction

Altera recommends that you use the lpm_shiftreg function to replace all other types of shift register functions, including old-style shift register macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_shiftreg (data[LPM_WIDTH-1..0], clock, enable, shiftin, load, sclr, sset, aclr, aset)

WITH (LPM_WIDTH, LPM_DIRECTION, LPM_AVALUE, LPM_SVALUE)

RETURNS (q[LPM_WIDTH-1..0], shiftout);

VHDL Component Declaration:

COMPONENT lpm_shiftreg

GENERIC (LPM_WIDTH: POSITIVE;

LPM_AVALUE: STRING := "UNUSED";

LPM_PVALUE: STRING := "UNUSED";

LPM_SVALUE: STRING := "UNUSED");

LPM_DIRECTION: STRING := "UNUSED";

LPM_TYPE: STRING := "LPM_SHIFTREG";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

clock: IN STD_LOGIC;

enable: IN STD_LOGIC := '1';

shiftin: IN STD_LOGIC := '1';

load: IN STD_LOGIC := '0';

sclr: IN STD_LOGIC := '0';

sset: IN STD_LOGIC := '0';

aclr: IN STD_LOGIC := '0';

aset: IN STD_LOGIC := '0';

q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

shiftout: OUT STD_LOGIC);

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	No	Data input to the shift register.	Input port LPM_WIDTH wide. At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used.
clock	Yes	Positive-edge-triggered Clock.	Default = 1.
enable	No	Clock Enable input.	The shift options also use the enable input for the Clock Enable. For serial operation, enable must be high (1). For parallel load operation, load must be high (1) and enable must be high or unconnected.
shiftin	No	Serial shift data input.	At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used.
load	No	Synchronous Parallel Load. High (1): load operation; low (0): shift operation.	Default is low (0) shift operation. For parallel load operation, load must be high (1) and enable must be high or unconnected.
sclr	No	Synchronous Clear input.	If both sset and sclr are used and both are asserted, sclr is dominant.
sset	No	Synchronous set input.	Sets q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1’s. If both sset and sclr are used and both are asserted, sclr is dominant.
aclr	No	Asynchronous Clear input.	If both aset and aclr are used and both are asserted, aclr is dominant.
aset	No	Asynchronous set input.	Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1’s. If both aset and aclr are used and both are asserted, aclr is dominant.

OUTPUTS

Port Name	Required	Description	Comments
q[]	No	Data output from the shift register.	Output port LPM_WIDTH wide. Either q[] or shiftout or both must be used.
shiftout	No	Serial shift data output.	Either q[] or shiftout or both must be used. The shiftout port value is equal to q[LPM_WIDTH-1] when LPM_DIRECTION="LEFT". When LPM_DIRECTION="RIGHT", shiftout equals q[0].

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q ports.
LPM_DIRECTION	String	No	Values are "LEFT", "RIGHT", and "UNUSED". If omitted, the default is "LEFT". The MSB is the leftmost bit and the LSB is the rightmost bit. The MSB is q[LPM_WIDTH-1].
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high. If omitted, defaults to all 1’s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number.
LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1’s. Altera recommends that you specify this value as a decimal number.
LPM_PVALUE	String	No	Constant value that is loaded at power on.
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".

Function:

Inputs	|	Outputs

aclr	enable	sclr	load	|

aset	clock	sset	|	q[LPM_WIDTH-1..0]

1	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	|	111... or LPM_AVALUE

0	0	0	X	X	X	X	|	q[LPM_WIDTH-1..0]

0	0	1	~	1	X	X	|	000...

0	0	1	~	0	1	X	|	111... or LPM_SVALUE

0	0	1	~	0	0	1	|	data[LPM_WIDTH-1..0]

0	0	1	~	0	0	0	|	q[LPM_WIDTH-2..0], shiftin (assuming LPM_DIRECTION = "LEFT")

Resource Usage:

Uses one logic cell per bit.

See also:

Megafunctions/LPM


lpm_dff (Parameterized D Flipflop & Shift Register Megafunction)
lpm_dff (D Flipflop & Shift Register)

Parameterized D-Type Flipflop and Shift Register Megafunction

Altera recommends that you use lpm_ff rather than lpm_dff for flipflop functions, and lpm_shiftreg for shift register functions. The lpm_dff megafunction is provided only for backward compatibility with MAX+PLUS II pre-version 7.0 designs.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_dff (data[LPM_WIDTH-1..0], clock, enable, shiftin, shiften, sclr, sset, sconst, aclr, aset, aconst)

WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)

RETURNS (q[LPM_WIDTH-1..0], shiftout);

The sconst and aconst ports are provided only for backward compatibility with MAX+PLUS II version 6.0 designs, but should be left unconnected in newer projects.

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	No	Data input to the flipflops.	Input port LPM_WIDTH wide. If the data[] input is not used, at least one of the aset, aclr, sset, sclr and/or the combination of shiftin and shiften must be used.
clock	Yes	Positive-edge-triggered Clock.
enable	No	Clock Enable input.	Default = 1.
shiftin	No	Serial shift data input.	The shift options also use the enable input for the Clock Enable. For serial operation, both shiften and enable must be high.
shiften	No	Shift enable input. High (1) = shift operation, low (0) = register operation.	Default = 0 (register operation).
sclr	No	Synchronous Clear input.	If both sset and sclr are used and both are asserted, sclr is dominant.
sset	No	Synchronous set input.	Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1’s. If both sset and sclr are used and both are asserted, sclr is dominant.
aclr	No	Asynchronous Clear input.	If both aset and aclr are used and both are asserted, aclr is dominant.
aset	No	Asynchronous set input.	Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1’s. If both aset and aclr are used and both are asserted, aclr is dominant.

OUTPUTS

Port Name	Required	Description	Comments
q[]	No	Data output from flipflops.	Output port LPM_WIDTH wide. Either q[] or shiftout or both must be used.
shiftout	No	Serial shift data output.	Output port. Either q[] or shiftout or both must be used.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q[] ports.
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high. If omitted, defaults to all 1’s. The LPM_AVALUE parameter is limited to a maximum of 32 bits.
LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1’s.

Function:

Inputs	|	Outputs

aclr	enable	sclr	shiften	|

aset	clock	sset	|	q[LPM_WIDTH-1..0]

1	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	|	111... or LPM_AVALUE

0	0	0	X	X	X	X	|	q[LPM_WIDTH-1..0]

0	0	1	~	1	X	X	|	000...

0	0	1	~	0	1	X	|	111... or LPM_SVALUE

0	0	1	~	0	0	1	|	q[LPM_WIDTH-2..0], shiftin

0	0	1	~	0	0	0	|	data[LPM_WIDTH-1..0]

Resource Usage:

Uses one logic cell per bit.

See also:

Megafunctions/LPM


lpm_inv (Parameterized NOT Gate Megafunction)
lpm_inv (NOT Gate)

Parameterized Inverter Megafunction

Altera recommends using a NOT primitive or operator rather than lpm_inv. The lpm_inv function is useful only when compiling files imported from other industry-standard design tools.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_inv (data[LPM_WIDTH-1..0])

WITH (LPM_WIDTH)

RETURNS (result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_inv

GENERIC (LPM_WIDTH: POSITIVE;

LPM_TYPE: STRING := "LPM_INV");

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUT

Port Name	Required	Description	Comments
data[]	Yes	Data input to the lpm_inv.	Input port LPM_WIDTH bits wide.

OUTPUT

Port Name	Required	Description	Comments
result[]	Yes	Inverted result.	Output port LPM_WIDTH bits wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and result[] ports.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Input	|	Output

data[]	|	result[]

0	|	1

1	|	0

Resource Usage:

Uses no resources (i.e., 0 logic cells).

See also:

Megafunctions/LPM


lpm_latch (Parameterized Latch Megafunction)
lpm_latch (Latch)

Parameterized Latch Megafunction

Altera recommends that you use the lpm_latch function only if the aset port is needed; otherwise, you should the LATCH primitive rather than lpm_latch for easier implementation and to improve compilation time.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_latch (data[LPM_WIDTH-1..0], gate, aclr, aset, aconst)

WITH (LPM_WIDTH, LPM_AVALUE)

RETURNS (q[LPM_WIDTH-1..0]);

The aconst port is provided only for backward compatibility with MAX+PLUS II version 6.0 designs, but should be left unconnected in newer projects.

VHDL Component Declaration:

COMPONENT lpm_latch

GENERIC (LPM_WIDTH: POSITIVE;

LPM_PVALUE: STRING := "UNUSED";

LPM_TYPE: STRING := "LPM_LATCH";

LPM_AVALUE: STRING := "UNUSED";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);

gate: IN STD_LOGIC;

aclr: IN STD_LOGIC := '0';

aset: IN STD_LOGIC := '0';

q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	No	Data input to the latch.	Input port LPM_WIDTH wide. If the data[] input is not used, then either aset or aclr inputs must be used.
gate	Yes	Latch enable input. High = flow-through, low = latch.
aclr	No	Asynchronous Clear input.	Default = 0. Sets the latch to all 0’s. If both aset and aclr are used and both are asserted, aclr is dominant. aset and aclr affect the q[] outputs before the polarity is applied to the ports.
aset	No	Asynchronous set input.	Default = 0. Sets q outputs to the value specified by LPM_AVALUE, if that value is present, or sets the count to all 1’s. If both aset and aclr are used and both are asserted, aclr is dominant. aset and aclr affect the q[] outputs before polarity is applied to the ports.

OUTPUTS

Port Name	Required	Description	Comments
q[]	Yes	Data output from the latch.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q[] ports.
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high. If omitted, defaults to all 1’s. The LPM_AVALUE parameter is limited to a maximum of 32 bits.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Inputs	|	Outputs

aclr	aset	gate	|	q[LPM_WIDTH-1..0]

1	X	X	|	000...

0	1	X	|	111... or LPM_AVALUE

0	0	1	|	data[LPM_WIDTH-1..0]

0	0	0	|	q[LPM_WIDTH-1..0]

Resource Usage:

Uses a single logic cell per bit.

See also:

Megafunctions/LPM


lpm_mult (Parameterized Multiplier Megafunction)
lpm_mult (Multiplier)

Parameterized Multiplier Megafunction

Altera recommends that you use lpm_mult to replace all other types of multiplier functions, including old-style multiplier macrofunctions.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_mult (dataa[(LPM_WIDTHA-1)..0], datab[(LPM_WIDTHB-1)..0], sum[(LPM_WIDTHS-1)..0], aclr, clock)

WITH (LPM_WIDTHA, LPM_WIDTHB, LPM_WIDTHP, LPM_WIDTHS, LPM_REPRESENTATION, LPM_PIPELINE, LATENCY, INPUT_A_IS_CONSTANT, INPUT_B_IS_CONSTANT, USE_EAB, MAXIMIZE_SPEED)

RETURNS (result[LPM_WIDTHP-1..0]);

The LATENCY parameter is provided only for backward compatibility with MAX+PLUS II pre-version 7.0 AHDL designs.

VHDL Component Declaration:

COMPONENT lpm_mult

GENERIC (LPM_WIDTHA: POSITIVE;

LPM_WIDTHB: POSITIVE;

LPM_WIDTHS: NATURAL := 0;

LPM_WIDTHP: POSITIVE;

LPM_REPRESENTATION: STRING := "UNSIGNED";

LPM_PIPELINE: INTEGER := 0;

LPM_TYPE: STRING := "LPM_MULT";

LPM_HINT: STRING := "UNUSED");

PORT (dataa: IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);

datab: IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);

aclr, clock: IN STD_LOGIC := '0';

clken: IN STD_LOGIC := '1';

sum: IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0');

result: OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
dataa[]	Yes	Multiplicand.	Input port LPM_WIDTHA wide.
datab[]	Yes	Multiplier.	Input port LPM_WIDTHB wide.
sum[]	No	Partial sum.	Input port LPM_WIDTHS wide.
clock	No	Clock for pipelined usage.	The clock port provides pipelined operation for the lpm_mult function. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected.
clken	No	Clock enable for pipelined usage.	Available for VHDL only.
aclr	No	Asynchronous Clear for pipelined usage.	The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0’s, asynchronously to the clock signal.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.	Output port LPM_WIDTHP wide. If LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) or (LPM_WIDTHA + LPM_WIDTHS), only the LPM_WIDTHP MSBs are present.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTHA	Integer	Yes	Width of the dataa[] port.
LPM_WIDTHB	Integer	Yes	Width of the datab[] port.
LPM_WIDTHP	Integer	Yes	Width of the result[] port.
LPM_WIDTHS	Integer	Yes	Width of the sum[] port. Required even if the sum port is not used.
LPM_REPRESENTATION	String	No	Type of multiplication performed: "SIGNED", "UNSIGNED", or "UNUSED". If omitted, the default is "UNSIGNED".
LPM_PIPELINE	Integer	No	Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT	String	No	Allows you to assign Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.
INPUT_A_IS_CONSTANT	String	No	Altera-specific parameter. Values are "YES", "NO", and "UNUSED". If dataa[] is connected to a constant value, setting INPUT_A_IS_CONSTANT to "YES" optimizes the multiplier for resource usage and speed. If omitted, the default is "NO".
INPUT_B_IS_CONSTANT	String	No	Altera-specific parameter. Values are "YES", "NO", and "UNUSED". If datab[] is connected to a constant value, setting INPUT_B_IS_CONSTANT to "YES" optimizes the multiplier for resource usage and speed. The default is "NO".
USE_EAB	String	No	Altera-specific parameter. Values are "ON", "OFF", and "UNUSED". Setting the USE_EAB parameter to "ON" allows MAX+PLUS II to use EABs to implement 4 x 4 or (8 x const value) building blocks in FLEX 10K devices. Altera recommends that you set USE_EAB to "ON" only when LCELLS are in short supply. If you wish to use this parameter when you instantiate the function in a GDF, you must specify it by entering the parameter name and value manually with the Edit Ports/Parameters dialog box (Symbol menu). You can also use this parameter name in a TDF or a Verilog Design File. You must use the LPM_HINT parameter to specify the USE_EAB parameter in VHDL Design Files.
LATENCY	Integer	No	Altera-specific parameter. Same as LPM_PIPELINE. (This parameter is provided only for backward compatibility with MAX+PLUS II pre-version 7.0 designs. For all new designs, you should use the LPM_PIPELINE parameter instead.)
MAXIMIZE_SPEED	Integer	No	Altera-specific parameter. You can specify a value between 0 and 10. If used, MAX+PLUS II attempts to optimize a specific instance of the lpm_mult function for speed rather than area, and overrides the setting of the Optimize option in the Global Project Logic Synthesis dialog box (Assign menu). If MAXIMIZE_SPEED is unused, the value of the Optimize option is used instead. If the setting for MAXIMIZE_SPEED is 6 or higher, the Compiler will optimize lpm_mult megafunctions for higher speed; if the setting is 5 or less, the Compiler will optimize for smaller area.

Specifying a value for MAXIMIZE_SPEED has an effect only if LPM_REPRESENTATION is set to "SIGNED."

Function:

Inputs	|	Outputs

dataa[LPM_WIDTHA-1..0]	datab[LPM_WIDTHB-1..0]	sum[LPM_WIDTHS-1..0]	|	product[LPM_WIDTHP-1..0]

a	b	s	|	LPM_WIDTHP most significant bits

|	of a * b + s

Resource Usage:

The following table summarizes the resource usage for an lpm_mult function used to implement 4-bit and 8-bit multipliers with LPM_PIPELINE = 0 and without the optional sum input. Logic cell usage scales linearly in proportion to the square of the input width.

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	8	121	80 	Note (1)

Speed	|	8	163	52 	Note (1)

Routability	|	4	29	34 	Note (1)

Speed	|	4	41	27 	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	4	26 (11)	23 	Note (2)

Speed	|	4	27 (4)	19 	Note (2)

Numbers of shared expanders used are shown in parentheses ( ).

In the FLEX 10K device family, the 4-bit by 4-bit multiplier example shown above can be implemented in a single EAB.

See also:

Megafunctions/LPM


lpm_mux, mux & busmux (Parameterized Multiplexer Megafunctions)
lpm_mux, mux & busmux (Multiplexers)

Parameterized Multiplexer Megafunctions

Altera recommends that you use the lpm_mux function to replace all other multiplexer functions, including old-style multiplexer macrofunctions. Example

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

The mux and busmux megafunctions are derived from lpm_mux, and are intended to simplify the use of lpm_mux in GDFs:.

The busmux function is equivalent to an lpm_mux function with LPM_SIZE set to 2. Example

The mux function is equivalent to an lpm_mux function with LPM_WIDTH set to 1. Example

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_mux (data[LPM_SIZE-1..0][LPM_WIDTH-1..0], sel[LPM_WIDTHS-1..0], clock, aclr)

WITH (LPM_WIDTH, LPM_SIZE, LPM_WIDTHS, LPM_PIPELINE)

RETURNS (result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_mux

GENERIC (LPM_WIDTH: POSITIVE;

LPM_WIDTHS: POSITIVE;

LPM_PIPELINE: INTEGER := 0;

LPM_SIZE: POSITIVE;

LPM_TYPE: STRING := "LPM_MUX";

LPM_HINT: STRING := "UNUSED");

PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);

aclr, clock: IN STD_LOGIC := '0';

clken: IN STD_LOGIC := '1';

sel: IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

VHDL Component Declaration: busmux

VHDL Component Declaration: mux

Ports:

INPUTS

Port Name	Required	Description	Comments
data[][]	Yes	Data input.	Input port, consisting of LPM_SIZE buses, each LPM_WIDTH wide.
sel[]	Yes	Selects one of the input buses.	Input port LPM_WIDTHS wide.
clock	No	Clock for pipelined usage.	The clock port provides pipelined operation of the lpm_mux function. If an LPM_PIPELINE value other than 0 (default value) is specified, the clock port must be connected.
clken	No	Clock enable for pipelined usage.	Available for VHDL only.
aclr	No	Asynchronous Clear for pipelined usage.	The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0’s, asynchronously to the clock. However, the aclr port is used only if the LPM_PIPELINE parameter is specified (with a value other than 0) and the clock port is used.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Selected input port.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[][] and result[] ports.
LPM_SIZE	Integer	Yes	Number of input buses to the multiplexer. LPM_SIZE <= 2 ^ LPM_WIDTHS.
LPM_WIDTHS	Integer	Yes	Width of the sel[] input port.
LPM_PIPELINE	Integer	No	Specifies the number of Clock cycles of latency associated with the result[] output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined).
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Each lpm_mux function defines LPM_WIDTH multiplexers. Each multiplexer has the following function:

Inputs	|	Output

sel[LPM_WIDTHS-1..0]	|	result[LPM_WIDTH-1]

0	|	data[0] [LPM_WIDTH-1..0]

1	|	data[1] [LPM_WIDTH-1..0]

2	|	data[2] [LPM_WIDTH-1..0]

...	|	...

LPM_SIZE-2	|	data[LPM_SIZE-2] [LPM_WIDTH-1..0]

LPM_SIZE-1	|	data[LPM_SIZE-1] [LPM_WIDTH-1..0]

This table assumes that LPM_SIZE is a power of two, although it is not required.

Resource Usage:

The following table summarizes the resource usage for an lpm_mux function used to implement a 16-to-1 multiplexer. Logic cell usage scales linearly in proportion to log(LPM_SIZE).

Design Goals	|	Design Results

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Notes

FLEX 6000, FLEX 8000, and FLEX 10K	Routability	|	16	13	18 ns	Note (1)

Speed	|	16	10	15 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Speed	|	16	4 (0)	10 ns	Note (2)

Numbers of shared expanders used are shown in parentheses ( ).

See also:

Megafunctions/LPM


Example: lpm_mux with multiple buses

The following example shows an lpm_mux design that uses multiple buses.


Example: busmux

The following example shows a simple way to multiplex 2 buses using busmux.


Example: mux

The following example shows how to use mux to select one node from a bus.


Example: busmux_1
VHDL Component Declaration: busmux

COMPONENT busmux

GENERIC (WIDTH: POSITIVE);

PORT (data, datab: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);

sel: IN STD_LOGIC;

result: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));

END COMPONENT;


Example: mux_1
VHDL Component Declaration: mux

COMPONENT mux

GENERIC (WIDTH: POSITIVE;

WIDTHS: POSITIVE);

PORT (data: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);

sel: IN STD_LOGIC_VECTOR(WIDTHS-1 DOWNTO 0);

result: OUT STD_LOGIC);

END COMPONENT;


lpm_or (Parameterized OR Gate Megafunction)
lpm_or (OR Gate)

Parameterized OR Gate

Altera recommends using an OR primitive or operator rather than lpm_or for easier implementation and to improve compilation time. However, lpm_or may be useful if you need parameterized inputs.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_or (data[LPM_SIZE-1..0][LPM_WIDTH-1..0]

WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[LPM_WIDTH-1..0];

VHDL Component Declaration:

COMPONENT lpm_or

GENERIC (LPM_WIDTH: POSITIVE;

LPM_SIZE: POSITIVE;

LPM_HINT: STRING := "UNUSED");

LPM_TYPE: STRING := "LPM_OR";

PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[][]	Yes	Data input to the OR gates.	Input port LPM_SIZE x LPM_WIDTH wide.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Result of OR operators.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and result[] ports. Number of OR gates.
LPM_SIZE	Integer	Yes	Number of inputs to each OR gate. Number of input buses.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Each lpm_or function defines LPM_WIDTH OR gates. Each OR gate has the following function:

Inputs	|	Output

DATA[LPM_SIZE-1..0]_[LPM_WIDTH-1] Note (1)	|	RESULT[LPM_WIDTH-1]

1XXX...	|	1

X1XX...	|	1

XX1X...	|	1

...	|	...

0000...	|	0

Resource Usage:

Uses one logic cell per output.

See also:

Megafunctions/LPM


lpm_tff (Parameterized T Flipflop Megafunction)
lpm_tff (T Flipflop)

Parameterized T-Type Flipflop Megafunction

Altera recommends that you use lpm_ff rather than lpm_tff. The lpm_tff megafunction is provided only for backward compatibility with pre-MAX+PLUS II version 7.0 projects.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_tff (data[LPM_WIDTH-1..0], clock, enable, sclr, sset, sconst, sload, aclr, aset, aconst, aload)

WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)

RETURNS (q[LPM_WIDTH-1..0]);

The sconst and aconst ports are provided only for backward compatibility with MAX+PLUS II version 6.0 designs, but should be left unconnected in newer projects.

Ports:

INPUTS

Port Name	Required	Description	Comments
data[]	Yes	Data inputs/bit enables for the T flipflops. Data input during aload or sload.	Input port LPM_WIDTH wide.
clock	Yes	Positive-edge-triggered Clock.
enable	No	Clock Enable input. Enables all synchronous activities.	Default is enabled (1).
sclr	No	Synchronous Clear input. Clears the T flipflop on the next active Clock edge.	Default = 0. If both sset and sclr are used and both are asserted, sclr is dominant.
sset	No	Synchronous set input. Sets the T flipflop on the next active Clock edge.	Default = 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q to all 1’s. If both sset and sclr are used and both are asserted, sclr is dominant.
sload	No	Synchronous load input. Loads the T-type flipflops with the value on the data input on the next active Clock edge.	Default = 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high or unconnected.
aclr	No	Asynchronous clear input.	Default = 0. If both aset and aclr are used and both are asserted, aclr is dominant.
aset	No	Asynchronous set input.	Default = 0. Sets q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1’s. If both sset and sclr are used and both are asserted, sclr is dominant.
aload	No	Asynchronous load input. Asynchronously loads the T flipflops with the value on the data input.	Default = 0. If aload is used, data must be used.

OUTPUTS

Port Name	Required	Description	Comments
q[]	Yes	Data output from T flipflops.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[] and q[] ports.
LPM_AVALUE	Integer	No	Constant value that is loaded when aset is high (1). If omitted, defaults to all 1’s. The LPM_AVALUE parameter is limited to a maximum of 32 bits.
LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of clock when sset is high (1). If omitted, defaults to all 1’s.

Function:

Inputs	|	Outputs

aclr	aload	clock	sset	|

aset	enable	sclr	sload	|	q[LPM_WIDTH-1..0]

1	X	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	X	|	111... or LPM_AVALUE

0	0	1	X	X	X	X	X	|	data[LPM_WIDTH-1..0]

0	0	0	0	X	X	X	X	|	q[LPM_WIDTH-1..0]

0	0	0	1	~	1	X	X	|	000...

0	0	0	1	~	0	1	X	|	111... or LPM_SVALUE

0	0	0	1	~	0	0	1	|	data[LPM_WIDTH-1..0]

0	0	0	1	~	0	0	0	|	q[LPM_WIDTH-1..0]

|	XOR data[LPM_WIDTH-1..0]

Resource Usage:

Uses one logic cell.

See also:

Megafunctions/LPM


lpm_xor (Parameterized XOR Gate Megafunction)
lpm_xor (XOR Gate)

Parameterized XOR Gate

Altera recommends using the XOR primitive or operator rather than lpm_xor for easier implementation and to improve compilation time. However, lpm_xor may be useful if you need parameterized inputs.

Altera also recommends instantiating this function as described in Creating a Custom Megafunction Variation with the MegaWizard Plug-In Manager.

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION lpm_xor (data[LPM_SIZE-1..0][LPM_WIDTH-1..0])

WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[LPM_WIDTH-1..0]);

VHDL Component Declaration:

COMPONENT lpm_xor

GENERIC (LPM_WIDTH: POSITIVE;

LPM_SIZE: POSITIVE;

LPM_HINT: STRING := "UNUSED");

LPM_TYPE: STRING := "LPM_XOR";

PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));

END COMPONENT;

Ports:

INPUTS

Port Name	Required	Description	Comments
data[][]	Yes	Data input to the OR gate.	Input port LPM_SIZE x LPM_WIDTH wide.

OUTPUTS

Port Name	Required	Description	Comments
result[]	Yes	Each result[] bit is the XOR of LPM_SIZE bits.	Output port LPM_WIDTH wide.

Parameters:

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of the data[][] and result[] ports. Number of XOR gates.
LPM_SIZE	Integer	Yes	Number of inputs to each XOR gate. Number of input buses.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files. The default is "UNUSED".
LPM_TYPE	String	No	Identifies the LPM entity name in VHDL Design Files.

Function:

Each lpm_xor function defines LPM_WIDTH XOR gates. Each XOR gate has the following function:

Inputs	|	Output

data[LPM_SIZE-1]_[LPM_WIDTH-1] Note (1)	|	result[LPM_WIDTH-1]

Even	|	0

Odd	|	1

Resource Usage:

Uses one logic cell per output.

See also:

Megafunctions/LPM

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