6&|8Raima Data Manager Version 3.308Yo],-  9:C [[MS Sans Serif@@c8FPGA Compiler II / FPGA ExpressCopyright 1996-1999 Synopsys, Inc.d messages about FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express activities on the design source or implementation (chip) that is selected. To become familiar with the design flow and key features of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, run the online Quick Tour (from the Help menu) and refer to the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Getting Started. Note that Quick Tour is available only for PC installations of the program. For help on specific topics, choose Help Topics (from the Help menu) to access a table of contents, an alphabetic index, or a text-search feature. While using a specific feature of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, you can use context-sensitive help to display a brief explanation of that feature. Click the Context-Sensitive Help button or press Shift-F1, and then click an object in the GUI. f^8FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Main Window The FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express main window is a multiple document interface window. Its multiple child windows share a common tool bar, and menus, and other GUI tools. The main window contains a Project window and an Output (messages) window for each project you open. When you open or create a project, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express opens a project window to display the project contents. Each project window contains two windowsa Design Sources Window and a Chips Window. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically saves project contents. You do not need to explicitly save your projects. You can have multiple implementations open to enter constraints at any time, but be aware that each open implementation uses RAM. The Output window at the bottom of the main window displays errors, warnings, anh~File / New Project command New Project button Creates a new project with the name and path you specify. There are two ways to create a project. You can either select File > New Project from the file menu or click the New Project icon on the tool bar. To create a new project, specify a directory where the project will be stored. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates the directory and a project file. In this directory, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates subdirectories to store internal and intermediate files. These files should not be edited or modified. u^8t*File / Open Project command Open Project button Opens an existing project. You can open a project in these ways: Select File>Open Project from the File menu or click the OpenProject tool-bar icon and locate the project file in the Open dialog box. Select the project from the most recently used project list in the File menu (if the project was open recently). For Windows users: Locate the project file in the File Manager, Explorer, or My Computer, and drag it into the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Main window. ?File / Close Project command Closes the active project window. m8 File / Save command Save button Saves all open files and projects. A project file is saved automatically whenever it is changed. There are two ways to save a file or a project. You can either select File > Save from the File menu or click the Save tool-bar icon..  @File / Import Constraints command Imports and reads an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express constraint file and enters the performance constraints, attributes, and optimization options directly into the active, open implementation. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express merges the imported values with those in the open design implementation. For definitions of timing and module constraint terminology, see these topics: Timing Terminology Port and Pad Terminology Module and Hierarchy Optimization Terminology !a8 (File / Export Constraints command Exports and saves to a file the performance constraints, attributes, and optimization options specified from the active implementation. The exported constraint file is not used for reporting or editing. Its main purpose is to allow you to save time and reduce replication errors by applying the information in this file to a similar design. For definitions of timing and module constraint terminology, see these topics: Timing Terminology Port and Pad Terminology Module and Hierarchy Optimization Terminology  File / Project Report command Project Report button Opens a dialog box so you can name your report file. There are two ways to generate a Project Report. You can either select File>Project Report from the File menu or click the Project Report tool bar icon.For Project Report, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express generates a report that includes project, library, file, and chip information. You can also generate reports on individual libraries, files, or chips. ^8 File / [Open Recently Used Project] FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express maintains a list of the four most recently opened projects. Select from this list to save time when opening one of these projects. Open Recently Used Project FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express maintains a list of the four most recently opened projects. Select from this list to save time when opening one of these projects. ^8Open Recently Used Project FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express maintains a list of the four most recently opened projects. Select from this list to save time when opening one of these projects. Open Recently Used Project FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express maintains a list of the four most recently opened projects. Select from this list to save time when opening one of these projects. ^8Opened Projects FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express maintains a list of the four most recently opened projects. Select from this list to save time when opening one of these projects. vFile / Exit command Saves any open source files and implementations, closes and saves the current project, and exits. ,8Edit / Undo command Reverses certain commands or deletes the last entry you typed. You cannot undo some actions; in that case, the Undo command is unavailable. Edit / Cut command Cut button Removes the selected text from the active document and places it on the clipboard. There are two ways to perform this operation. Either select Edit > Cut from the edit menu or click the Cut tool-bar icon. 80Edit / Copy command Copy button Copies the selection to the clipboard. This is especially useful for copying the contents in constraint tables into a text or spreadsheet document. There are two ways to perform this operation. Either select Edit > Copy from the edit menu or click the Copy tool-bar icon. Edit / Paste command Paste button Inserts the contents of the clipboard at the insertion point, replacing any selection. In constraint tables, you can paste multiple cells, but only if the size of the range of cells on the clipboard matches that of the cells selected to be replaced. There are two ways to perform this operation. Either select Edit > Paste from the edit menu or click the Paste tool-bar icon. զ8 TEdit / Delete command Deletes the current selection (text, file or implementation). Edit / Fill Down command Copies the contents and formats of the cell or cells in the top row of a range into the rest of the rows in the range. -8dEdit / Next Error command Moves the cursor and display to the next error in the design source file. &lEdit / Previous Error command Moves the cursor and display to the previous error in the design source file. -8/Edit / Find Text command Searches for text in the open file from the current caret location downwards. When the text is found, it is highlighted. Press to search again. For more information, see: Case sensitive Find String Match whole word only @qCase Sensitive Matches the case of the find string (the text to be searched for) when searching for target text. 8IFind String Specifies the text string to be searched forcontrolled by the Case Sensitive Match and Whole Word Only check boxes. RxMatch Whole Word Only Searches only for whole words. The search does not find the text if it is part of a longer word. w8[cEdit / Find Again command Finds the next instance of the specified text in the design source file.  dSynthesis / Add Source Files command Add Sources button Adds the design source files for the project. There are three ways to add source files: Select Synthesis>Add Source Files from the Synthesis menu Click the Add Sources tool bar icon For Windows users, locate the source files in the File Manager, Explorer, or My Computer, and drag them into the Design Sources window. You can select and add individual source files or groups of files. Source files can be added to a project at any part of the design flow. Source files are automatically analyzed as they are added to the project. See Analysis Order when order is important. See also Source File Location. l^8!qSynthesis / New Library command Creates a design library called WORK. Design source files default to WORK. To support packages and other design libraries, you can create named libraries and then add design source files to the appropriate library. See also: New Library Name "~New Library Name Specifies the required library name. Note that all libraries used in an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project are subdirectories of the project. You cannot move them. b8#Synthesis / Update command Update button Updates the selected library, design file, implementation, or project and all dependencies. There are two ways to update a library, design file, implementation, or project. You can either select Synthesis > Update from the Synthesis menu or click the Update tool-bar icon while the library, design file, implementation, or project is selected. You can also force an update, Using the Force Update command. You might use this feature to update a component because a change you have made at a lower level or in a related file would not be apparent to FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. $^Synthesis / Force Update command Forces an update of the selected library, design file, implementation, or project, whether or not it has been modified. You might use this command to update a component because a change at a lower level or in a related file would not be apparent to FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. 8%TSynthesis / Create Implementation command Create Implementation button Creates a new implementation (chip) for the top-level (root) design selected in the top-level design dro-down box. This process elaborates the design and maps it to generic gates. There are two ways to create an implementation. You can either select Synthesis>Create Implementation from the Synthesis menu or click the Create Implementation tool bar icon when the top-level entity/module in the expanded hierarchy list (by double-clicking on the top-level design source file in the Design Sources window) is selected. &QSynthesis / Optimize Chip command Optimize Chip button Optimizes the elaborated implementation (chip) for speed or area, guided by the constraints and controls specified for it. There are two ways to optimize an implementation. You can either select Synthesis>Optimize Chip from the Synthesis menu or click the Optimize tool-bar icon. Optimization takes place as a background process, and progress is indicated in the status bar. For definitions of timing and module constraint terminology, see: Timing Terminology Port and Pad Terminology Module and Hierarchy Optimization Terminology 8'Q~he design flow. The attributes are associated with a specific design implementation (and device) and not to the source code. (Options command Displays property pages that let you configure various aspects of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. See also: General Options Project Options Optimization Options LPM Options 28)DView / Main Tool Bar command Toggles display of the main tool bar. *7View / Tip Bar command Toggles display of the Tip bar. 18+View / Output Window command Toggles display of the Output window, which contains errors, warnings, or messages about the selected component or activity. ,aView / Status Bar command Toggles display of the Status bar along the bottom of the main window. b8-Window / Cascade command Makes the Design Sources and the associated Chips windows the same size and cascades them within the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express main window. .Window / Tile command Tiles the Design Sources and the associated Chips windows within the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express main window. 8/TWindow / Arrange Icons command Arranges the icons of any minimized Project windows. 0 MWindow / Split command Lets you resize the Design Sources and Chips windows. [81xWindow / [Open Window] command Activates the selected window (brings it to the front, or opens it if it was iconified). 2Help / Help Topics command Opens the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express topic-based help system, which you can navigate using the table of contents, keyword index, or full-text search feature. f`83%Help / Quick Tour command Invokes the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Quick Tour, which familiarizes you with the design flow and key features of the tool. Note that Quick Tour is available only on PC installations. 4.Help / Synopsys Web Site command Starts your web browser at the Synopsys home page, which includes links to additional information about FPGA Compiler II / FPGA Express. c857Help / About FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express command Displays the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express version, copyright, and logo. 6@cSTOP button FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express analyzes, elaborates, and optimization on a design as background tasks. Clicking STOP terminates the current background task at the next point in the process. Note that this option is not active for some commands (for example, Create Implementation and Export Netlist). 487JTop-Level Design drop-down box This drop-down box sets the top-level design for the new design implementation. Click the box to display a list of entity architectures (VHDL), modules (Verilog), and designs (schematic) of the analyzed source files. Scroll through the list and choose the top-level design for the design implementation. You can also set the top-level design by selecting a design from the expanded source file list. 8SContext-Sensitive Help button For context-sensitive help, click the Context-Sensitive Help button (this button) or press Shift-F1, then click an object in the application. If there is a help topic for the item, it is displayed. a89\aStatus Bar The Status bar: Shows brief help while the mouse is over a tool bar button or menu item. Displays progress messages while FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express is analyzing sources, creating an implementation, and optimizing a design. Indicates current memory usage. The upper bar shows the percentage of RAM currently occupied, and the lower bar shows the percentage of the paging file that is occupied. Generally, if the lower bar is close to full, your system is out of virtual memory. Check your disk space and performance settings from the Control Panel. :hTip Bar Displays messages to indicate the actions that you are most likely to perform next, depending on the state of the current project. The light bulb flashes to attract attention when a new message is displayed. 8;qVLightbulb The lightbulb flashes to attract attention when a new message is displayed. <y=Refresh All Timing Refreshes the timing tables for the chip. F38=qUsing Help Shows generic help on using Windows Help, such as capabilities, keyboard accelerators, and bookmarks. >Select Top-Level Design for New Implementation Sets the top-level design for the new design implementation. Click this box to display a list of entity architectures (VHDL) and modules (Verilog) for the analyzed design source files. Scroll through the list and choose the top-level design for the design implementation. You can also set the top-level design by selecting a design icon from the expanded design source file tree in the Design Sources window. T8?Dialog Box Help FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express conforms to the new Windows 95 User Interface Design Guide. Help buttons in dialog boxes provide help on the items in the dialog box. Context-sensitive help provides help about the dialog box. @Context Menus Where applicable, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses context menus. A context menu is a pop-up menu specific to the desktop. It contains frequently used operations for a specific object. To see the context menu for a specific object, select the object with the right mouse button. You can use the menu items on the main menu bar to manipulate the object whether or not the object has a context menu. Z`8AProject Window This window shows the active FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project. The project window is partitioned into two smaller windows: Design sources - Shows source and netlist files in the project Chips - Shows implementations created from the design source files This window gives an overview of the contents and status of the project. Each source file and design implementation is represented by an icon that indicates its state. The Output window on the bottom of the main window shows errors, warnings, and messages reporting results and the status of operations on the selected design source or implementation. BProject Window When you open or create a project, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express opens a separate window to display its contents. Each project window contains two windowsa Design Sources Window and a Chips window. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically saves project contents so you do not have to explicitly save your projects. You can have multiple implementations open to enter constraints at any time, but be aware that each open implementation uses RAM. The project window gives an overview of the contents and status of the project. Each source file and design implementation is represented by an icon that indicates its state. The Output window on the bottom of the main window shows errors, warnings, and messages reporting results and the status of operations on the selected design source or implementation. P_8COutput Window The Output window automatically displays errors and warnings for each action you perform on a design source or chip. It also displays warnings and messages about selected chips. You can use the information in this window for debugging. If you double-click on the text part of an error, you start a text editor so you can change the HDL source code. If you double-click on the error code displayed in parentheses, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays an extended help page for that error if there is one. You can use the information in this window with the built-in HDL Editor for debugging. The Output window has a context menu which provides these commands Copy Save this page Save all pages D)Error Messages FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays several kinds of error messages: Interactive Messages Interactive messages are the result of user actions and usually appear in a popup dialog box. These are self-contained messages that report what has happened and what to do next. Analysis Messages Analysis messages are the result of HDL or netlist source analysis. Analysis results are indicated on the associated icon. You can view detailed error messages in the Output window. Create Implementation Messages Create Implementation messages are the result of creating an implementation for a design. To view these messages, see the Output window when you select the implementation. Optimization Messages Optimization messages are the result of optimizing a source implementation for a design. To view these messages, see the Output window when you select the implementation. See these topics for more information: Source file status icons Implem)c8EFzt the file icon, click the right mouse button, and select Edit File.  In the Output window, double-click the error text. FEViewing Errors and Warnings The FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Output window is a separate top-level window below the Design Sources and Chips windows. The Output window displays errors, warnings, and messages for a design source or implementation.  Messages are divided into three tabbed pages (Errors, Warnings, and Messages) for classification and interpretation; click the tab to see each set of messages. This is the format of the individual errors and warnings: One or two lines of the source file indicating where the error occurred (if the analyzer can determine the location of the error) One line indicating the nature of the message (error or warning) and its location (source line number) One or more lines of message description including an error code To edit the source file where an error occurred, use either of these methods to open the file in the built-in HDL Editor or an assigned external editor. In the Design Sources window, selecU=8GOutput window context menu / Copy command Copies the content of the Errors, Warnings, or Messages currently in the Output window. You can then paste this material into another document. HOutput window context menu / Save This Page command Opens the Save This Info Page dialog box. Specify a name and location for a text file of the errors, warnings, or messages currently in the Output window for the selected design source file or chip. 38I Output window context menu / Save All Pages command Opens the Save All Info Pages dialog box. Specify a name and location for a text file of all errors, warnings, and messages in the Output window for the selected design source file or chip. JProject Status Icons These icons indicate the status of the project: Components analyzed OKno errors or warning  Components analyzed with warnings  Components analyzed with errors  Busycomponents are being analyzed or updated _38K)Library Status Icons These icons indicate the status of each library in the project:  Source files analyzed OKno errors or warning  Source files analyzed with warnings  Source files analyzed with errors  Busysource files are being analyzed or updated +LRM   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+MRL3f333f3333f3ffffff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+NSO   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+OSN3f333f3333f3ffffff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+PTQ   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+QTP3f333f3333f3ffffff3f3f3f4444444444444444444444443f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+RUS   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+SUR3f333f3333f3ffffff3f3f3f4444444444444444444444444444444444444444444444444444443f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+TVU   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+UVT3f333f3333f3ffffff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+VXW   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+|8+WXV3f333f3333f3ffffff3f3f3f4444444444444444444444443f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f+XYY   C ("3DUfw"333f3333DUf3ffffffw3f3f3f""""333333f333333333f33ff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3f-48+YYX3f333f3333f3ffffff3f3f3f3f333f3333333f3333333f3333DDDDUUUUff33f3ff3f3f3f3ff3ffffffffffff3fffffff3fffffff3ffffffwwwwf̙333f33̙33f3ffff̙ff3f̙3f̙3f̙ʦ3f333f3333f3ffffff̙3̙f̙̙̙̙3f3fZ@fSource File Status Icons These icons indicate the status of each source file:  Has not been processedstatus is unknown.  Analyzed OKno errors or warnings.  Analyzed with warnings.  Analyzed with errors.  Missing the path has changed or the file been deleted. See also Source File Location  Out of datethe file has changed since it was last analyzed. Busythe file is currently being analyzed.  Nonsource file. As documentation, you can add any file type to your projecttext readme files, for example. They are not analyzed or otherwise processed, but you can open them by double-clicking the icon. _8[^Implementation Status Icons These icons indicate the status of each unoptimized and optimized implementation: Unoptimized implementation generated OKno errors or warnings Unoptimized implementation generated with warnings Unoptimized implementation generated with errors  Unoptimized implementation is out of date with source  BusyUnoptimized implementation is being optimized or updated  Optimized implementation OKno errors or warnings  Optimized implementation optimized with warnings  Optimized implementation optimized with errors  Optimized implementation is out of date with source  BusyOptimized implementation is being updated \Source File Location Source files can be located anywhere on your computer or network that you can access. When you add source files to a project, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express stores their locations in the project. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not copy source files to the project directory. This method ensures that updates to those source files are reflected in your projects. By default, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express remembers absolute paths to source files (for example, d:\designs\secret\hdl\display.vhd on a PC or Computer share directory counter.v on a UNIX system). This is convenient for projects with shared or common code. 58]Clocks Constraint Table To enter constraints for clocks, click the right mouse button on an elaborated implementation, select Edit Constraints and the the Clocks tab. See Clocks Constraint Entry. To view the results of optimization, click the right mouse button on an optimized implementation, select View Results and then the Clocks tab. See Clocks Constraint Table After Optimization. ^Clocks Constraint Entryk8_`Use the Clocks constraint table to specify the waveforms of periodic signals in the design. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you click the right mouse button on an elaborated implementation and select Edit Constraints. To view the results of optimization, see Clocks Constraint Table After Optimization. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically constructs the list of periodic signals when it creates an implementation. For each periodic signal, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the name (Name column) and period/rise/fall waveform (Clock column). Name This is the full name of the periodic signal in the design hierarchy (for example, top/module1/clk). Clock This is the waveform (period, rise time, fall time) of each periodic signal. Note that the falling edge can be first, and the clocks duty cycle does not have to be 50%. To specify a wa`_veform, click the Clock cell, click the expand arrow that appears in the cell, and then select Define. This displays the Define Clock dialog box where you can enter the period, rise time, and fall time of the signal. The waveform in this dialog box is for information only and does not reflect the values you enter. Alternatively, you can click the expand arrow in the cell and select a set of values from the list. This list contains all the previously entered values. You can also use the cut and paste commands. Default timing values: When a table cell is blank, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the default clock waveform defined in the first row. This default waveform is derived from the Clock frequency value in the Create Implementation dialog box. You can override this value when editing the implementation constraints. See Entering Timing Constraints for a description of the top-down procedure for specifying timing requirements. See also Edit8aBClocks Constraint Table After Optimization For optimized implementations, the Clocks constraint table contains these additional columns: Required Frequency This is the target frequency in megahertz for this clock. Estimated Frequency This is the estimated frequency in megahertz for this clock, based on a statistical timing model provided by the FPGA vendor. If the value is displayed in red, the target frequency has not been met. See Timing Analysis for a description of the top-down procedure for reviewing the results of optimization. See also Clocks Constraint Entry. bPaths Constraint Table To enter constraints for paths, click the right mouse button on an elaborated implementation, and select Edit Constraints, and then the Paths tab. See Paths Constraint Entry . To see the results of optimization, click the right mouse button on an optimized implementation, select View Results, and then the Paths tab. See Paths Constraint Table After Optimization. For the meaning of the icons in the Paths constraint table, see Paths Constraint Table Icons. 8vPaths Constraint Entrydes default timing values using the default waveforms of the periodic signals. To specify point-to-point constraints, create subpaths by clicking the right mouse button on a path for the subpaths menu . See Timing Subpaths for the steps in specifying point-to-point timing constraints. See Entering Timing Constraints for a description of the top-down procedure for specifying timing requirements. See also Editing Constraint Table Entries. 8efdriodic signal, or all level-sensitive sequential elements clocked by a specified periodic signal. To This is the ending group of the path. It can be the set of all primary outputs of the design, all edge-sensitive sequential elements clocked by a specified periodic signal, or all level-sensitive sequential elements clocked by a specified periodic signal. Required Delay This is the maximum delay of the path, computed from the waveforms of the periodic signals. This value is the difference between the active edge of the ending group of the path and the active edge of the starting group of the path. To enter a new value for a path group, click the Required Delay column to highlight the default value and type in the new value. Alternatively, you can click the expand arrow in the cell and select a value from the list of previously entered Delay values. You can also use cut and paste commands. Default Delay Values FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express computefePaths Constraint Entry Use the Paths constraint table to specify timing constraints for timing groups. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you click the right mouse button on the elaborated implementation and select Edit Constraints. For optimized implementations, the Paths constraint table expands to display additional timing information about the paths and subpaths. See Paths Constraint Table After Optimization. The Paths constraint table contains the list of timing groups automatically constructed in the Create Implementation step. For each path, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the starting group (From column), the ending group (To column), and the maximum delay of the path (Required Delay column). From This is the starting group of the path. It can be the set of all primary inputs of the design, all edge-sensitive sequential elements clocked by a specified peY=8ghd path. The columns in the third table are Instance Path, Cell Type, Delay, and Fanout.  See Timing Analysis for a description of the top-down procedure for reviewing the results of optimization. See also Paths Constraint Entry. hgPaths Constraint Table After Optimization For optimized implementations, the Paths constraint table expands to display additional timing information about the paths and subpaths. The default table shows all the timing groups for the chip. Each row represents a group of paths between timing groups.  When you select a row, the Paths constraint table displays a second table. The second table shows the worst delays to all endpoints in the selected group of timing paths. Each row shows the path from the start group to an end group, including estimated delay and slack. Slack can be used to filter the display. Right-click the Est. Delay/Slack column title and then select Filter delay (to set a slack value for filtering), or Display all (to remove filtering).  When you click on a row, the Paths constraint table displays a third table. The third table shows the complete path from the startpoint to the endpoint. It describes the delay between each pin (or port) and the next pin in the selecte38i/Paths Constraint Table Icons The icons in the Paths constraint table have these meanings:  All input ports  All output ports  Flip-flops clocked by rising edge  Flip-flops clocked by falling edge  Latches with active high enable  Latches with active low enable  Subpath start point or end point j7Ports Constraint Table To enter constraints for ports, click the right mouse button on an elaborated implementation, select Edit Constraints, and then the Ports tab. See Ports Constraint Entry. To see the results of optimization, click the right mouse button on an optimized implementation, select View Results, and then the Ports tab. See Ports Constraint Table After Optimization. 8cPorts Constraint EntrylEmnts apply to Lucent technology only. Pad Location To specify the location of pads for a port, enter it in this cell. Pad locations are vendor-specific. You cannot specify pad locations for a design using Xilinx technology that has the Do Not Insert I/O Pads option selected. See Entering Timing Constraints for a description of the top-down procedure for specifying timing requirements. See also Editing Constraint Table Entries. 8mEnlcent technology only. Direct In Connect Select whether the pad-mapping optimization uses the dedicated connection from this input port to a register cell. Direct connections generally provide faster connections with relation to setup and hold time. The options are: default (maintain the design defaults) 1 (use a direct connection to the register pad cell) 0 (do not use a direct connection to the register pad cell) Direct in connect constraints apply to Lucent technology only. Slew Rate Select a fast or slow slew rate for an output or bidirectional port. Direct Out Connect Specify whether the pad-mapping optimization uses the dedicated connection from a register pad cell to this output port. Direct connections generally provide faster connections with relation to setup and hold time. The options are: default (maintain the design defaults) 1 (use a direct connection from the register pad cell) 0 (do not use a direct connection from the register pad cell) Direct out connect constrainEomgn that has the Do Not Insert I/O Pads option selected. Pad Direction Use the pull-down list in this cell to specify this port as three-state (bidirectional). Resistance Resistance options for a port or pad are specific to the implementation's target device. Use the pull-down list for the port to select from available options. Resistance constraints apply to Actel, and Lucent, and Xilinx technologies only. Input Register Delay Use the pull-down list options in this cell to control whether optimization uses an input delay inside an input register. The use of an input delay reduces the hold time requirement for an input transition. Input register delay constraints apply to Xilinx and Lucent technologies only. Use I/O Register Specify that I/O register pads be used on a port where applicable. I/O register constraints apply to Altera and Xilinx technologies only. Voltage In Specify CMOS or TTL input voltage levels for an input or bidirectional port. Voltage in constraints apply to Lu8oEpnn. You can cut and paste into subsequent rows to apply the settings from one row to another. The first columns show the port name and the default port type (Direction) as specified in the HDL or netlist description. These are the constraints you can enter in the Ports constraint table: Input Delay  To define an input delay other than the default, click the Input Delay cell for a port and select Define. In the Define Delay dialog box, define the input delay. Output Delay  To define an output delay other than the default, click the Output Delay cell for a port and select Define. In the Define Delay box, define the output delay. Global Buffer  To specify insertion of a global buffer for a port or to select automatic global buffer insertion, click the Global Buffer cell for a port and make the appropriate selection. The options are automatic (default) and dont use. Global buffer constraints apply to Actel and Xilinx technologies only. You cannot define global buffers for a desipEoPorts Constraint Entry Enter port-specific constraints in the Ports constraint table. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you click the right mouse button on an elaborated implementation and select Edit Constraints. For optimized implementations, the Ports constraint table contains additional information about timing. See Ports Constraint Table After Optimization. The columns in the Ports constraint table let you define constraints that characterize top-level ports, such as buffer type, pad direction, pull-up/down, voltage level, resistance, slew rate, and I/O register use. Some of the constraints are technology-specific. Each row in the table shows the constraints for a port. The first row defines default values for all ports. If there is no entry for a port in a column, optimization uses the value defined in the default row. Once you have entered a value, that value becomes available to all the rows in that columʽ8qrPorts Constraint Entry Enter port-specific constraints in the Ports constraint table. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you click the right mouse button on an elaborated implementation and select Edit Constraints. For optimized implementations, the Ports constraint table contains additional information about timing. See Ports Constraint Table After Optimization. The columns in the Ports constraint table let you define constraints that characterize top-level ports, such as buffer type, pad direction, resistance, slew rate, and I/O register use. Each row in the table shows the constraints for a port. The first row defines default values for all ports. If there is no entry for a port in a column, optimization uses the value defined in the default row. Once you have entered a value, that value becomes available to all the rows in that column. You can cut and paste into subsequent rows to apply the settings from one rrqsow to another. The first columns show the port name and the default port type (Direction) as specified in the HDL or netlist description. These are the constraints you can enter in the Ports constraint table: Input Delay  To define an input delay other than the default, click the Input Delay cell for a port and select Define. In the Define Delay dialog box, define the input delay. Output Delay  To define an output delay other than the default, click the Output Delay cell for a port and select Define. In the Define Delay box, define the output delay. Global Buffer  To specify insertion of a global buffer for a port or to select automatic global buffer insertion, click the Global Buffer cell for a port and make the appropriate selection. The options are automatic (default) and dont use. You cannot define global buffers for a design that has the Do Not Insert I/O Pads option selected. Pad Direction Use the pull-down list in this cell to specify this port as three-state (bidireʽ8srctional). Resistance Resistance options for a port or pad are specific to the implementation's target device. Use the pull-down list for the port to select from available options. Input Register Delay Use the pull-down list options in this cell to control whether optimization uses an input delay inside an input register. The use of an input delay reduces the hold time requirement for an input transition. Use I/O Register Specify that I/O register pads be used on a port where applicable. Slew Rate Select a fast or slow slew rate for an output or bidirectional port. Pad Location To specify the location of pads for a port, enter it in this cell. Pad locations are vendor-specific. You cannot specify pad locations for a design that has the Do Not Insert I/O Pads option selected. See Entering Timing Constraints for a description of the top-down procedure for specifying timing requirements. See also Editing Constraint Table Entries. tPorts Constraint Table After Optimization For optimized implementations, the Ports constraint table contains these additional columns: Input Slack This column displays the input slack in nanoseconds for an input or inout port. Positive slack means that the requirement is met; negative slack means that the requirement is not met. Output Slack This column displays the output slack in nanoseconds for an output or inout port. Positive slack indicates that the requirement is met; negative slack means that the requirement is not met. ]8uModules Constraint Table To enter constraints for modules, click the right mouse button on an elaborated implementation, select Edit Constraints and then the Modules tab . See Modules Constraint Entry. To see the results of optimization, click the right mouse button on an optimized implementation, select View Results, and then the Modules tab. See Modules Constraint Table After Optimization. For the meaning of the icons in the Modules constraint table, see Modules Constraint Table Icons. -Modules Constraint Entryv8wx&he software effectively treats a design as a black-box. This feature applies only when the design hierarchy is preserved. If the hierarchy is not preserved, then the dont touch setting is ignored. By default, the dont touch attribute is set to FALSE. The available options are: True: Enables Dont Touch on that entity/module/instance. All the lower entities/modules/instances inherit this setting. False: Disables Dont Touch on that entity/module/instance. All the lower entities/modules/instances inherit this setting. True : Enables Dont Touch on all the instances of that entity/module. False : Disables Dont Touch on all the instances of that entity/module. Inherit: Takes on the setting of the entity/module in which that entity/module is instantiated. Inherit : All the instances of that entity/module take on the setting of the entity/module in which that entity/module is instantiated. Operator Sharing Use this setting to contrxywer, preserving hierarchy reduces compilation time if it is an issue. Primitives Use this setting to control the preservation or optimization of the primitives instantiated in the module. When set to Preserve, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express retains the boundaries of all the primitives instantiated in the module , except for buffers and inverters, and uses the implementation of the primitives provided by the architecture vendor. An Optimize setting eliminates the boundaries of all the primitives instantiated in the module and FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes the primitive logic with the logic of the module. The default is Preserve. Dont Touch FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express allows you to set a dont touch attribute on a design/entity/module and also on cells and instances. Use this setting to control whether or not a portion of your design is optimized. When unoptimized, tv8yzxFPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the defined value in each table cell for the module and for each submodule of that module without an explicitly defined value. The Modules constraint table has these columns: Hierarchy Use this setting to control the preservation or elimination of the modules boundary during optimization. Set to Preserve, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express retains the boundary of this module during optimization. The logic of this module is optimized independently of the rest of the designs logic, and the module remains a module in the optimized implementation. An Eliminate setting allows elimination of the boundary between the module and its container during optimization. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes the logic of this module with the logic of the rest of the modules container. In general, eliminating hierarchy yields the best quality of results. HowevzyModules Constraint Entry Use the Modules constraint table to control optimizing the design hierarchy. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you click the right mouse button on an elaborated implementation and select Edit Constraints. For optimized implementations, the Modules constraint table displays additional detail. See Modules Constraint Table After Optimization. The Modules constraint table contains a separate row for each user module in the design. Submodules are listed below parent modules and the names of the submodules are indented. When you open the Modules constraint table for the first time, the values in the default row are the recommended values for the architecture. Modules without a defined value in a cell inherit the value of a module further up the hierarchy. If the top module has no defined value, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the value in the default row. 8`8{ Project OptionsOptions dialog box In this dialog box, you can control project defaults: FSM synthesis: Default encoding (takes effect on file analysis) These buttons control the encoding for finite state machines (FSM) in VHDL designs. Choices include One Hot (default), Binary, and Zero One Hot. FSM synthesis: Interpretation of VHDL when others These buttons control implementation of the when others selection in the VHDL case statement describing the state transition logic. Choices include fastest & smallest (default) or safest. fastest & smallest provides the best implementation when illegal state transitions can be ignored. If recovery from illegal state transition is necessary, choose safest. To ensure the fastest & smallest FSM implementation, omit the when others statement from your FSM descriptions. See How to Specify Finite State Machines for more information. Default Export Timing specifications option to YES This check box sets the default for the Export Tim|Modules Constraint Table After Optimization For optimized implementations, the Modules constraint table displays these additional columns: Area This column displays the number of lookup tables for a module and its submodules. The value for a top-level module is the total number of lookup tables in the whole design. The column displays a question mark (?) when the module contains black boxes. For a detailed report, click the cell in this column and select Details from the drop-down list to bring up the Cell Counts window. Flip-flops This column contains the number of flip-flops for a module and its submodules. The value for a top-level module is the total number of flip-flops in the design. Latches This column contains the number of latches for a module and its submodules. The value for a top-level module is the total number of latches in the design. See also Modules Constraint Entry. w38}Modules Constraint Table After Optimization For optimized implementations, the Modules constraint table displays these additional columns: Area This column displays the number of lookup tables for a module and its submodules. The value for a top-level module is the total number of lookup tables in the whole design. The column displays a question mark (?) when the module contains black boxes. For a detailed report, click the cell in this column and select Details... from the drop-down list to bring up the Cell Counts window. Flip-flops This column contains the number of flip-flops for a module and its submodules. The value for a top-level module is the total number of flip-flops in the design. Latches This column contains the number of latches for a module and its submodules. The value for a top-level module is the total number of latches in the design. See also Modules Constraint Entry. ~'Modules Constraint Table Icons The icons in the Modules constraint table have these meanings:  Entity or module containing other entities or modules  Entity or module }b89WTechnology-Specific Options When you click the right mouse button on an elaborated implementation and select Edit Constraints, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables. If there are additional controls for the selected device, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express also includes a tab and dialog box for that technology with the constraint tables. See: Options for Actel Devices Options for Altera Devices Options for Lucent Devices Options for Xilinx Devices General Technology-Specific Options RTechnology-Specific Options When you click the right mouse button on an elaborated implementation and select Edit Constraints, FPGA Compiler IIFPGA Express displays the constraint tables. If there are additional controls for the selected device, FPGA Compiler IIFPGA Express also includes a tab and dialog box for that technology with the constraint tables. See Options for Xilinx Devices. A_8bOptions for Actel Devices Use this dialog box to specify a maximum fanout for a specific implementation targeting an Actel device. The maximum fanout value can be between 2 and 24. You can also choose a different mapper by enabling advanced optimization. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses an advanced optimization algorithm if you check this box. This option might produce improved quality of results. Note that compilation time might increase.  rFOptions for Altera Devices Use this dialog box to toggle LCELL buffer insertion and style for a specific implementation targeting an Altera FLEX device. A check in this box means these specifications at optimization: insert LCELL buffers in the EDIF netlist and specify WYSIWYG (what you see is what you get) style in the constraint file (ACF) for place and route. If this option is not selected, no LCELL buffers are inserted and the logic synthesis style is FAST. Use this dialog box also to enable the Register Retiming feature for APEX20K and FLEX10K devices in FPGA Compiler II Altera Edition. Register Retiming supports pipelining and also balances delay between registers. For more information, see.Performing Register Retiming in FPGA Compiler II.  See Project Options to set defaults using the Synthesis > Option dialog box. .=8Options for Lucent Devices Use this dialog box to control GSR inference for the device. A check in the box enables GSR mapping for designs unlinked cells or black boxes.  lOptions for Xilinx Devices Use this dialog box to set these options: Ignore unlinked cells during GSR mapping A check in this box enables GSR inference for designs that contain unlinked cells or black boxes. Buffer internal nets A check in this box inserts clock buffers to drive high fanout internal nets. Perform retiming A check in this box enables Register Retiming for XC4000, Spartan, and Virtex devices in FPGA Compiler II. Register Retiming supports pipelining in addition to balancing delay between registers. For more information, see the application note Performing Register Retiming in FPGA Compiler II.  [8eGeneral Technology-Specific Options You can select whether to infer LPM operators from HDL code, or to have FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express build these operators using generic gates. In general, it's advisable to leave these options checked unless you know that your selected vendor or device family does not support LPM.Create Project Report dialog box Creates a text report on the project including library, design source files, and optimized and unoptimized implementations. Selecting File > Project Report or clicking on the Project Report icon in the tool bar opens the Create Project Report dialog box where you can name your report. Browse the hierarchy with the drop-down list in the Save in field. You can create a new directory (folder) for your report by clicking the New Folder button. [8_Create Implementation dialog box Create a design implementation by specifying a vendor and architecture for the design. You can also specify the target device and speed grade. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates a design implementation by synthesizing logic from individual design sources and logically linking them into a structured hierarchy. See also: Implementation Name Vendor Family Device Speed Grade Optimize for Speed or Area Optimization Effort Clock Frequency Preserve Hierarchy Do Not Insert I/O Pads Skip Constraint Entry 6Implementation Name To specify a name for the implementation, type a name in the Implementation Name dialog box. By default, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates a unique name using the top-level design name as its base. For designs described in VHDL, this is the name of the entity; for designs described in Verilog, this is the name of the module. You can override the default by typing in a name. In parentheses, each chip name includes the names of the target technology vendor, the family, the device, and the speed grade. 386Vendor Selects the FPGA vendor of your target device. 8Family Selects the device family of your target device. 38CDevice Selects the specific die and package of your target device. ;Speed Grade Selects the speed grade of your target device. ^8 Optimize for Speed or Area Controls whether FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes for faster speed or smaller area. The default is to optimize for speed Optimization Effort Controls the mapping effort for this design. This option affects timing optimization most with little influence on area. Low effort takes the least time to compile. Use low if you are running a test to check the logic. Low is not recommended if the design must meet area or timing goals. High effort takes longer to compile but should produce better designs. The mapping process proceeds until it has tried all strategies. la8 Skip Constraint Entry To skip constraint specification for the design, check the Skip Constraint Entry box. If you select this option, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express elaborates and optimizes the design implementation when you click the OK button. The program does not pause after creating the elaborated implementation to let you enter design constraints. Do not select this option if you want to specify detailed design constraints and optimization options. To enter or modify constraints after optimization, right-click the elaborated implementation and select Edit Constraints. Note: You generally obtain best performance when you fully specify constraints. +TDo Not Insert I/O Pads To specify that I/O pads should not be inserted at optimization, check the Do Not Insert I/O Pads box. This option indicates that this design implementation is a module in a larger design and I/O pads are not relevant. Selecting this option has these implications: You cannot define pads or their location. Manually instantiated I/O pads from the design source files are not preserved. Global buffers cannot be specified and are not automatically inferred. Global set and reset are not implemented or inferred. Timing constraints are not exported in the netlist file. . S8;XDo Not Insert I/O Pads To specify that I/O pads should not be inserted at optimization, click the Do Not Insert I/O Pads check box. This option indicates that this design implementation is a module in a larger design and I/O pads are not relevant. Selecting this option has these implications: You cannot define pads or their location. Manually instantiated I/O pads from the design source files are not preserved. Global buffers cannot be specified and are not automatically inferred. Global set and reset are not implemented or inferred. Timing constraints are not exported in the netlist file.  JNClock Frequency To specify the general clock frequency for a design implementation, enter its value in the Clock Frequency field. If you do not enter a frequency, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the default value from the General tab of the Options dialog box in the Synthesis > Options menu. 28SDefine Clock In the Clocks constraint table, you can specify the rise time, fall time, and period of the designs clock signals. See also: Period Rising Edge Falling Edge dePeriod To specify the period of the clock signal, enter the value of one full period in nanoseconds. 28mRising Edge Offset of the rising edge of the clock. The rising edge can be anywhere within the clock (0 to period-1) except at the same offset as the falling edge. vFalling Edge Offset of the falling edge of the clock. The falling edge can be anywhere within the clock (0 to period-1) except at the same offset as the rising edge. 28Clock Signal Definitions Period - One full period of the clock signal in nanoseconds Rise - The time of the rising edge of the clock signal in nanoseconds Fall - The time of the falling edge of the clock signal in nanoseconds Define Path Delay In the Paths constraint table, you can specify maximum delays between commonly clocked or enabled timing groups and external input and output delays relative to those path groups. See also: Delay Timing Group 28cPath Delay Specify the path delay from one timing group to another with values in nanoseconds. iTiming Group Timing groups  consist of logic cells with common timing behavior A timing group is one of these types: all inputs, all outputs, all flip-flops or latches clocked by the same clock. Internal timing paths are separated by cell type (flip-flop, latch), active clock edge or enable level (rising, falling, high, low), and clock or enable signal. b86Select Top-Level Design Select the Top Level-Design from the drop-down list. The top-level (or root) design may have been renamed. Because FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the top-level design as the starting point for design hierarchy, it must always be defined. pUpdate Optimized Implementation You should update the optimized implementation because FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has detected that the elaborated design implementation is newer than its optimized implementation. Design constraints were edited or a new elaborated implementation was created since the last optimization. ^8Open Open an existing FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project in a new window. When you open a project, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically saves any currently open projects. Editing Constraint Table Entries You can enter and view FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimization constraints through a set of constraint tables for each implementation. Editing these tables is similar to editing a popular spreadsheet with the additional functionality of being able to copy values from related fields. For explanations of the various fields and regions in constraint tables, refer to the Help Index.  For more information, use the following links: Constraint Page Tabs Columns Rows Name Direction Disabled Areas Default values Default Row Empty Fields Specific Entry Combo Selection $8Constraint Page Tabs The constraints are organized under tabs as property tables. When you select a tab, the table becomes visible. Note that hidden tables are not closed or saved, merely covered. Data is saved only when the whole Constraint window is closed. wColumns Data is organized in columns of similar entries for each of the named objects (ports or modules, for example). 'a8Rows In most tables, the first row shows default settings. Subsequent rows show the individual settings for specific ports, modules, and so forth. If you do not enter specific overrides, the default settings apply to the object type. For ports, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses defaults for individual ports where applicable (for example, certain values cannot be applied to input or output ports). For modules, values are inherited hierarchically. cName The first column of each table usually lists the object name (ports or modules, for example). 718Direction The port directions listed are from the source of the design (VHDL or Verilog). In certain cases, you can override the direction in the pad direction column of the Ports constraint table. vDisabled Areas Areas that are not applicable for a particular object are disabled (grayed), and no entry is possible. 418Default Values Values that are defaults inferred from other settings are displayed in italics. Values that you specifically enter are displayed in normal font. &vDefault Row The value in this row is applied to all ports, modules, and so forth that do not have specific overrides. 6180Empty Fields Fields with no entries inherit the value specified in the default row. If there is no default value, fields with no entries use the system default. :Specific Entry This is an example of a field with a specific valuein this case, one of a list of valid settings. Optimization uses this value, not the default setting in the first row. 118DfCombo Selection Most fields let you select values from a combo list. The combo list contains values that have been used for other fields (which may be easily copied) and, where applicable, a standard Define command that invokes a dialog box for configuring complex settings. Double-clicking a field is equivalent to selecting Define from the drop-down list. NCell Counts Displays the cumulative cell count of every target primitive cell instance in the designs subhierarchy. The Cell Counts window includes any unlinked cells in the design. To exclude subhierarchy instances, clear the Counts Cumulative for All Subhierarchy check box. The Cell Counts window displays the cell count of subdesigns and primitives in the current design. List of cells Counts cumulative for all subhierarchy I8]List of Cells This list of library primitives shows the number of each type. Black boxes are indicated by module or entity name in the list and marked with a question mark (?). fCounts cumulative for all subhierarchy If this is checked, the cell counts listed reflect the whole design hierarchy below the selected entity/module instance. If cleared, the counts reflect the selected entity/module instance only. [8o Adding Source Files FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express source files can be any combination of VHDL, Verilog HDL, or FPGA netlist files. Each source file is automatically analyzed for syntax errors as it appears in the project window. You can find explanations of any source file errors in the online language reference manuals, accessible from the Windows Help menu. Source files are not copied; they are added and analyzed in their present location. By default, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express remembers absolute path names. See Source File Location for more information about path names. If changes are made to the files (indicated by a ? icon), reanalyze the files so that they are updated in the project. |Exporting Netlists for Xilinx Specify a folder or directory to hold the optimized design files formatted into Xilinx Netlist Format (XNF). Depending on the hierarchical structure of a design, there may be more than one file. The name of each optimized design file corresponds to the top-level design name with an .xnf suffix. Timing constraints are not included in the netlist file for any design that you compiled with the Do Not Insert I/O Pads option selected. If you choose the Export Timing Constraints option, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express exports the timing constraints in the top-level .xnf file. V8pExporting Netlists for Lucent Specify a folder or directory to hold the optimized design file formatted into Electronic Data Interchange Format (EDIF). The name of each optimized design file corresponds to the top-level design name with an .edn extension If you choose the Export Timing Specifications option, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express exports a Synopsys preference file whose name corresponds to the top-level design name with a .prf extension Timing constraints are not included in the netlist file for any design that you compiled with the Do Not Insert I/O Pads option selected. Exporting Netlists for Altera Specify a folder or directory to hold the optimized design files formatted into Electronic Data Interchange Format (EDIF). The name of each optimized design file corresponds to the top-level design name with an .edf extension In addition to the EDIF file, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express exports an assignments and constraints file (ACF) containing design constraints and a library mapping file (LMF) containing descriptions of the library cells used in the EDIF file when targeting MAX and FLEX devices. For APEX devices, the ACF is replaced by a TCL script file containing project information. The names of these files correspond to the top-level design name with an .acf extension for the ACF and an .lmf extension for the LMF. Timing constraints are not included in the netlist file for any design that you compiled with the Do Not Insert I/O Pads option selected. p8WImporting Constraints into an Implementation Use this dialog box to read an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express constraints file and enter the performance constraints, attributes, and optimization options directly into the active, open implementation. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express merges the imported values with those in the open design implementation. For definitions of timing and module constraint terminology, see these topics: Timing Terminology Port and Pad Terminology Module and Hierarchy Optimization Terminology Exporting Constraints from an Implementation Use this dialog box to save the performance constraints, attributes, and optimization options specified in the active implementation and export them to a file. The exported constraint file is not used for reporting or editing. To edit constraints, use the Implementation window. To create a constraint report, use the Report command. You can save time and the reduce the risk of replication errors by using the Import Constraints command to apply the information in this file to a similar design. For definitions of timing and module constraint terminology, see these topics: Timing Terminology Port and Pad Terminology Module and Hierarchy Optimization Terminology }S8Create New FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Project Enter the name of the project and navigate the directory tree to specify where to store it. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates a project file and a new directory and subdirectories to store internal and intermediate files. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates the project and immediately opens the Add Source Files dialog box so you can add the source files for this project. Add Sources Enter the names of the design source files and navigate the directory tree to specify where the files are located. The files are not copied, but are added to the selected library. See Analysis Order when order is important. T8`New Library Name Enter the name for a new library. You can add new libraries to your project at any time by clicking the right mouse button in the Design Sources window and selecting New Library. However, if a library contains packages or other files that must be analyzed before other files are analyzed, create them first. See also Analysis Order. Diagnose License Problem FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses a flexible licensing system which gives end users and system administrators many configuration options, but which can also have unexpected side-effects, especially when multiple applications using the same licensing mechanism are installed side-by-side. For more information, see: Specific License Location Current value of LM_LICENSE_FILE Check shared license location a8Specific License Location Enter the path for the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express-specific license file in this field. This file should not be accessed by other applications.  =Current value of LM_LICENSE_FILE This non-editable field shows the license location shared by multiple applications. See the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Installation Guide or the FPGA Installation Guide for a description of ways to set the environment variable LM_LICENSE_FILE. [8 eCheck shared license location FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express should check the shared license location for the license file. See the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Installation Guide or the FPGA Installation Guide for information about setting the environment variable LM_LICENSE_FILE.  General Options tabOptions dialog box You can use the following options to configure the appearance and behavior of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. These options apply to all subsequent projects. For more information, see: Show full pathnames of source files Warn before deleting files and chips Show Add Files dialog box after creating project Use FPGA Compiler II Altera Edition FPGA Express internal source editor Default clock frequency when creating new chip :c8- Show full pathnames of source files By default the file names shown in the project file window are short (just the file name). If you have large projects with sources from several directories, it can be useful to see the full path names to ensure there is no ambiguity. When you check this box, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the full path of each file. 6 xWarn before deleting files and chips When you select this option (the default), FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express prompts before removing any source files or chips from the project. When you clear this box, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express deletes files and chips from the project without warning first. b8? FShow Add Files dialog box after creating project When you select this option (the default), FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically prompts for source files when you create a new project. When you clear this box, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not automatically prompt for source files at project creation. If you are familiar with the drag and drop capability of the Windows File Manager or Explorer programs, you may prefer to switch this option off and drag files from an appropriate browser. I Use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express internal source editor FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has an integrated, built-in HDL Editor that you can use to edit design source files when you select Edit File from the Design Sources window. You can find next and previous errors and analyze a file without leaving the editor. By default, this option is selected. If you have an external editor with which you are more familiar or which provides other useful capabilities, clear this box, and ensure that your editor is associated with the appropriate file extensions (using the standard capabilities integrated with the Windows File Manager and Explorer programs). >T8T ]Ask before creating directory Setting this prompts the user before directories are created. ] Default clock frequency when creating new chip When you create a new chip, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express offers a default frequency for the primary clock of the chip. Use this field to set the default as appropriate for your current project. 2`8f Project OptionsOptions dialog box Use this dialog box to control project defaults: FSM synthesis: Default encoding (takes effect on file analysis) These buttons control the encoding for finite state machines (FSM) in VHDL designs. Choices include One Hot (default), Binary, and Zero One Hot. FSM synthesis: Interpretation of VHDL when others These buttons control implementation of the when others selection in the VHDL case statement describing the state transition logic. Choices include fastest & smallest (default) or safest. fastest & smallest provides the best implementation when illegal state transitions can be ignored. If recovery from illegal state transition is necessary, choose safest. To ensure the fastest & smallest FSM implementation, omit the when others statement from your FSM descriptions. See How to Specify Finite State Machines for more information. Default Export Timing specifications option to YES This check box sets the default for the Export Timing Sf pecifications option when you export a netlist. Insert LCELL buffers, style WSIWYG (Altera FLEX only) For Altera FLEX devices, a check in this check box means these specifications at optimization: insert LCELL buffers in the EDIF netlist and specify WYSIWYG (what you see is what you get) style in the constraint file (ACF) for place and route. If this option is not selected, no LCELL buffers are inserted and the logic synthesis style is FAST. A change to this setting takes effect the next time you create an implementation. Enable Verilog Preprocessor Verilog Preprocessor constructs such as 'ifdef, 'else, 'endif are disabled by default. To enable the Verilog Preprocessor for subsequent HDL analyses of Verilog files, open the Project Options dialog box and check the Enable Verilog Preprocessor box. Note: You must reanalyze any previously analyzed files. Otherwise changes do not affect the synthesized RTL. Input XNF Bus Style Enter the XNF (Xilinx Netlist Format) bus style for reading 8`8f bXNF netlists when your target technology is Xilinx. You must specify how the buses of the design are expanded into individual signals because XNF has a wide variety of bus styles. If FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express cannot determine which individual signals in the XNF netlist to map to the bus signals defined in the HDL code, you might get a Failed to Link error message. For example, if the buses have the format name in the XNF netlist, set the XNF Bus Style to: %s<%d>. A change to this setting takes effect the next time you create an implementation. See Bus Naming Style . Export Directory You can specify the default directory in which netlists are stored during Export Netlist. Save these settings as user defaults for new projects. This check box controls saving these settings for other new projects.  ^s<%d>. A change to this setting takes effect the next time you create an implementation. See Bus Naming Style . Export Directory You can specify the default directory in which netlists are stored during Export Netlist. Save these settings as user defaults for new projects. This check box controls saving these settings for other new projects. 8`8 {ing Specifications option when you export a netlist. Enable Verilog Preprocessor Verilog Preprocessor constructs such as 'ifdef, 'else, 'endif are disabled by default. To enable the Verilog Preprocessor for subsequent HDL analyses of Verilog files, check the Enable Verilog Preprocessor box. Note: You must reanalyze any previously analyzed files. Otherwise changes do not affect the synthesized RTL. Input XNF Bus Style Enter the XNF (Xilinx Netlist Format) bus style for reading XNF netlists when your target technology is Xilinx. You must specify how the buses of the design are expanded into individual signals because XNF has a wide variety of bus styles. If FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express cannot determine which individual signals in the XNF netlist to map to the bus signals defined in the HDL code, you might get a Failed to Link error message. For example, if the buses have the format name in the XNF netlist, set the XNF Bus Style to: % Optimization OptionsOptions dialog box In this dialog box, you can enable duplicate register merges and can specify register duplication for Actel ProASIC 500K, Altera APEX20K, Lucent Orca3, Xilinx XC4000, Spartan, and Virtex devices. ]8 LPM OptionsOptions dialog box In this dialog box, you can select, on a per-vendor basis, whether to infer LPM operators from HDL code, or to have FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express build these operators using generic gates. In general, it's advisable to leave these options checked unless you know that a vendor or device family does not support LPM.  Create / Edit Timing Subpath FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically extracts all timing paths that exist between clock edges (primary timing paths), and lets you constrain those paths with a maximum delay. When a subset of the actual paths within a primary timing path need a tighter constraint to ensure correct behavior, you can define a timing subpath. Subpaths appear as children of the primary paths and may be expanded or collapsed by double clicking the [+] icon. Create a new subpath by clicking the right mouse button on either the appropriate primary path or any subpath of the primary path, and selecting New Sub path. To edit an existing subpath, click the right mouse button on it and select Edit Sub path. The Create/Edit Timing Sub Path dialog box displays a delay field and all the cells in the from and to groups. Each group has a set of controls for adding and removing cells from the from and to lists. In the Create/Edit Timing Sub PathcS8 P dialog box, enter the desired delay, and then double-click all cells that make up the subpath. The controls below each list give an alternate way of adding named cells to the list using global-style regular expressions (similar to filename wildcards). To add a set of named cells to a list, type in the expression to match (for example, *_ENAB) and then click the appropriate Select button. For more information, see: Primary Path Subpath Name Delay From cell list To cell list From / To Select All From / To Clear All From / To Select expression From / To Select  xPrimary Path This is a non-editable field displaying the name of the primary path for which you are creating a subpath. 28 Subpath Name This name identifies the subpath in reports and in the Paths constraint table for an optimized implementation. The name appears in the From and To columns suffixed with From and To respectively.  )Delay The delay for the current subpath. 28 eFrom cell list The list of cells comprising the subpaths From group. To toggle the selection of a cell, double-click it. The reason for this divergence from the normal use of windows selection clicks (in which click selects current, shift-click selects a range, control-click toggles) is to prevent the loss of a complex selection by a mistaken keystroke.  aTo cell list The list of cells comprising the subpaths To group. To toggle the selection of a cell, double-click it. The reason for this divergence from the normal use of windows selection clicks (in which click selects current, shift-click selects a range, control-click toggles) is to prevent the loss of a complex selection by a mistaken keystroke. 28 mFrom / To Select All Selects all cells in the appropriate list, regardless of their current selection state.  xFrom / To Clear All Clears selection of all cells in the appropriate list, regardless of their current selection state. Z8 From / To Select expression Enter a regular expression by which a set of cells can be added to the current From or To list. The cells matching an expression in this field are added to the appropriate list by clicking the associated Select button. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not retain the expression text after you close this dialog box and the selection is made only after you click the Select button. + lFrom / To Select Adds the cells matching the expression in the associated edit field to the selection list. V86 Export Netlist dialog box Creates an optimized EDIF or XNF netlist for place-and-route. Optionally creates a VHDL or Verilog netlist for functional simulation.  To enable timing constraint exports, check the Export Timing Specifications box. EDIF Bus Styles option The option labeled Bus Style in the Place and Route section of the Export Netlist dialog box adds control for the bus style for EDIF output. Bus information for top-level I/O can be preserved or eliminated. The default setting, Expand, causes each bit of a bus to become an individual I/O port. The other settings include delimiters for different bus style notations: [], <>, (), and {}. Please consult the FPGA vendor documentation to determine which bus style setting is appropriate for your design. Generate Synopsys db Files option (FPGA Compiler IIFPGA Compiler II Altera Edition only) Exports .db files along with the netlist. This enables projects created in FPGA Compiler IIFPGA Compiler II Altera Edition to be 6 integrated into your design flow with other Synopsys tools. These files are placed in the location specified in "Export Directory" option. To access this feature from the command line, use the -db switch with the export_chip command. Note that FPGA Compiler IIFPGA Compiler II Altera Edition creates two .db files. For a design called test, for example, one file, named test-Optimized_des.db, describes the design. The other file, named test-Optimized_lib.db, contains the technology library primitives used in the design. For more information, see the ASIC to FPGAPLD Migration Using FPGA Compiler IIFPGA Compiler II Altera Edition application note. U8U yExport FPGA Shell Script dialog box Specifies the location of an exported FPGA shell (fc2_shell or fe_shell) script.  a ,Export Design Compiler Script dialog box Specifies the location of an exported Design Compiler script file (FPGA Compiler IIFPGA Compiler II Altera Edition). For more information, see the ASIC to FPGAPLD Migration Using FPGA Compiler IIFPGA Compiler II Altera Edition application note.  ɻ8m Welcome to FPGA Compiler II! This introductory chapter of your online manual contains the following information: What is FPGA Compiler II? FPGA Compiler II Benefits of Using FPGA Compiler II Using FPGA Compiler II For information about program basics, see these topics: Launching the Program Starting Work in FPGA Compiler II Finding Help and Information Tips on Using FPGA Compiler II Glossary  What is FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express? FPGA Compiler II Altera Edition is a complete FPGA logic-synthesis and optimization tools. With it you can create optimized FPGA netlists from VHDL code, Verilog HDL code, and existing, unoptimized FPGA netlists. The following figure shows how FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express fits into your FPGA design flow:  In this flow, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express perform the following steps: Use the integrated text editor for entering VHDL and Verilog HDL source code for your design. You can also use the text editor in the analysis step (described next) for easy debugging of design source files. Analyze HDL (VHDL and Verilog HDL) design source files for correct syntax using the Synopsys industry-standard HDL language support. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express accepts any combination of VHDL, Verilog HDL, and FPGA netɻ8 list files as sources for a design. For example, you can use functions or subdesigns created through schematic capture and Verilog within a VHDL top-level design. After you add the design source files, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically analyzes the HDL files. If the source files contain errors, the Output window and text editor help you find and correct problems. Elaborate from VHDL, Verilog HDL, and FPGA netlist source files, targeting a specific FPGA architecture and device. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesizes the logic of your design, using architecture-specific algorithms to target devices from the leading FPGA manufacturers. In this part of the design flow, the program elaborates each design module and creates and links the design hierarchy to form a unique design implementation. After this step, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express generates schematics of your de sign, so you can verify the function and timing of your circuits. Optimize logic for speed and area as directed by your design constraints, generating an FPGA netlist file that is ready for place and route by FPGA vendor tools. With the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express graphical user interface (GUI), you can enter constraints for your design in editable tables. The constraints contain performance requirements and optimization options for architecture-specific optimization engines. When it has completed optimization, the program generates a netlist ready for place and route by the FPGA vendor tools. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express also creates reports of its results. After this optimization, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express again generates schematics of your design, so you can verify the function and timing of your circuits. Extract and display accurate post-synthesis delay informatioɻ8 n for timing analysis and debugging. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays timing information beside your design constraints and highlights timing violations. This information is linked directly to the schematics, so you can easily decide whether to place and route the design or make design changes. See Benefits of FPGA Compiler II Altera Edition FPGA Express:  FPGA Express FPGA Express core technology was developed specifically for FPGA and programmable logic device (PLD) architectures with the following features: Architecture-specific mapping and optimization for all leading programmable logic devices Industry-leading quality of results Standard Verilog and VHDL support Easy-to-use design flows and graphical user interfaces Integrated static timing analysis with TimeTracker TCL-based scripting language for true batch and command-line modes ƻ8 I Altera Edition.  sts only in FPGA Compiler IIFPGA Compiler II Altera Edition. For more information, see the application note "ASIC to FPGAPLD Migration Using FPGA Compiler IIFPGA Compiler II Altera Edition." DesignWare Foundation supportFPGA Compiler IIFPGA Compiler II Altera Edition recognizes instantiated DesignWare Foundation components to support design reuse. For more information, see the application note "Using DesignWare Foundation in FPGA Compiler IIFPGA Compiler II Altera Edition." This feature exists only in FPGA Compiler IIFPGA Compiler II Altera Edition. Platform-independent licensing for UNIX and Windows NT. This feature exists only in FPGA Compiler IIFPGA Compiler II Altera Edition. Note: For users of the original FPGA Compiler software it is highly recommended that you install the new FPGA Compiler IIFPGA Compiler II Altera Edition software. All in-maintenance FPGA Compiler customers have been automatically upgraded to FPGA Compiler IIFPGA Compiler Ic[8  increases productivity because HDL source code is vendor independent, retargetable, and reusable. Because the program takes HDL source code as input, you have the above advantages in addition to the built-in optimization programs specifically tuned for each FPGA vendors device family. Using Common, Familiar Systems The FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Windows-compliant GUI uses standard commands and procedures to accept all your input values; no command scripts are required for constraint entry. A complete set of Tcl-based commands is included for batch or interactive command-line operation. For more information about these commands, see the online help or the man pages available from the scripting shell. Synthesizing With Flexible Design Flows FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express accommodate various design styles and performance goals with multiple synthesis design flows. Your FPGA design can be either complex or simp|N Y8 FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express in Your Design Flow Your design methodology determines how you use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express in your design flow. Entering Designs into FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express supports the following methods of describing FPGA designs: HDL-based design methodology uses only HDL source code for design entry.  You can enter one or more VHDL or Verilog HDL files describing any hierarchical design structure. You can then split the design into hierarchical functional blocks or create a single flattened design description. This feature makes it easy to reuse modules from a common design library or design source. Schematic-based design methodology uses schematics for design entry. This design methodology adds only one step to a traditional FPGA design process, but it can produce improved area an d performance. Mixed design methodology uses a combination of HDL source code and schematics for design entry. In this design methodology, the HDL source code is synthesized, combined with netlists from schematic entry, and optimized into a netlist ready for FPGA place and route tools. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express allows you to divide a design between HDL and schematic input in any proportion and create virtually any design hierarchy. You can also use functional blocks made from both schematics and HDL to reuse modules from common design libraries or design sources.  For a description of these steps, see Design Flow Overview. f]8YSynthesis / Edit File command OLaunching the Program FPGA Compiler IIFPGA Compiler II Altera Edition You can launch FPGA Compiler II from Windows, Solaris, and HP UX Windows: From the Start menu, choose Programs > Synopsys > FPGA Compiler II. Solaris and HP-UX: Make sure that fc2/bin is in your path. Then type fc2 to start the program. To launch the scripting tool (FST) for FPGA Compiler IIFPGA Compiler II Altera Edition, enter fc2_shell. FPGA Express To launch FPGA Express, choose Start > Programs > Synopsys > FPGA Express from the Windows Start menu. To launch FST for FPGA Express, enter fe_shell. 0|8+RA  |&WordMicrosoft Word  4System    -@Times New Roman*wgw  - 4&{|C )z()t6+0|8++ 0|8+ + + 𻻻 "໻+ K "wp+ 𻻻 + ""+ " DD ""+wwwp" 𻻻 """" ""+ DDDD """"wwwwwp""+ 𻻻 """+  """"DDDDD """+wwwwww{"""" 𻻻0|8+ 񻻻""໻ """+DDDDDDD""wwwww"""+ 𻻻  񻻻"+  ""DDDDDDDK"+www"" 𻻻 񻻻"  "+DDDDDDD"w"+ + " "DDDDD""໻𻻻 񻻻 "DDD" 𻻻໻ ໻ D 0|8+𻻻  ໻ D@ 𻻻໻ 񻻻 ໻ DDD@ 𻻻dH  ໻ DDDDD@ + ໻fdD  ໻  DDDDDDD@K w  fff 𻻻 ໻ ໻DDDDDDDDD www  fff`   ໻  DDDDDDDK0|8+wwwww  ff  ໻DDDDDKwwwwwww f    DDDKwwwww{   +DKwww{  w{໻ 0|8++0|8+&'&tZ--%xx--&i@ Arial i!w*wgw i -l. 2 l4Create project<......*.'&#--%''I--&+u 3-  3.2 3 4Open projectA......*.*l'&$8 --%((--&w H4- K4.2 K44Identify...'.*l4.2 44sourcesy*..*.*.'&s --%#--&dd "- ".2 "4Update<.....*l'& M --%H H V--&>  -  .a8++2  4Create implementation<...G..G......*l-'& 5)--%00--&' -  .2  4OptimizeA.G(..*l-'&  --%o--&0 - 3 . 2 3 4Export netlist7*....*.*l-'-.2 "4Update<.....*l'& M --%H H V--&>  -  . .Starting Work in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Express To begin using FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, create or open a project. Follow the enabled tool bar icons from left to right to perform the steps for optimizing your design. Update  To become familiar with design flow and key features of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, step through the online Quick Tour (from the Help menu) and refer to the tutorial in the Help and FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Getting Started. For help on specific topics, choose Help > Help Topics for a table of contents, an alphabetical index, or a text search. For a brief description of a specific feature of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, use context-sensitive helpclick the Context Help button or press Shift-F1 and click an object on the screen. For a good hands-on tour of FPGA CompZ80 using the menu or the Play button. The Quick Tour is available only on PC installations of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. Tool Bar and Tip Bar The tool bar and tip bar guide you through the design flow. The tool bar contains icons for each step in the design flow. Clicking all the buttons from left to right automatically takes you through the entire design flowfrom project creation to netlist generation. The tip bar provides tips and information at each stage of the design flow. It automatically detects the state of the design and identifies the next logical step in design flow. The tip bar also provides a brief explanation of the function and purpose of each step. Context-Sensitive Help For a brief description of a specific feature of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, use context-sensitive help. Click the question mark button on the tool bar or press Shift-F1, then click the item. Detailed Online Help For more deta0 8iled information, choose the Help System command from the Help menu. You can access specific help topics by a table of contents, an alphabetical index, or a text search. Output Window Information The Output window automatically displays errors and warnings for each action you perform on a design source or chip. It also displays warnings and messages about selected chips. You can use the information in this window with the built-in HDL editor for debugging. Compiler Reference Manuals Online reference manuals for VHDL and Verilog HDL contain complete language descriptions and their application to FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesis and optimization. You can find the all compiler reference manuals on the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express CD-ROM. Vendor-Provided Documents Also available from the Help pull-down menu is a selection of documents provided by FPGA vendors. You may find these helpful in answering some of8;hExpress converts the frequency into a waveform rising at time 0 and falling at one half of the period. Q  Results. b8Q Tips on Using FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express The following tips will help you use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express more efficiently. Mouse Behavior Left button click: Selects and deselects. Double-click: In the Design Sources and Chips windows, expands or contracts the hierarchy of the project, library, or file. On an error in the Error/Warnings window, starts the text editor and opens the design source file to the selected error. Right button clickbrings up a context menu of activities for: The source file in the Design Sources window and the editor. Unoptimized or optimized implementations in the Chips window. The messages in the Errors/Warnings window. Subpaths in the Timing Constraints table. If you want to . . . Expand or contract a project, library, or file tree: Double-click the icon. Add to a library: Click the Add Sources tool bar button Choose Synthesis > Add Sources. View extended help oQ n an error or warning: In the Output window, double-click the error number. Use the Help Index to locate the error number. Modify a design source file using the editor: In the Design Sources window, right-click the file icon and choose Edit File. In the Output window, double-click the error text. Enter constraints for an implementation: Right-click the implementation and choose Edit Constraints. Specify timing constraints on arbitrary timing paths: Right-click the path in the Timing Constraints and choose Create Subpath. Copy data within a row or column: Copy the selection with Edit > Copy and paste it into the destination cell with Edit > Paste. Select the cell containing the data you want to copy and the cells to which the data should be copied. Press Control-d or select Edit > Fill down. Run timing analysis on an implementation: Right-click the optimized implementation and choose View Results. View the results of optimization: Right-click the implementation and choose Viewb8 \Glossary These topics define FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express terminology: Analysis Terminology Global Buffer Terminology Global Set and Reset Terminology Implementation Terminology Module and Hierarchy Optimization Terminology Port and Pad Terminology Project Management Timing Terminology  ,Tutorial The fastest way to learn to use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express is to complete this tutorial, which follows the program design flow: 1. Creating Design Source Files 2. Setting Up a Project  3. Synthesizing the Design  4. Entering Design Constraints and Controls  5. Optimizing a Design Implementation  6. Analyzing Timing 7. Viewing Schematics 8. Generating optimized FPGA netlists and reports  This tutorial also contains information on running the FPGA Scripting Tool (FST). Va8 Creating Design Source Files The first step in the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design flow is to create HDL source files. You can use any text editor to enter VHDL and Verilog HDL source code for your design. You generally perform this step outside FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. However, you can also use the integrated HDL Editor to edit a design source file once it has been read into a project.  Setting Up a Project The key components of a project are source files describing FPGA designs. Source file types are VHDL, Verilog HDL, or netlist. Netlist files usually originate from schematic capture systems or preoptimized macro libraries. Setting up a project in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express involves these steps: Creating a project. Creating libraries of design source files. Analyzing and debugging source files. S8  II Altera EditionFPGA Express displays the Create New Fexp Project dialog box.  In the Create New Fexp Project dialog box, you can choose a location for the project. Use the drop-down list in the Save In field to navigate your directory tree. You can click the Create New Folder icon to create a new directory.  Type the name tutorp for the project folder (directory). The tutorp directory is where project files will be stored. Click the Create button to create the new project. After the program creates the tutorp project, the Add Sources dialog box opens. For the next step, see Creating libraries of design source files  Creating a Project After you prepare the project source files, start the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design flow by creating an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project. When you create an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project, the program creates a new folder (directory) in which to store the project information. To create a new project in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express: Start FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express from the Start menu (Start > Programs > Synopsys > program_name). This opens the main window. When you start FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, you can open an existing project or create a new one. For now, create a new project by clicking the Create Project button in the tool bar or by choosing New from the File menu. In the startup window, FPGA Compiler IIFPGA CompilerQ8 Adding Design Source Files After you create the project, the next step is to add design source files. Whenever you create a project, a default library named WORK is automatically put into the project folder. Libraries contain design source files. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express source files can be any combination of VHDL, Verilog HDL, or FPGA netlist files. When you add source files to a project library, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically analyzes the files for syntax errors, warnings, or any other information. If there are errors, you can find detailed explanations of the problems in the online help. In VHDL environments, it is sometimes necessary to have multiple libraries. You can add a library at any time by right-clicking in the Design Sources window and choosing New Library. Then add design sources to that library in the same way you did for WORK. In Verilog, there is no analogy to a library constru ct and therefore no advantage to creating new libraries. Note FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not copy design source files. When you add these files, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express analyzes them in their current location. If you are required to make changes to the files (indicated by a ? icon), you must click the Update button in the tool bar or right-click in the Design Sources window and choose Update File so that FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express will reanalyze the files and update the project. To add source files: Make sure the Add Sources dialog box is open. If this dialog box is not open, you can also access it by clicking  on the tool bar, by choosing Synthesis > Add Source Files, or by right-clicking in the Design Sources window and choosing Add Sources in the WORK library. Select source files from the Add Sources dialog box. (This dialog box was opened in the previouQ8 s step.) For this tutorial, use the tutor design files written in VHDL (tutor.vhd, counter.vhd) or Verilog (tutor.v, counter.v). These files are located in the Synopsys > FPGA_CompilerII or FPGA_Express > samples > tutorial > vhdl or verilog directories. To add a source file to a library other than WORK, right-click the library and choose Add Sources In. When you have selected your design sources, click Open.  Note: On the PC, you can also drag and drop source files into the Sources window to add them to the project. After you have selected your design sources, the program displays the project window and extends the menu bar. The project window is divided into two windowsthe Design Sources window and the Chips window. The Design Sources window displays the name, location, and status of the design's source files. The Chips window displays information for individual design implementations such as name and device type.  Note that the project window title bar displays the name of th e project. Each source file is automatically analyzed as it appears in the project window, and the icon to the left of each file name indicates the results of the analysis.  In this tutorial, the counter file has at least one error (indicated by the red cross) that must be corrected. The green check marks next to the other files indicate that the files have no errors or warnings. The error in the one source file is reflected up the hierarchy so that the library and the project icons are also marked with a red cross. See Library Status Icons for a list and explanation of each analysis status icon. Notice that the Output window at the bottom displays error messages about the selected source file. For the next step, see Analyzing and debugging source files R8, Analyzing and Debugging Source Files To help find and correct errors and warnings in source files, use the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express error, warning and message tabs in the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Output window. These pages show the file name, line number, and type of each error or warning. After viewing the messages, you can use the built-in HDL Editor to investigate and fix the source files. To view and correct errors and warnings: After selecting counter in the Design Sources window, view the errors in the Output window. Read the error and warning messages. Correct any errors in the design source file. There are two ways to open an HDL editor window directly to an error in a design source file: To open a source file at the location of the first error, right-click in the Design Sources window and choose Edit File. To open a source file at the location of a specific error, double-click the text for t,  hat error in the Output window. This method works only if there are multiple errors in the file. If you selected the internal source editor as the default source file editor (from the Synthesis > Options > General properties screen), FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses the built-in HDL Editor to edit the selected file. You can use the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Edit menu to navigate in the text file. You can also use the HDL Editor menu that is displayed when you right-click in the HDL Editor window. If you did not select the internal source editor, choosing Edit File starts the editor associated with the file type and opens the file.  The HDL Editor indicates that the errors in the counter are caused by a typing error in the if statement. Change the text from fi to if in the counter file. Save the file. The tutor.vhd icon contains a question mark, indicating that the file is out of date. Update the file. Ei:b8 , ther go to the Design Sources window and click  on the tool bar, or right-click in the HDL Editor window and choose Analyze File before closing the HDL Editor window. Based on the extent of your modifications, you can update a file, library, or the project. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express reanalyzes only the files that have been modified. If your changes are not evident to FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express (if the changes are in a dependent file, for example): Right-click in the Design Sources window and choose Force Update File (Library or Project). After you finish adding, analyzing, and debugging source files, you are ready to synthesize the design. See Synthesizing the Design.  L Synthesizing the Design FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses design configurations to specify a target device and design constraints to produce optimized FPGA netlists. Each design configuration with its set of design files sets up a unique design implementation. In this step, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesizes a unique, unoptimized design implementation from your source files. It creates a generic, logical description of the design, then maps the description to a specific vendor and device technology. After you have completed this step, you can set design constraints and controls before optimizing. These are the steps in synthesizing the design implementation: Adding the top-level design Specifying the target architecture Setting the target clock frequency Choosing synthesis options and creating the design implementation  a8 _ Adding the Top-Level Design To begin building a design implementation from analyzed source files, you add the top-level entity (VHDL), module (Verilog), or schematic design. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses this information to start building design hierarchy and interconnections. For this example, choose tutor as the top-level entity. You can add the top-level design in any of these ways: Click the drop-down list of top-level designs in the tool bar to see a list of all entities, modules, and netlist designs in the source files. Scroll through the list to find and choose the top-level design.  Double-click the source file to expand it and display an icon for the top-level design. Select the icon, right-click in the Design Sources window and choose Create Implementation. Click  on the tool bar. For the next step, see Specifying the Target Architecture.  s Specifying the Target Architecture After selecting a top-level design, specify a target architecture in the Create Implementation dialog box. To specify a target architecture: Enter an implementation name. If you do not enter a name, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically creates a unique implementation name. Specify the vendor and family for the design. (Optional) Specify the device type and speed grade.  For this tutorial, you can choose any vendor or family. The tutor design is small enough to fit any device family supported by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express.  For the next step, see Setting the Target Clock Frequency. a8  Specifying the Target Architecture After selecting a top-level design, specify a target architecture in the Create Implementation dialog box. To specify a target architecture: Enter an implementation name. If you do not enter a name, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically creates a unique implementation name. Specify the vendor and family for the design. (Optional) Specify the device type and speed grade.  For this tutorial, you can choose any vendor or family. The tutor design is small enough to fit any device family supported by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express.  For the next step, see Setting the Target Clock Frequency.  eSetting the Target Clock Frequency Set the target clock frequency for the design in the Create Implementation dialog box. This target frequency is used as the default value for all clocks in the design. After you synthesize the design implementation, you can change target clock frequencies in the design constraint tables. For this tutorial, simply enter a target clock frequency of 50 MHz. Note: Over-constraining a design can cause problems with some FPGA vendors place-and-route tools. For best results, specify only what is really required. For the next step, see Creating the Design Implementation  . S8 Choosing Synthesis Options and Creating the Design Implementation After you set the target architecture and clock frequency, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express is ready to synthesize architecture-specific logic and create a design implementation. To create the design implementation, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesizes logic for each source file. It determines the complete hierarchical structure and topology of the design, including multiple-level links and references between subdesigns. With this information, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express produces an intermediate, unoptimized design implementation. To create a design implementation: In the Create Implementation dialog box, verify the target architecture, clock frequency, and implementation name. (Optional) You can also provide other specifications in this dialog box, including: Choosing to optimize for speed or area with  high or low CPU effort. Choosing I/O pad insertion, if applicable. Choosing to skip constraint entry at this time (see Push-Button Design Flow). For this tutorial, however, do not select Skip constraint entry. Choosing to preserve hierarchy in the design. Click OK. When FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has finished creating the design implementation, an icon, its name, and target device appear in the Chips window. The implementation icon indicates its status. Check the Output window to investigate errors and warnings. Check the Output window to investigate errors and warnings.   For the next step, see Entering Design Constraints and Controls. T8 gh or low CPU effort. Choosing I/O pad insertion, if applicable. Choosing to skip constraint entry at this time (see Push-Button Design Flow). For this tutorial, however, do not select Skip constraint entry. Choosing to preserve hierarchy in the Click OK. When FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has finished creating the design implementation, an icon, its name, and target device appear in the Chips window. The implementation icon indicates its status. Check the Output window to investigate errors and warnings. Check the Output window to investigate errors and warnings.  For the next step, see Entering Design Constraints and Controls.  Choosing Synthesis Options and Creating the Design Implementation After you set the target architecture and clock frequency, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express is ready to synthesize architecture-specific logic and create a design implementation. To create the design implementation, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesizes logic for each source file. It determines the complete hierarchical structure and topology of the design, including multiple-level links and references between subdesigns. With this information, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express produces a intermediate, unoptimized design implementation. To create a design implementation: In the Create Implementation dialog box, verify the target architecture, clock frequency, and implementation name. (Optional) You can also provide other specifications in this dialog box, including: Choosing to optimize for speed or area with hi=U8 Entering Design Constraints and Controls Before you start to optimize a design to a target device, you can set performance constraints, attributes, and optimization controls. Design constraints guide FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express with specific optimization requirements. Although this step is optional, it is highly recommended. Entering your requirements in the constraint tables can improve the results of place and route tools. For example, entering constraints for an output port with restrictive speed requirements makes it easier for the place-and-route tool to fulfill those requirements. In another example, if a design is very large and has many hierarchical levels, entering hierarchy constraints helps the place and route tool. If default constraints are not sufficient for your requirements, you might have to create and optimize implementations many times to enter constraints. Note though that overconstraining a design can cause problems with som e FPGA vendors place and route tools. For best results, specify only what is really required. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express separates constraint entries into logically related groups (for example, clocks, ports, and paths). FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express extracts design-specific information such as clock names, port names, and design hierarchy from the design and displays it in FPGA vendor-specific tables. You enter performance constraints, attributes, and optimization options directly into the tables. Each set of constraint tables and dialog boxes is specific to a particular target FPGA architecture. Controls for some target technologies are available through a vendor-specific dialog box that is displayed as another tab with the constraint tables. To enter design constraints, attributes, and options: Right-click the design implementation and choose Edit Constraints to open the design constraint and optimizatioV8 n-control tables. Constraints and controls are logically separated into separate Clocks, Paths, Ports, and Modules tables. Note that in these tables you can specify all of your physical pad locations. Click the tabs to toggle between tables.  Open and explore the tables for the tutor implementation. The contents of the tables depend on the architecture that you chose. Notice that clock and pad tabs are preloaded with the clock frequency (and corresponding period) that you entered for the base clock frequency. After entering constraint, attribute, and option information, close the implementation's constraint window. This will save any changes. For the next step, see Optimizing a Design Implementation and Generating Output.  control tables. Constraints and controls are logically separated into separate Clocks, Paths, Ports, and Modules tables. Click the tabs to toggle between tables. Use the online help if you need instructions and information about specific constraints, attributes, and optimization options.  Open and explore the tables for the tutor implementation. The contents of the tables depend on the architecture that you chose. Notice that clock and pad tabs are preloaded with the clock frequency (and corresponding period) that you entered for the base clock frequency. After entering constraint, attribute, and option information, close the implementation's constraint window. This will save any changes. For the next step, see Optimizing a Design Implementation. V8 e FPGA vendors place and route tools. For best results, specify only what is really required. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express separates constraint entries into logically related groups (for example, clocks, ports, and paths). FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express extracts design-specific information such as clock names, port names, and design hierarchy from the design and displays it in FPGA vendor-specific tables. You enter performance constraints, attributes, and optimization options directly into the tables. Each set of constraint tables and dialog boxes is specific to a particular target FPGA architecture. Controls for some target technologies are available through a vendor-specific dialog box that is displayed as another tab with the constraint tables. To enter design constraints, attributes, and options: Right-click the design implementation and choose Edit Constraints to open the design constraint and optimization- Entering Design Constraints and Controls Before you start to optimize a design to a target device, you can set performance constraints, attributes, and optimization controls. Design constraints guide FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express with specific optimization requirements. Although this step is optional, it is highly recommended. Entering your requirements in the constraint tables can improve the results of place and route tools. For example, entering constraints for an output port with restrictive speed requirements makes it easier for the place-and-route tool to fulfill those requirements. In another example, if a design is very large and has many hierarchical levels, entering hierarchy constraints helps the place and route tool. If default constraints are not sufficient for your requirements, you might have to create and optimize implementations many times to enter constraints. Note though that overconstraining a design can cause problems with som8 Optimizing a Design Implementation After you finish entering constraint, attribute, and option definitions, you are ready to optimize the design and generate FPGA netlists. In this step, you optimize a design implementation for performance and area, guided by the implementation constraints and controls you entered in the constraint tables. To optimize a design implementation: Click the design implementation in the Chips window to select it. Its name is displayed in the top-level design field of the tool bar. Right-click the design implementation and choose Optimize Chip, or click  in the tool bar.  A new optimized implementation icon appears beneath the original implementation. When you optimize a design implementation, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express analyzes the actual timing and area of your design to see whether they meet your requirements. After optimization, the design implementation tables display the constraints you have specified with th ee actual results of your design so you can compare them. For the next step, see Analyzing Timing. =80 s. Note that all pins on the timing path will be displayed; hence, two rows of the path table correspond to a single net (src & load).  Check the Ports constraint table for information about input and output delays. The following figure shows the Ports constraint table where results include the slack for input arrival time and output delay for each port.  Check the Modules constraint table for information about the device resources used. Double-click the items in the Area column for details about cell count. The following figure shows the Modules constraint table after optimization.  For the next step, see Viewing Schematics. 0 Analyzing Timing You can determine circuit performance by checking the results of optimization and analyzing timing information. The post-synthesis timing data is displayed in the same formats as the tables you used to enter constraints. To view the results of optimization: Open an optimized implementation by clicking the right mouse button and selecting View Results. Check the Clocks constraint table to see the maximum clock frequencies FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express calculated for each of the clocks in the design. Clock frequency violations appear in red. The figure below shows the Clocks constraint table after optimization.  Check the Paths constraint table for more detail on timing violations. Select a path group to see a list of paths in that group. Select a path from the list to see the details of path composition, cumulative delays, and fanout. The following figure shows the Paths constraint table after optimization. See also Timing Analysi@8T s. Note that all pins on the timing path will be displayed; hence, two rows of the path table correspond to a single net (src & load).  Check the Ports constraint table for information about input and output delays. The following figure shows the Ports constraint table where results include the slack for input arrival time and output delay for each port.  Check the Modules constraint table for information about the device resources used. Double-click the items in the Area column for details about cell count. The following figure shows the Modules constraint table after optimization.  For the next step, see Viewing Schematics. T Analyzing Timing You can determine circuit performance by checking the results of optimization and analyzing timing information. The post-synthesis timing data is displayed in the same formats as the tables you used to enter constraints. To view the results of optimization: Open an optimized implementation by clicking the right mouse button and selecting View Results. Check the Clocks constraint table to see the maximum clock frequencies FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express calculated for each of the clocks in the design. Clock frequency violations appear in red. The figure below shows the Clocks constraint table after optimization.  Check the Paths constraint table for more detail on timing violations. Select a path group to see a list of paths in that group. Select a path from the list to see the details of path composition, cumulative delays, and fanout. The following figure shows the Paths constraint table after optimization. See also Timing Analysi8x oth part of the same net. In the schematic window the critical path is highlighted in red, allowing you to see the path graphically. Select a path and pause the mouse pointer over the cells of the path in turn. A popup window displays the cell name, cell type, pin numbers, delay, fanout and slack values. Select a pin from the pin list. The cell that the pin is attached to is highlighted in yellow. Move along the path by clicking the Previous Pin and Next Pin buttons on the tool bar, or by clicking the pins in the path in turn in the TimeTracker. With a cell selected and highlighted in yellow, click the Fan-in and Fan-out buttons on the toolbar to display the fan-in and fan-out cones of logic. For the next step, see Generating Netlists and Reports. See also Summary.  x !nd then release the mouse button and the Shift key (in that order). Note that the schematic is flat, because you specified that no hierarchy was to be preserved when you created the implementation. To view timing results graphically using the TimeTracker: Select the Paths tab (the Paths constraint table) in the TimeTracker window. Select the RCCLK RCCLK row in the path groups window (the upper left pane). The paths constrained by this path group are now displayed in the paths area (bottom left pane). Note that for any paths that fail timing, the timing values are displayed in red in the TimeTracker window, and in the schematic the registers are highlighted. Select the first path from this section. The right-hand side of the TimeTracker window displays the pins contained in this path. The instance pathname, cell type, delay and fanout are shown for each pin. Note that the pins are in pairseach end of a net in the critical path has two pins, with identical fanout, as they are b8!x " e-clicking anywhere in the schematic. Navigate around the hierarchy using the Chips window: Double-click on a level of hierarchy to expand it. Select one of the blocks to view that level. Notice that all cells are generic, not mapped to a particular technology at this stage, and that all hierarchy is preserved because operators have not been implemented at this stage, and they appear as primitive cells. When you are comfortable with the navigation features, close the RTL view. To view a gate-level (or mapped / optimized) design: In the Chips window, right-click on the optimized implementation called "tutor-Optimized". From the popup menu, choose View Schematic. The windows auto-arrange, displaying the Project window on the left, and the TimeTracker and schematic windows on the right. Navigate around the schematic by clicking the Zoom in, Zoom out, and Zoom full-fit buttons on the toolbar. To view an area, hold the shift key and left-drag the mouse pointer over the area of interest, a"x !Viewing Schematics You can view and analyze your design graphically, using the integrated schematic viewer and Time Tracker feature. You can view an RTL view of the design:  or a gate level (mapped) view of the design:  To view an RTL or generic design: In the Chips window, right-click on the un-optimized implementation called "tutor". From the popup menu, choose View Schematic. The windows auto-arrange to maximize the viewable area. Maximize the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express window to allow the schematic to be viewed using the maximum screen area. Navigate around the schematic by clicking the Zoom in, Zoom out, and Zoom full-fit buttons on the toolbar. To view an area, hold the Shift key and left-drag the mouse pointer over the area of interest, and then release the mouse button and the Shift key (in that order). View the contents of the "my_counter(counter)" block by double-clicking on the block. Return to the next level up by right-doubl58# $Viewing Schematics You can view and analyze your design graphically using Vista, the integrated schematic viewer and Time Tracker feature. You can view a RTL view of the design: n or a gate level (mapped) view of the design:  To view an RTL or generic design: In the Chips window, right-click on the un-optimized implementation called "tutor". From the popup menu, choose View Schematic. The windows auto-arrange to maximize the viewable area. Maximize the main program window in the screen area. Navigate around the schematic by clicking the Zoom in, Zoom out, and Zoom full-fit buttons on the toolbar. To view an area, hold the Shift key and left-drag the mouse pointer over the area of interest, and then release the mouse button and the Shift key (in that order). View the contents of the "my_counter(counter)" block by double-clicking on the block. Return to the next level up by right-double-clicking anywhere in the schematic. Navigate around the hierarchy using the Chips window: Do$ #%uble-click on a level of hierarchy to expand it. Select one of the blocks to view that level. Notice that all cells are generic, not mapped to a particular technology at this stage, and that all hierarchy is preserved because operators have not been implemented at this stage, and they appear as primitive cells. When you are comfortable with the navigation features, close the RTL view. To view a gate-level (or mapped / optimized) design: In the Chips window, right-click on the optimized implementation called "tutor-Optimized". From the popup menu, choose View Schematic. The windows auto-arrange, displaying the Project window on the left, and the TimeTracker and schematic windows on the right. Navigate around the schematic by clicking the Zoom in, Zoom out, and Zoom full-fit buttons on the toolbar. To view an area, hold the shift key and left-drag the mouse pointer over the area of interest, and then release the mouse button and the Shift key (in that order). Note that the schematic i58% $&s flat, because you specified that no hierarchy was to be preserved when you created the implementation. To view timing results graphically using the TimeTracker: Select the Paths tab (the Paths constraint table) in the TimeTracker window. Select the RCCLK RCCLK row in the path groups window (the upper left pane). The paths constrained by this path group are now displayed in the paths area (bottom left pane). Note that for any paths that fail timing, the timing values are displayed in red in the TimeTracker window, and in the schematic the registers are highlighted. Select the first path from this section. The right-hand side of the TimeTracker window displays the pins contained in this path. The instance pathname, cell type, delay and fanout are shown for each pin. Note that the pins are in pairseach end of a net in the critical path has two pins, with identical fanout, as they are both part of the same net. In the schematic window the critical path is highlighted in red, all& %owing you to see the path graphically. Select a path and pause the mouse pointer over the cells of the path in turn. A popup window displays the cell name, cell type, pin numbers, delay, fanout and slack values. Select a pin from the pin list. The cell that the pin is attached to is highlighted in yellow. Move along the path by clicking the Previous Pin and Next Pin buttons on the tool bar, or by clicking the pins in the path in turn in the TimeTracker. With a cell selected and highlighted in yellow, click the Fan-in and Fan-out buttons on the toolbar to display the fan-in and fan-out cones of logic. For the next step, see Generating Output. See also Summary. A8' $Generating Netlists and Reports Generating an FPGA netlist and project report completes the synthesis design flow. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express generates XNF and EDIF netlists that can be directly processed by place and route systems from technology vendors VHDL and Verilog netlists for functional simulation. A report file to review and document the project. These are the steps in generating output for your optimized implementation: Generating netlist files Generating a report See also Summary. ( )r IIFPGA Compiler II Altera EditionFPGA Express will not overwrite VHDL or Verilog files that the program did not generate. In this case, a file extension will be added to prevent a filename collision. C8) (Generating Netlist Files Generating an FPGA netlist and project report completes the synthesis design flow. To generate netlist files: Select the optimized design implementation and click  on the tool bar, or right-click the implementation and choose Export Netlist. The Export Netlist dialog box appears.  Choose an export directory for the netlist files. To change directories, type the new directory name, or click the Browse button. A standard Windows file browser appears. Select whether or not to export timing constraints with the netlist, using the Export Timing Specifications checkbox. Select an Output Format for your netlist: Select NONE to export a netlist for place-and-route. Select Verilog or VHDL to export a netlist for functional. Click OK. Caution Do not overwrite your VHDL/Verilog/EDIF/XNF source files. Always export netlists into a separate directory to make sure they are manageable. You may have many files exported from a single design. Note that FPGA Compile*[Generating a Report You can generate an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express report on a project, library, file, or chip. A project report documents the design through the synthesis and optimization design flow and includes information such as design source data, constraints, and optimization options. To generate a report: Select the project, library, design, or chip in the project window and click  on the tool bar, or right-click the project, library, design, or chip and choose Report. In the dialog box that appears, select a name and location for the report.  Click Save. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates a text file containing summary information for the whole project, the library, the design, or the chip. Open the file in a text editor or word processing application.  ?a8++,commands are documented in online man-page style help pages.  See: FST Man Pages for more information about the man help pages Introduction to FPGA Scripting Tool (FST) for more information about the scripting tool ,++Running the FPGA Scripting Tool FPGA Scripting Tool (FST) implements a TCL-based command-line interface to all the synthesis and optimization features of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. FST is designed for those users who Are more accustomed to command-line or keyboard-based interfaces than with graphical interfaces. Understand the capabilities of the tool and wish to specify operations as quickly as possible, thus, a specification that might require multiple mouse clicks and keyboard entries can be entered as a single command.  You can run FST from the command line of the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express shell, or by executing batch files composed of FST commands. To run FST in a shell window: Start the shell with the Start > Programs > Synopsys > FPGA Compiler II or FPGA Express shell command in Windows, or by typing fc2_shell or fe_shell in a DOS or UNIX shell. In the FST shell, execute FST commands. All FST a8-ASummary You have completed the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design flow tutorial. The design flow is comprised of these steps: Creating design source files Setting up an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project, then adding, analyzing, and debugging source files Creating a design implementation, specifying the top-level design and target device, and synthesizing logic from the design descriptions Entering performance constraints and controls to guide the optimization process Optimizing the logic Analyzing timing Viewing a schematic of the design Generating netlists and report files You can also run steps 2 through 7 from the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express shell using FST commands. Now you are ready to apply the power of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express to your own designs../ HDL. Capture the schematics for the rest of the design. . (Optional) Verify the design functionally. For HDL code, use an HDL simulator. For schematics, use a gate-level simulator. In FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, set up the design and analyze the source files. In FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, select the target device and optionally enter design constraints. In FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, synthesize and optimize the HDL source code and/or schematic capture netlists to produce an optimized EDIF or XNF netlist for place-and-route. (Optional) In FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, analyze timing information to verify acceptable circuit performance. (Optional) Generate a Verilog or VHDL netlist for functional simulation. Place and route the design with the FPGA vendor's development system. (Optional) Simulate the design with back-annotated tiλ8/.Design Flow Overview The FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design methodology uses HDL source code or schematic capture to describe an FPGA design. The HDL source code is synthesized, combined with netlists from schematic entry, then optimized into a netlist that is ready for FPGA place and route tools. This is the process for designing an FPGA with FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express: Create the design. For an HDL-based or mixed (HDL and schematic) design methodology, write the HDL source code for the design. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express process the HDL code to produce an optimized netlist that is ready for FPGA place and route tools * For a schematic-based methodology, capture the design schematics and export VHDL, Verilog, or EDIF. * For a mixed (HDL and schematic) design methodology, write the HDL source code for the parts of the design you have decided should be described in01FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Functions FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates optimized FPGA netlists from VHDL code, Verilog HDL code, and existing, unoptimized netlists in the following design flow: Analyzes VHDL and Verilog HDL source files for correct syntax using the Synopsys industry-standard HDL language policy. Synthesizes logic from VHDL, Verilog HDL, and FPGA netlist source files, targeting a specific FPGA architecture and device. Optimizes logic for speed and area as directed by your design constraints, generating an FPGA netlist file ready for place-and-route by FPGA vendors' tools. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express accepts any combination and mix of VHDL, Verilog HDL, and FPGA netlist files as input sources for a single design. For example, you can use functions or subdesigns that are created in schematic capture and Verilog HDL within a VHDL top-level design, and viceλ8102 versa. After you add the design sources, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express analyzes HDL files. If you have errors in the source files, the error viewer and text editor help you to find and correct problems. Next, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express synthesizes the logic for your design, using architecture-specific algorithms to target devices from the leading FPGA manufacturers. During this part of the design flow, each design module is elaborated and the design hierarchy is created and linked to form a unique design implementation. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes the design as directed by your design constraints. With FPGA Compiler II / FPGA Express' graphical user interface (GUI), you can enter constraints for your design in editable tables. The constraints contain performance requirements and optimization options for the architecture-specific optimization engines. When it ha21s completed optimization, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express generates a netlist ready for place-and-route by the FPGA vendors' tools. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express also creates Verilog and VHDL netlists for functional simulation, and reports that document its results. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express extracts and displays accurate post-synthesis delay information for timing analysis and debugging. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays timing information beside your design constraints so you can make quick, informed decisions. X83)4FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Design Flows There are a number of ways to use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express to create successful FPGA designs. The way you use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express depends on the size, complexity, and performance requirements of your designs and your experience with HDL methodology. Each of the following FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design flows provides a solution to a different design challenge. These design flows are only a few examples of the ways to use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. Review these design flow summaries to see which one will work best in your design environment. Push-Button Design Flow  The Push-Button design flow is the simplest way to use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. It reduces the amount of data entry to a minimum, ena4)35bling you to create FPGA designs using fewer steps. This method produces good results, but does not use many of the enhanced features of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express that consistently produce the highest performance results. Performance (Constraint-Driven) Design Flow  The Performance design flow uses all the high-performance capabilities of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. You specify detailed design constraints and optimization controls to guide the synthesis and optimization tools. Using this design flow is the best way to ensure that your designs are consistently optimized for speed and area. Hierarchical  The FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project manager.allows you to design several chips in the same project. You can add the source files for all the chips on a board. After you identify the top-level design file of each chip, the program automatically links the rest of85)4 the design files in the chip hierarchy. Script-Based  You can access all of the functionality of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express through the FPGA Scripting Tool (FST), a TCL-based command-line language. You can use FST to synthesize many chips, in batch mode or interactively, from the shell command line. ASIC-Compatible  With FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, you can easily migrate between ASIC and FPGA design flows. You can generate .dc shell scripts for any design and can translate them to fc2_shellfc2_altera_shell format.. If a design doesn't meet the specifications or if its requirements change, you repeat part or all of the design flow. These design iterations are a common part of an FPGA design flow. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has built-in features that enable you to iterate designs with minimal effort. For more information, see Design Flow Iteration. 6@7Performance (Constraint-Driven) Design Flow When to use Performance design flow The Performance (constraint-driven) design flow emphasizes capturing a complete set of performance constraints and optimization controls. By thoroughly specifying the unique constraints and controls for each design, you increase the predictability and repeatability of the results. The Performance design flow is composed of five main steps. Set up the project. Select the target architecture and elaborate the design. Optimize logic. Analyze timing information. Generate netlists and reports. Setting Up the Project To begin this flow, set up the design by adding and analyzing source files. Use the integrated HDL text editor to modify design source files if there are any errors. Re-analyze any modified design source files with Update. Selecting the Target Architecture and Elaborating the Design Select the target architecture, package, and speed grade. Enable optimization for speed or area at high or lo87@68w effort. Then elaborate the design implementation. Entering Constraints and Controls Open the elaborated implementation to display the design constraint and optimization control tables. In these tables, completely capture the system level and internal performance constraints for your design. The tables are customized for each FPGA vendor and device family, so they include only constraints that apply to a particular target device. Capture the period, rise time, and fall time for each system clock. From this information, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express calculates the constraints on the path groups automatically. You can override this information as desired. Enter the input and output delays at each port and other device-specific port attributes such as built-in I/O registers and pull-up and pull-down resistors. By specifying design-specific constraints, you produce the desired results in the first pass and eliminate multiple design iterations. Beca8@79use the target performance is entered in advance, little or no time is spent in iteration cycles. The design implementation constraint tables let you control the optimization of specific modules, entities, and sub-designs. The optimization controls for area/speed, CPU effort, hierarchy, primitives, and arithmetic operator sharing have a strong effect on the final results. You can choose to preserve hierarchical boundaries during optimization, or you can flatten the design to optimize logic across the hierarchy. You might choose to preserve special preoptimized macros and components, and prevent optimization completely. Optimizing Logic After the constraints and controls are fully captured, close the design Constraint window and optimize the design. Analyzing Timing Information Open the optimized design implementation to view the post-synthesis timing information. On the Ports constraint table, check the slack for input arrival time and output delay time. On the Paths constraint table,89@8 compare the estimated circuit delays with the design requirements. You can view detailed information for all the paths by double-clicking them in this table. Check the paths with timing violations, which are highlighted in red. Generating Netlists and Reports Finally, export an EDIF or XNF netlist for place and route, optionally generate a Verilog or VHDL netlist as well for functional simulation, and generate a design report for documentation and review. :e{When to Use Performance Design Flow Use the Performance design flow to address challenging design situations where high device performance, predictability, and repeatability of results are most important. You are required to spend more time in the initial setup of the synthesis and optimization tools for this flow, but you save time and effort in the overall design creation. a`8;m<ompiler IIFPGA Compiler II Altera EditionFPGA Express uses the clock frequency to guide the optimization of all clock signals and the corresponding period for input and output delays. Before you optimize the design, make sure the Skip Constraint Entry check box is checked in the Create Implementation dialog box. This option enables you to complete design elaboration and optimization in one step. Click the OK button to elaborate and optimize the design. Optimizing Logic and Generating Netlists and Reports When the elaboration and optimization steps are complete, export an EDIF or XNF netlist for place-and-route, optionally generate a Verilog or VHDL netlist as well for functional simulation, and generate a design report for documentation and review. <m;Push-Button Design Flow The Push-Button design flow requires very little setup and interaction to produce netlists ready for place and route. Only three steps are required to complete analysis optimization, and netlist generation. The Push-Button design flow is composed of three main steps. Set up the project. Select the target architecture and elaborate the design. Optimize logic and generate netlists and reports. For more information, read the following sections and see When to use Push-Button design flow Setting Up the Project To begin this flow, set up the design by adding and analyzing source files. Use the integrated HDL text editor to modify design source files if there are any errors. Reanalyze any modified design source files with Update. Selecting the Target Architecture and Elaborating the Design Select the target architecture, package, and speed grade. Enable optimization for speed or area and at high or low effort. Then enter the desired clock frequency. FPGA Cc8=When to Use Push-Button Design Flow Use the Push-Button design flow when you want to synthesize and optimize an FPGA design quickly. This design flow requires the least amount of effort and time to set up, run, and proceed to the FPGA vendors' place and route tools. It is a good way to try FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express or to test a design before final specifications are complete. Although this flow might produce acceptable device performance, the results are less predictable and repeatable than those obtained from the more complete design flows. Use the Performance design flow to use all the capabilities of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. >?Hierarchical Design Flow The first three steps in the Hierarchical design flow are the same as for the Performance design flow. Set up the project. Select the target architecture and elaborate the design. Enter constraints and controls. Optimize logic, generate reports, and export the design constraint file. Analyze timing information. Create a new implementation. Import the design constraint file. Repeat the optimization process and generate netlists and reports. For more information, read the following sections and see When to use Hierarchical design flow. Starting the Hierarchical (Multiple-Target) Design Flow To target multiple devices, first complete the Performance design flow for one target device. In addition to the steps in the normal Performance flow, export the constraint file for the design. This constraint file contains the complete constraint and control information that you entered in the constraint tables. Avoid using device-specific macros or primitives if you 38?>@want to compare target devices. If the source files contain vendor or family-specific components, the design cannot be ported to other vendors or families. At the end of this stage, you will export an EDIF or XNF netlist for place-and-route with the FPGA vendors software to extract exact timing information for the design. Creating Another Implementation Next, create a new design implementation from the source files, choosing another target device family or vendor. Select the new vendor, family, device, and speed grade for the new implementation, but keep the rest of the design information the same. Importing the Constraint File Because the design constraints and optimization controls for the initial implementation are already captured, you can apply them to the new design implementations with the Import Constraints feature. This feature enables you to reuse the constraint information. If some of the constraints no longer apply to the new target device, a tool similar to the Windows@?5 Wizard allows you to associate existing constraints to the new implementation. Repeating the Optimization Process After the constraint file is applied to the new implementation, optimize and export the new netlist. Repeat this process for each target architecture and compare the timing and area results. }c8AWhen to Use Hierarchical Design Flow Use the Hierarchical design flow when you want to find and compare the performance of a design for multiple device families and vendors. You can manage and analyze different implementations within the same FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project. The source files, design constraints, and optimization controls are the same; only the target device is different. BCEiles that have been changed or modified. Then, you can continue with the rest of your chosen design flow. Changing the Target Device Family, Architecture, or Vendor If you need to create a new implementation from new source files or for a new target device, you can apply existing constraints and controls. Use the Hierarchical (multiple device) design flow. You can use more than one implementation or set of source files in one project. You can also create separate projects for each implementation. Either way, you can transfer constraint information between similar designs. [8CBDesign Flow Iteration These are the steps in design flow iteration. Set up the project Select the target architecture and elaborate the design Enter constraints and controls Optimize logic and generate reports Analyze timing information Repeat all or part of the design flow There are several ways to iterate a design in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. These are a few helpful techniques to use for design iterations. Changing or Modifying Source Files Use the integrated HDL text editor to modify design source files if there are any errors. If you change or modify the source files of a design after they have been analyzed, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically recognizes the modified state of the files. The icon for modified source files indicates that they must be reanalyzed. To update the source files, use the Update command. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express reanalyzes fDHow to Use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express in Timing Analysis Timing analysis gives you detailed information about the timing behavior of your design. You can analyze timing results as part of your FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express design flow rather than running place-and-route tools and performing timing analysis after place and route For any path, the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express TimeTracker provides a detailed listing of the path composition to aid you in debugging critical paths. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express timing analysis shortens the design cycle by eliminating the need to run vendor tools to get timing information. See these topics for more information: Using the FPGA Compiler II Altera Edition FPGA Express TimeTracker Timing Analysis Entering Timing Constraints O8EFHow to Specify Timing Constraints Although timing constraints can be specified in many ways in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, Synopsys strongly recommends the following procedure. Specify the default clock waveform. The clock default is the first row in the Clocks constraint table. The default should be sufficient in most of the cases when the design has only one clock and there are no special input delay and output delay requirements. Specify the clock waveforms for all the clocks. The waveform you define using the Define option in the Clock pull-down list in the Clocks constraint table should be sufficient for most synchronous designs without special I/O port delay requirements and without multicycle paths. In the Paths constraint table, change the default path delays that FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically calculates from the clock waveform. It is important that the delays be specified accuFE rately so that they do not overconstrain or underconstrain the optimization. In the Ports constraint table, change the default input delay and output delay of I/O ports when they have special requirements. Any delay specified at a port overrides the path delay from or to the port. With FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express you can enter point-to-point constraints (e.g., multicycle timing paths) by creating subpaths. Just right-click on the path in the Paths table and select New Subpaths. 8GHYou can expand and contract the path hierarchy of the Paths constraint table by double-clicking on the path icon. To modify or delete subpaths, select the subpath and click the right mouse button for the subpath menu. HGTiming Subpaths To create subpaths for a path, select a path in the Paths constraint table and click the right mouse button for the New Subpath menu.  The selections are New Subpath, Edit Subpath, and Delete Subpath. Select New Subpath or Edit Subpath (if available). The Create/Edit Timing Sub Path dialog box opens, displaying the primary path and the components in that path. Enter a name for the subpath. Select startpoints and endpoints for each subpath group by double-clicking the object icons. The names of subpath groups must be unique. Specify the delay for the subpath. You can specify a different constraint for each subpath. You can use the Select All buttons to make multiple startpoint and endpoint selections. You can also use the Clear All buttons to clear all startpoint and endpoint selections. You can enter common expressions such as DI* to make multiple selections. When you click OK, the Paths constraint table is updated to reflect the new subpath groups.   18I)Subpath context menu / New Subpath command Opens the Create / Edit Timing Sub Path dialog box for the selected path. To specify constraints for arbitrary timing paths, create a new subpath. See Paths Constraint Entry and Timing Subpaths for more information about entering timing constraints. J%Subpath context menu / Edit Subpath command Opens the Create / Edit Timing Sub Path dialog box for the selected subpath. See Timing Subpaths for more information. ۺ8K0LSubpath context menu / Delete Subpath command Deletes the selected subpath. >L EWelcome to FPGA Compiler"\)tion I/O Pad Mapping Clock and Global Signal Mapping This online information is not a comprehensive style guide. Check the online HDL and VHDL references for more hints and tips on taking advantage of the flexibility of VHDL and Verilog HDL to produce successful designs. Each FPGA vendor also publishes literature about wric[8MeHDL Coding for FPGA Synthesis HDL coding style plays a large part in determining the design's quality of results. Two design descriptions might be functionally identical, but differences in their HDL coding style can contribute to area and speed variations in the resulting circuit implementations. Thus, it is important to understand how coding style affects synthesis and optimization results. See these topics for ways to prepare synthesis-friendly source files for FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express: Simplifying an HDL Design with FPGA Compiler II Altera Edition FPGA Express Built-in Module Generation I/O Pad Mapping Clock and Global Signal Mapping This online information is not a comprehensive style guide. Check the online Verilog HDL and VHDL reference manuals for more hints and tips on taking advantage of the flexibility of HDL to produce successful designs. Each FPGA vendor also publishes literature about writing synthesizable HDL source code.N|HDL Coding for FPGA Synthesis HDL coding style plays a large part in determining the design's quality of results. Two design descriptions might be functionally identical, but differences in their HDL coding style can contribute to area and speed variations in the resulting circuit implementations. Thus, it is important to understand how coding style affects synthesis and optimization results. See these topics for ways to prepare synthesis-friendly source files for FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express: Simplifying an HDL Design with FPGA Compiler II Altera Edition FPGA Express Built-in Module Generation I/O Pad Mapping Clock and Global Signal Mapping This online information is not a comprehensive style guide. Check the online Verilog HDL and VHDL reference manuals for more hints and tips on taking advantage of the flexibility of HDL to produce successful designs. Each FPGA vendor also publishes literature about writing synthesizable HDL source code.8OProject State The project state is defined by of the status of the source files (see Source file status icons), and the status of the implementation (see Implementation status icons). FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express uses visual symbols to indicate the state of the source files, the implementations, the libraries, and the project. See Library status icons and Project status icons. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not prevent you from putting the project into an inconsistent state. For example, you can add a file named test.v, analyze it, implement it, elaborate it, make modifications to the test.v source file, add it back in, and reanalyze it. At this point, the elaborated and optimized implementation are out of date with respect to the source; however, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not prevent you from exporting the netlist from the existing optimized implPI/O Pad Mapping Most FPGA architectures use complex I/O pad structures to increase throughput at the boundaries of the chip. As in the case of internal functional modules, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically maps logic into these architecture-specific I/O structures. You can also instantiate I/O macros directly into HDL source code from a vendor library, but this practice decreases the portability and flexibility of the code. It also lengthens the design creation and iteration cycles. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically maps I/O signals to the chosen FPGA architecture during synthesis. You can add or change the characteristics of I/O pad structures after elaboration by editing the design implementation's Ports constraint table. You can use the pull-down lists to select a pull-up or pull-down resistor, I/O register, or other attributes to characterize individual I/O signals. 8Q'Clock and Global Signal Mapping Each FPGA architecture has dedicated resources used for system clocks and other global signals such as resets and enables. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically tracks these resources and allocates them to the most appropriate I/O signals. For example, if the device has four available global clock buffers and the design describes five clock signals, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express allocates the buffers to the four most heavily loaded signals. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express also lets you manually assign specific global buffers to I/O signals for Actel and Xilinx technologies. Use the Ports constraint table to make the assignments. Making I/O attribute assignments in an FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express project instead of instantiating them in HDL source code increases the portability of the code and simplifies tR2General Coding Styles for Synthesis HDL coding is the foundation for synthesis. A good coding style can generate smaller and faster designs. See these topics to help you write efficient code: Using meaningful and efficient names Using one naming style to distinguish separate words Conventions for name suffixes Guidelines for coding macros, modules, functions, and expressions Differences between variables and signals Register inference Three-state inference If statements Case statements Nonblocking statements General HDL constructs %>8ST ci_interrupt TSUsing Meaningful and Efficient Names A good signal name conveys the meaning of the signal or the value of a variable; without this information, hardware descriptions are difficult to read. These are some guidelines for naming signals: Make the significance of the name apparent. For example, Too long: floating_pt_opcode_rs1 Too short: frs1 Recommended: fpop_rs1 Example, unnecessarily long names: for (loop_count=0; loop_count < 1024; loop_count = loop_count+1) RAM[loop_count] = 32'h0; Example, improved shorter names: for (i = 0; i < 1024; i = i +1) RAM[i] = 32'h0; Avoid confusing characters. Some characters look similar and are easily confused with each other.  For example: O (letter O) and 0 (zero) l (letter I) and 1 (one) Use a consistent capitalization style. Inconsistent capitalization is confusing and leads to mistakes.  For example: Packet_Addr and packet_addr Use the noun or noun_verb form for names. For example,  addr_decode data_grant p7>8U]Using One Naming Style to Distinguish Separate Words C, Pascal, and Modula are the three styles commonly used to distinguish separate words in a name. Choose one convention and apply it consistently. Synopsys Recommended Style Use lowercase for HDL keywords and uppercase for user-defined or vendor-defined identifiers. entity, module, signal, wire, reg PACKET_ADDR, DATA_IN, STD_LOGIC C Style Names are lowercase. Words are separated by an underscore character. packet_addr, data_in, first_grant_enable Pascal Style The first letter of the name and first letter of each word are capitalized; the remaining letters are lowercase. PacketAddr, DataIn, FirstGrantEnable Modula Style  The first letter of the name is lowercase. The first letter of subsequent words is capitalized; the remaining letters are lowercase. packetAddr, dataIn, firstGrantEnable VConventions for Name Suffixes Append an underscore character and a suffix to clarify the meaning of the name. These are common suffixes and their meaning: Suffix Represents *_clk clock signal *_next signal before being registered *_l active low signal *_z signal that is driven by a three-state output *_f register that uses the active falling edge *_xi primary chip input *_xo primary chip output *_xod primary chip open drain output *_xz primary chip three-state output *_xbio primary chip bidirectional I/O a28W'Guidelines for Coding To write efficient code, use the guidelines in these sections: Guidelines for Macros  Guidelines for Modules  Guidelines for Functions  Verilog Function Construct  VHDL Function Construct  Guidelines for Expressions  X>YGuidelines for Macros Use these guidelines for macros: Do not use `define attributes inside module definitions. Using `define inside module definitions is dangerous because the local macro and the global macro have the same reference name but different values. If the reference scope is restricted to a particular module, use a parameter instead. Do not use nested `define attributes. Reading a macro that is nested more than twice is difficult. To make your HDL source code readable, do not use a nested `define. In Verilog code, keep `define attributes in a separate file and use them only to declare constants. In Verilog code, define local references as generics or parameters in the module, not by passing a generic or parameter. For example, `define WIDTH 128 // Global definition in def_macro.v reg regfile[`WIDTH -1:0]; // Global reference in reg128.v module foo(a,b,c); parameter WIDTH=128; input [WIDTH-1:0] a, b; // Use parameters output [WIDTH-1:0] c; In VHDL, you can define a glc28Y>Xobal CONSTANT in the package so it can be referenced by the use clause. Similarly, GENERIC is defined in the entity declaration and is used for local reference. For example,  CONSTANT WIDTH : INTEGER := 128; -- Global definition Library my_lib my_lib.synthesis.def.all: -- Global reference ENTITY foo IS GENERIC(WIDTH:INTEGER:=128); PORT(a,b : IN std_logic_vector(WIDTH-1 downto 0); c: OUT std_logic_vector(WIDTH-1 downto 0)); ZQGuidelines for Modules Use these guidelines for modules: Ensure that top-level modules contain only interconnects. A design is a hierarchy tree that consists of one or more modules, any of which can instantiate other modules. The root module should not contain anything other than interconnections and module instantiations. Encapsulate any interface logic in a lower module so synthesis can compile faster. Do not use logic expressions when passing a value through ports. The port list can include expressions, but this complicates debugging. For example, if the port list includes expressions, uncovering the cause of a problem related to bit mismatches is difficult. ,:8[_\Guidelines for Functions Use these guidelines for functions: Do not use global references within a function. In procedural code, a function is evaluated when it is called. If it is referenced in a continuous assignment, the function is evaluated when any of its declared input values change. Including references to nonlocal names within a function is dangerous, because the function might not be reevaluated if the nonlocal value changes. This can cause a simulation mismatch between the register transfer level (RTL) description and the gate-level netlist. For example: function BYTE_COMPARE; input [15:0] VECTOR1, VECTOR2; input [7:0] LENGTH; begin if (BYTE_SEL) then // compare the upper byte else // compare the lower byte Be aware that task and function local storage is static. Formal parameters, outputs, and local variables retain their values after a function has returned. This storage is reused each time the function is called. This static storage can be useful for debugging\_[K, but it also means that functions and tasks cannot be called recursively. 58]pVerilog Function Construct This is an example of a function construct in Verilog: function CompareVectors; // VECTOR1, VECTOR2, LENGTH input [199:0] VECTOR1, VECTOR2; input [15:0] LENGTH; reg [15:0] i; reg NOTEQUAL; begin i=0; NOTEQUAL = 0; while ((iDataOut<=DataBus; when `0'=>DataOut<=(others=>`0); END CASE; end process; -- initial: PROCESS begin ... end process; always: PROCESS(clk, reset) begin ... end process; END;-- test :8kjGeneral HDL Constructs The following examples are general HDL constructs for Verilog and VHDL. Verilog General HDL Construct  module TEST (DATAOUT, DATAIN, SELECT, CS_L, WE_L, OE_L); output [63:0] DATAOUT; input [63:0] DATAIN; inout SELECT; input CE_L, WE_L, OE_L; // Internal wire/reg declarations wire [63:0] DATABUS; reg OUTPUTENABLE; // Function and task definitions function PARITY(DATA, SENSE) ... endfunction // Parity // Module instantiations M1 SubM1(); M2 SubM2(); // Continuous assignments assign DATAOUT = (OUTPUTENABLE ? DATABUS[63:0] : 64'h0); // always and initial blocks initial begin ... end always @(posedge clk or posedge reset) begin ... end // always endmodule // test VHDL General HDL Construct  library IEEE; use IEEE.std_logic_1164.all; ENTITY test IS PORT(DataIn, CS_L, WE_L, OE_L : IN std_logic; Select : INOUT std_logic; DataOut : OUT std_logic); ARCHITECTURE RTL of test IS -- Internal wire/reg declarations SIGNAL DataBus : std_logic_vector (63 downto 0); lzPartitioning for Synthesis Partitioning within an FPGA at the correct level of granularity can enhance the synthesis process. Two principal goals are behind any partitioning recommendations: Achieving the best synthesis results Reducing compile time Better synthesis results are significantly easier to obtain if you arrange logic correctly in modules and in the hierarchy. +Q8mnme destination path and have outputs that are multiplexed to that path, keep the adders in one process or always set a block. This approach allows FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express to consider resource sharing (that is, to use one adder in place of two) if the constraints allow sharing. To ensure that resource sharing is activated, choose the ON option for resource sharing in the Modules constraint table of the design implementation. nmAchieving the Best Synthesis Results These are recommendations to help you achieve better synthesis results: Keep functionally related combinational logic in the same module. Keeping related combinational logic together in the same module is critical because intermodule partitions can restrict logic optimization across hierarchical boundaries. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express cannot move logic across hierarchical boundaries if those boundaries are preserved during optimization. One way to ensure that logic is optimized across hierarchical boundaries is to choose the Eliminate option (the default) for modules in the Modules constraint table for the design implementation. The eliminate option allows optimization of larger, functionally related groups of logic. Merge resources in the same process block. Either merge resources that can be shared into the same process (VHDL) or always set a block (Verilog). For example, if two separate adders have the sam28o2Port and Pad Terminology Hand-instantiated pads Inout port  Input register delay Pad constraints Pad mapping Port pad type Preserving pads Resistor pad Three-state driver Three-state output port pPHand-Instantiated Pads Primitive pad cells that are instantiated by the designer in the netlist or HDL description are defined as hand-instantiated pad cells. For example, an instance of a Xilinx OBUF in a design is a hand-instantiated pad cell. Q38q[Inout Port An inout port is a port whose net is driven by a three-state driver and loads internal logic or other ports in the design. rgInput Register Delay The input register delay is the setup time for registers mapped to input pads or driven directly by input ports. Note: This definition is exactly opposite to what ASIC designers are accustomed. 38srPad Constraints When you specify pad constraints, you describe the type of pad cells that the pad-mapping optimization inserts at the ports of the top-level design. You can specify these pad characteristics: port pad type, slew rate, input register delay, and resistor pads. tPad Mapping Pad mapping is the optimization step that creates the I/O pads at each port in the top-level design. This optimization is controlled by the pad constraints and by the global pad controls you set when you create implementations. 38uPort Pad Type There are four basic port pad types. These types are either defined by the designer using the Ports constraint window or are inferred from the HDL or netlist description. Port pad type inferencing is determined by the port direction and analysis of the loads and drivers at each port. For ports with this pad type Pad mapping inserts this type of pad cells Input Input pad buffer or input pad register Output Output pad buffer or output pad register Three-state output Three-state pad buffer or registered three-state pad buffer Inout Input pad buffer or input pad register and output pad buffer or output pad register vPreserving Pads You can use the Do Not Insert I/O Pads check box in the Create Implementation dialog box to retain all I/O pads (the default) or remove them before executing pad mapping. 48wResistor Pad A resistor pad is a pull-up or pull-down cell that causes the logic value of a three-state net to be either logic 1 or logic 0 when the net's three-state drivers are all driving a logic z or high impedance. xThree-State Driver Pad mapping treats any of the following as a three-state driver: The output pin of a three-state cell inferred in the HDL description The output pin of a hand-instantiated three-state cell in the netlist or HDL description The pin of an unlinked cell that has no direction specified or has direction inout Ports with the direction inout when there are multiple inout ports tied to the same net 0T8yThree-State Output Port A three-state output port is a port whose net is driven by a three-state driver and does not load other logic or ports in the design. zDefault Port Type This field displays the default port pad type. The default value is found by analyzing the ports net. The number of loads, drivers, three-state drivers, input ports, output ports, and inout ports on the net determine the type. If the type field is empty, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express cannot infer the port pad type and requires that you specify the type. 28{Slew Rate To specify the slew rate for a port, select an option from the Slew Rate drop-down list. The options are specific to the implementations target device type. |Resistance To specify the resistance for a port, click an option from the Resistance drop-down list. The options are specific to the implementations target device type. %ٸ8} Timing Terminology Active edge Clock Default timing values Delay External delay Flip-flop Input delay Latch Multicycle path Output delay Path delay Point-to-point timing Sequential element Slack Timing group Timing path ~'Active Edge The active edge of a clock signal at a sequential element is the edge at which the output signal becomes stable. For flip-flops, the active edge is the clocking edge. For example, rising edge is the active edge for positive edge-triggered flip-flops. For level-sensitive latches, the active edge is the end of the enabled time. For example, falling edge is the active edge for positively enabled latches. Active edge is an important concept in understanding how default path delays are assigned to timing paths. f8;Clock Clocks are signals with a periodic behavior. In synchronous circuit designs, clocks are used to synchronize the propagation of data signals by controlling sequential elements. It is important that you accurately specify all clocks so that FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express can optimize a synchronous circuit efficiently. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically analyzes the circuit and lists all the signals that require clock definitions in the Clocks constraint table. A clock is defined by its waveform, with rising and falling edge times in the interval between 0 and its period. It is important to know that the interval always starts at time 0. In this way, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express knows the precise relationship between all the clocks in the design. A clock can also be specified by its frequency. In this case, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA JDefault Timing Values FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express follows several rules in assigning default timing values to clocks, timing paths, input delay, and output delay. The default clock waveform rises at 0 and falls at 10ns with period 20ns. Any clock with an unspecified waveform inherits the default clock waveform. The default path delay of a timing path is the time from an active clock edge of the clock for the starting group to the next active edge of the clock for the ending group.  If the starting group is the INPUT group, the default delay is the period of the clock for the ending group. If the ending group is the OUTPUT group, the default delay is the period of the clock for the starting group. The default path delay from the INPUT group to the OUTPUT group is the period of the default clock. The default input delay of an input or inout port is the path delay from the INPUT group to another group. The default output delay of an ouCT8JHtput or inout port is the path delay from a group to the OUTPUT group. aDelay Delay is the time it takes a signal to propagate from one point to another. All delays specified in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express are in nanoseconds and must be integers. V8lExternal Delay You can specify the timing behavior of a port using input delay or output delay. You can also specify timing behavior in terms of how the signal is generated externally; that is, by specifying the external delay from an external sequential element clocked by a known clock to the port. These two specifications are functionally equivalent. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not support external delay specifications. {Flip-Flop Flip-flops are edge-triggered devices controlled by periodic signals (clocks). Flip-flops synchronize the propagation of data signals. H8oInput Delay The input delay of an input or inout port is the maximum delay from that port to a timing group. Latch Latches are enabled devices usually controlled by periodic signals (clocks). Latches allow propagation of data signals during a specific time interval. Latches are also referred to as level-sensitive devices. [^81Multicycle Path A design may have timing paths that are longer than a single cycle. If a timing group is formed only out of these timing paths and either the startpoints or the endpoints of these timing paths are enabled by a common signal, you can make the paths multicycle. You cannot make these timing paths multicycle if they share the same clock as other single-cycle timing paths. To make a timing path multicycle, change the default path delay computed by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express to the new delay representing the multicycle behavior. For example, if a timing path is clocked at both ends by 20ns clocks and its default path delay computed from the clock waveforms is 10, changing the default delay from 10ns to 30ns will add one more cycle to this timing path. rOutput Delay The output delay of an output or inout port is the maximum delay from a timing group to that port. 8Path Delay Path delay for a timing path is the maximum delay allowed from any point in the starting timing group to any point in the ending timing group. Point-to-Point Timing In FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, a timing point is defined as either the input or output of a register a primary I/O of the design. All timing points belong to one or more timing groups. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express supports point-to-point constraints. To specify a point-to-point constraint, create a subpath in the timing group, selecting a startpoint and an endpoint for the subpath. See Timing Subpaths. ,48dSequential Elements Flip-flops and latches are collectively referred to as sequential elements. Slack Slack is the margin by which a delay requirement is met. Positive slack means that the requirement is met; negative slack means that the requirement is not met. b8Timing Group A timing group is a collection of sequential elements and ports in the top-level design that have common timing behavior. These are timing groups: All input and inout ports belong to the INPUT group. All output and inout ports belong to the OUTPUT group. All flip-flops clocked by the same edge of a common clock belong to a group. All latches enabled by the same value of a common clock belong to a group. All flip-flops or latches enabled by the same value of a common signal belong to a group.  A timing group is a basic concept in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express because all timing constraints are specified using timing groups as basic entities. Timing Path A timing path is the set of combinational paths from one timing group (called the starting group) to another timing group (called the ending group). These are some examples of timing paths. Example 1: FROM: registers clocked by rising CLK1 TO: registers clocked by falling CLK2 Example 2 FROM: all inputs TO: latches enabled by high "G" To specify constraints for timing paths, see Paths Constraint Entry. To specify constraints for arbitrary timing paths, see Timing Subpaths. Q8yAnalysis Terminology Analyze Analysis order Bus Bus naming style HDL library Source file status icons +Analyze When analyzing a source file, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express checks for syntax errors and verifies that it follows Synopsys HDL policy. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically analyzes HDL source files when they are added as part of a library. To reanalyze a design source file, select it in the Design Sources window and click the Update option in the Synthesis menu or the Update tool bar button. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express analyzes only those files that were changed since the last analysis. To reanalyze a file that was not changed but which is dependent upon another file that has been changed, select Force Update in the Synthesis menu. ,189&Analysis Order The source files are analyzed in the order in which they are imported in the project. Analysis order is important only when packages are defined in the source files (for VHDL only). If a package defined in file1 uses another package defined in file2, it is the users responsibility to make sure that file2 is analyzed before file1. When files are analyzed in the wrong order, analysis errors may result. When the analysis order is important, be sure to add source files into the project in the order in which they must be analyzed. DuBus Buses are groups of one or more signals. For example, a 32-bit address bus represents 32 individual address signals. The number of signals in a bus corresponds to the width. Buses are not separate objects; they are names for sets of individually named ports or nets. Buses are explicit in VHDL and Verilog input formats. You can create bused ports in VHDL or Verilog. [8N\Bus Naming Style The bus naming style defines the format of the names of ports or wires belonging to a bus. The form of a bus naming style is %s in which contains only one %d parameter. %s corresponds to the name of the bus. The %d parameter corresponds to the bit position of the port in the bus. These are valid format descriptors: %s%d %s[%d] These are invalid format descriptors: %s%f %d%s %s%d%d A bus naming style of %s[%d] for a port with the name name in bit position I has a name assigned name[I]. To set the bus naming style, use the Synthesis > Options > Project page. dHDL Library FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express stores designs in HDL libraries. The default is a single library called WORK. To analyze and store files in a library other than WORK, click the right mouse button in the Design Sources window, and select New Library to create a new library. To add files to the new library, click the right mouse button in the Design Sources window, and select Add Sources in . You can analyze VHDL packages into a named design library where they can be explicitly referenced in the source files. In this example, the source containing the package STD must be associated with the library STD: LIBRARY STD; USE STD.TYPES.ALL; Source files associated with named libraries must be analyzed first so that other sources referring to that library can be analyzed successfully. You can also use named HDL libraries to manage multiple designs with the same names. +U8~gImplementation Terminology Elaboration Implementation status icons Linking Top-level design Elaboration Elaboration is the process of mapping a design to technology-independent library cells. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express infers logic from the source code logic (for example, an if-then-else statement is translated into an and-or network), sequential elements, and operators from the operations (for example, a + is translated into an addition operator). Only designs in files that are analyzed can be elaborated. Elaboration is part of the Create Implementation process. b8Linking Linking resolves all the design and library component references for the top-level design and for all other designs in the design hierarchy. See also Implementation Status Icons. Top-Level Design An HDL design can be partitioned into a set of smaller subdesigns. This partitioning produces a hierarchy of designs. The top-level design refers to the design at the top of this hierarchy. After analyzing the source files, select the top-level design for an implementation, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express recognizes the complete design hierarchy.E28GGlobal Buffer Terminology Global Buffer Global Buffer Insertion Global Buffer You can use global buffers to drive clocks or high fanout nets to make a design faster, minimize clock skew, or make the routing task easier. Some buffers can drive all nets, others can only drive clock nets. Buffers are architecture-dependent. Global buffers are usually a limited resource. Global buffers are available only to designs using Actel or Xilinx technologies that do not have the Do Not Insert I/O Pads option selected. 8Global Buffer Insertion Global buffer insertion is the process of inserting global buffers into the netlist to minimize clock skew and make designs faster and easier to route. Global buffer insertion takes into account architecture-dependent issues such as the number of buffers available for a particular architecture and the ability of a global buffer to drive nonclock signals. Global buffer insertion is part of the optimization process. You cannot insert global buffers into netlists of designs that you compiled with the Do Not Insert I/O Pads option selected. You can enter port-specific directives in the Global Buffer column of the Ports constraint table for Actel or Xilinx technologies. In the first row, you can set the default for all ports using the values in the pull-down list: Automatic FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express decides where to insert global buffers) Dont use (no insertion of global buffers). You can enter values for individual portsf using the pull-down list in that cell, choosing from automatic, dont use, or a specific buffer type. For a specific buffer type, the global buffer insertion process tries to add a buffer of that type at this port. When a buffer cannot be assigned to a port, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not accept this directive. +8qProject Management Terminology FPGA netlist files Project Project file Project state Source files FPGA Netlist Files FPGA netlist files are text files that contain the design netlist description, in EDIF or XNF format as appropriate. *`8Project A project is a directory (folder) created by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. This directory holds a project file and subdirectories created by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express for internal and intermediate files. You do not need to look at the contents of the subdirectories; they are automatically maintained by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. Project File FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express creates the project file. This file contains all the information for FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express needs to reopen an existing project. The project file resides in a directory created by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express for the project. The project file has an .exp extension a8Oementation even though it is out of date with your most recent source file. Therefore it is important to pay attention to the implementation status icons. ,Source Files Source files are text files that contain the design description. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express accepts design descriptions in VHDL, Verilog HDL, XNF, and EDIF. Source files may be created using any Windows-compliant editor.o386Module and Hierarchy Optimization Terminology Modules and module boundaries Operator Operator sharing Primitive Primitive optimization LModules and Module Boundaries A module is part of an implementation hierarchy and is the container for its submodules. A modules label is the name of its top-level (root) design. The top-level design of an implementation hierarchy is associated with the top level design of this hierarchy. A module has a boundary defined by its ports. Module boundaries can be preserved or eliminated during optimization. You can use the Preserve and Eliminate settings in the Hierarchy column of the Modules constraint table to control whether boundaries are preserved during optimization. When the boundary of a module is preserved during optimization, the logic in this module is optimized independently of the logic in the rest of the modules container. When the boundary is eliminated during optimization, the logic in the module is optimized together with the rest of the logic in the container. In most cases, boundary elimination produces better results because optimization is global rather than local^8L. Eliminate is the recommended setting for achieving better quality of results. However, using Preserve can shorten compilation time.. [xects the best implementation for each of them during optimization. This example design described in VHDL contains two arithmetic expressions, an addition expression and a subtraction expression. Each expression has an operator (+ and -) and its operands (A and B). entity my_design is port( A : in integer range 0 to 65535; B : in integer range 0 to 65535; S : in BOOLEAN; Z : out integer range 0 to 65535 ); end my_design; architecture behavioral of my_design is begin process (A, B, S) begin if (S) then Z <= A + B; else Z <= A - B; end if; end process; end behavioral; ^8[Operator FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express handles these types of operators: logical, relational, and arithmetic. The logical operators are AND, OR, NAND, NOR, XOR, and XNOR. Logical operators found in HDL source code are converted into Boolean logic equations during elaboration. The relational operators are EQ (equal), NEQ (not equal), LT (less than), LE (less than or equal to), GT (greater than), and GE (greater than or equal to). The arithmetic operators are ADD (adder), SUB (subtracter), and MUL (multiplier). Note that there are other predefined arithmetic operators in VHDL that are converted into logic equation during elaboration (see the FPGA Compiler II / FPGA Express VHDL Reference Manual). Relational and arithmetic operators are not converted into Boolean logic equations during elaboration but are kept as special elements in the designs until optimization. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically seljOperator Sharing This example shows a design described in VHDL containing two operators, an adder and a subtracter. The example shows the difference that operator sharing makes to a design implementation. entity my_design is port( A : in integer range 0 to 65535; B : in integer range 0 to 65535; S : in BOOLEAN; Z : out integer range 0 to 65535 ); end my_design; architecture behavioral of my_design is begin process (A, B, S) begin if (S) then Z <= A + B; else Z <= A - B; end if; end process; end behavioral; Most synthesis tools implement this design using two independent hardware resources, one to implement the A + B addition, and one to implement the A - B subtraction. The outputs of these two pieces of logic go into a multiplexer controlled by S to produce Z. This is what FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express produces if you set the value of operator sharing for this design to Off in the Modules con^8jstraint table. For FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express to produce a smaller and faster implementation, leave the value of operator sharing to On in the Modules constraint table. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express generates faster and smaller logic for this design by using an adder / subtracter with A and B as inputs, controlled by S. This implementation also eliminates the multiplexer driving Z, which is now the output of the adder / subtracter. There are cases in which implementing several operators using the same hardware resource would not produce a smaller or faster implementation than the one in which each operator has its private resource. Making the decision to implement several operators using the same hardware resource can require complex computations, such as the computations FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express performs for you when operator sharing for a module is left at On (by defjault). Whether operator sharing is on or off, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express automatically selects the best implementation for every required hardware resource. The implementation is chosen from a large variety of implementations, including those supplied by vendors and those especially developed for FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express by Synopsys. 8zNconstraint table. See Primitive Optimization and Module Constraint Entry. zPrimitive A primitive is a basic technology library unit used in vendor netlists. For information about the primitives in a specific architecture, see the documentation for the technology vendor's library. You can also instantiate primitives in the HDL description of a design by using named association. The following example shows how to instantiate a primitive named BUF1 that has two ports, input I and output O. VHDL requires that you declare both the component and the instance. . . . component BUF1 port(I : in std_logic; O : out std_logic); end component; . . . begin u1: BUF1 port map( I => signal_a,r O => signal_b); Verilog requires only the instance declaration. BUF1 u1(.I(wire_a), .O(wire_b)); Primitives used in design source files are preserved during the analysis and elaboration phases. Whether the boundaries of these primitives are preserved or not during the optimization phase is controlled by the values you set in the Module `8Primitive Optimization The way FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express handles primitives during optimization is controlled by the values you set in the Modules constraint table. When you leave the value of the primitives of a module as Preserve, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express preserves the boundaries of all the primitives used in this module and the implementation of every primitive is the one provided by the architecture vendor. Preserve is the default setting. When you set the value of the primitives of a module to Optimize, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes the logic of the primitives used in the module together with the logic of the module. Optimize is the recommended setting if you do not have instantiated primitives (when optimizing gate-level netlists, for example). Some primitives cannot be optimized by FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express because the vendor does not provide a logic model for them. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express always preserves the boundaries of these primitives. Note that buffers and inverters are never preserved. 8PGlobal Set and Reset Terminology GSR inferencing Global Set / Reset (GSR) Global Set / Reset (GSR) The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. Z8GSR Inferencing FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express has built-in optimization that automatically detects the presence of global set/reset (GSR) signals in your design. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express marks the signal with a target technology-specific GSR marker block. Place and route tools use this marker to identify the GSR signal and route it using dedicated routing. Automatic GSR signal detection and dedicated routing assignment help improve the performance of your design in two ways: The signal has very little routing delay as compared to routing through the general routing resources General-purpose routing resources are not required and are free to route other critical signals. A net is recognized as a GSR net if your design contains one of the following: A net that sets or resets all the sequential elements in your design. A GSR marker cell identifying a net as a GSR net. In this case, if the net marked as GSR does not have explicit connections to the set or reset pin of all sequential elements in the design, the GSR mapper explicitly connects the marked net to the set/reset pins.  In Xilinx architectures, a sequential element can be either preset or reset, but not both. The GSR mapper checks that all sequential devices in the design meet this requirement. Specifically, the mapper checks: A sequential element with an INIT value of R can have only an asynchronous clear pin; it must not have an asynchronous set pin. A sequential element with an INIT value of S can have only an asynchronous set pin; it must not have an asynchronous clear pin.  If the design has a sequential element that violates either of these two conditions, the GSR mapper generates an error message. When you merge netlists that already have GSR nets in them, the GSR mapper checks that GSRs in individual netlists are logically connected. The GSR mapper issues an error if one or more of the following is true: The designZ8 has more than one GSR marker block located on different nets. The design has a net that asynchronously sets or resets all sequential devices and has a GSR marker block on a separate net. Sequential elements have attributes (such as INIT) implying a connection that conflicts with the connections to the net marked by the GSR marker block.  Make sure that the GSR marker block is being used in a consistent manner before reading the design into FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. GSR inferencing works only if your design does not contain any unlinked cells. If your design has an unlinked cell, the GSR mapper makes the conservative assumption that the unlinked cell has sequential elements that are not asynchronously set or reset by a GSR signal, and generates a warning that the GSR resource cannot be used because of the unlinked cell. For certain target technologies (the Xilinx XC3000, for example), the place and route tools do not support the GSR mark6er methodology. Therefore, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express cannot automatically assign the GSR signal in your design to on-chip GSR dedicated resources. Refer to the target technology vendor's GSR methodology guide for the steps required to assign the GSR signal to on-chip GSR dedicated resources. If you do not perform the vendor-specific steps, the GSR signal is routed using the general-purpose resources instead of the dedicated resources. This could impact the overall performance of the design because The GSR signal will have greater routing delay than if it used dedicated resources. The overall routing congestion on the chip increases because the GSR signal (which connects to every sequential element in your design) uses up some of the general-purpose routing resources.  k38> d &WordMicrosoft Word   System    -& .  --    &WordMicrosoft Word  Systemw ;|w|wgww ; -@Times New Roman|wgw2 H - & .  --   b&*x &&#TNPPp0x & TNPP &&TNPP   b &,v&lr z& -333- * $ilLPM A library of parameterized macros (LPM) is a library of flexible design elements that you customize by assigning values to parameters. LPMs include such functions as counters, decoders, and RAM. Each function has parameters such as data width and reset values.b8OSupported Architectures FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express supports these architectures from the following FPGA and PLD vendors: Actel ProASIC 500 K 54SX, 54SX-A Logic Integrator Series (1200AL, 3200DX) Accelerator Series (1400) Altera ACES Series APEX Series (20K, 20KE) FLEX Series (6000, 8000, 10K, 10KA, 10KB, 10KE) MAX Series (7000, 7000A, 7000AE, 7000E, 7000S, 9000) Lucent ORCA Series (ORCA2A, ORCA2TB, ORCA3C, ORCA3FPSC, ORCA3L) Xilinx Spartan Series (Spartan, Spartan-2, Spartan-XL) XC3000 Series (XC3000A, XC3000L, XC3100A, XC3100L) XC4000 Series (XC4000E, XC4000EX, XC4000L, XC4000XL, XC4000XLA, XC40000XV) XC5200 Series (XC5200) XC9500 Series (XC9500, XC9500XL, XC9500XV) Virtex Series (Virtex, Virtex-E) Others Atmel, Cypress, DataIO, Dynachip, Lattice, QuickLogic, Triscend, Vantis kSupported Architectures FPGA Compiler II / FPGA Express supports these Xilinx technology architectures: Spartan Series (Spartan, Spartan-2, Spartan-XL) XC3000 Series (XC3000A, XC3000L, XC3100A, XC3100L) XC4000 Series (XC4000E, XC4000EX, XC4000L, XC4000XL, XC4000XLA, XC40000XV) XC5200 Series (XC5200) XC9500 Series (XC9500, XC9500XL, XC9500XV) Virtex Series (Virtex, Virtex-E) See these topics when Xilinx is your target technology: How to define multicycle timing constraints How to use memory elements with Xilinx devices How to implement global buffers for Xilinx devices Exporting netlists for Xilinx uc8(YWhen Actel Is the Target Technology See Design flow targeting Actel Designer Devices. 3\When Altera Is the Target Technology See these topics when Altera is your target technology: Design flow targeting Altera FLEX and MAX devices How to use memory elements with Altera devices Using Altera MegaWizard components in FPGA Compiler II Altera Edition FPGA Express Exporting netlists for Altera Using LPMs Megafunctions/LPM L8EWhen Lucent Is the Target Technology See these topics when Lucent is your target technology: Design flow targeting Lucent ORCA 2CA and 2TA devices How to use memory elements with Lucent devices Exporting netlists for Lucent SWhen Xilinx Is the Target Technology See these topics when Xilinx is your target technology: How to define multicycle timing constraints How to use memory elements with Xilinx devices How to implement global buffers for Xilinx devices Exporting netlists for Xilinx 38cOther Supported Target Technologies For devices from Atmel, Cypress, DataIO, Dynachip, Lattice, QuickLogic, Triscend, and Vantis, see Design flow targeting supported devices.sDesign Sources Window The Design Sources window contains the source files and libraries for each project in a hierarchical tree. Double-click each project, library, or source file to expand or contract that level of the tree. Information about the selected project, library, or source file is shown in the Errors/Warnings window at the bottom of the project window. To work with the design sources, click the right mouse button to display this popup menu: Update File (Library, Project) Force Update File (Library, Project) Create Implementation Edit File Add source in New Library File Report (Library, Project) Remove  8mSynthesis / Create Implementation command Creates a new implementation (chip) from the selected design file.  Edit File command Invokes a text editor in a separate window so you can edit the source file for the selected design. You can use the General page from Synthesis > Options to select the built-in HDL Editor or an external editor that you have assigned to the file. 38Add Source in command Adds and automatically analyzes a new design source file for the selected library. The design source file remains in its original location and is not copied into the library, but is added to the list of files that make up the library. A design source can be in only one library in a project. See also Analysis Order for information about the order in which you add files to a library. <New Library command Creates a new library for this project. )8\Remove command Removes the selected design file from a library or a library from a project. Editor You can use the built-in HDL Editor or any assigned editor to modify your HDL design source file. Select Synthesis > Options for the General page containing the "Use FPGA Compiler II / FPGA Express internal source editor" option. When you select a design source, click the right mouse button, and select Edit File, you start the editor and open the selected file. The editor can be an external program such as Notepad, which you have assigned to open your HDL files. If you select the built-in HDL Editor (the default), a separate window opens at the line containing the first error, which is displayed in red. A window on the bottom describes the particular error. See also Editing an HDL Design Source. v[8MHDL Editor The HDL Editor is a built-in feature of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express that you can invoke through the Edit menu item in the Design Sources window if you have selected "Use FPGA Compiler II / FPGA Express internal source editor" in Synthesis > Options. When you right-click a file and select Edit File. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express opens a separate HDL Editor window containing the source for the selected design. The HDL Editor opens at the line containing the first error, which is displayed in red. A window on the bottom describes the particular error.  Clicking on the right mouse button displays a menu to let you save and navigate in the file: Save Undo Analyze File Next Error Previous Error Find Text Find Again Line Numbers. ?Save command Saves all changes made to the design source file. n28DUndo command Undoes the last edit action on the design source file. HAnalyze File command Analyzes the design source file for syntax errors. U8TLine Numbers command Toggles display of the line numbers in the design source file. CEditing an HDL Design Source To edit an HDL design source file: Select the design source file in a library. Click the right mouse button. Select Edit File from the menu. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express opens an HDL Editor window containing the source file for the design. If there are any errors or warnings, the HDL Editor opens at the first error, displayed in red with an explanation at the bottom of the Editor window. In the HDL Editor window, click the right mouse button to open an Edit menu or pull down the Edit menu in the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express main window. Use Next Error or Previous Error in either menu to navigate in the file. Reanalyze the design by clicking the Analyze File item in the Edit menu or click the Update icon in the tool bar.?18 BChips Window The Chips window displays the elaborated and optimized implementations (chips) for the selected design. The name of each chip uses the design name as its base. In parentheses, the name includes the names of the target technology vendor, the family, and the device, and the speed grade. Double-click each chip to expand or contract that level of the tree. To enter constraints for the chip, view calculated delays, or optimize, click the right mouse button to display this menu: Edit Constraints View Schematic Update Chip Force Update Chip Optimize Chip Export Netlist Place and Route Chip Backannotate Chip Export DC Script Export DC Chip Chip Report Delete Chip  Information about the selected chip is shown in the Errors/Warnings window at the bottom of the project window. 7Chips Window The Chips window displays the elaborated and optimized implementations (chips) for the selected design. The name of each chip uses the design name as its base. In parentheses, the name includes the names of the target technology vendor, the family, and the device, and the speed grade. Double-click each chip to expand or contract that level of the tree. To enter constraints for the chip, view calculated delays, or optimize, click the right mouse button to display this menu: Edit Constraints Optimize Chip Update Chip Export Netlist Chip Report Delete Chip  Information about the selected chip is shown in the Errors/Warnings window at the bottom of the project window. U8TEdit Constraints command When you select Edit Constraints for an elaborated chip, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables where you can enter requirements in terms of Clocks, Paths, Ports, and Modules. The Registers and Vendor Options constraint tables are available only for selected technologies. See also View Results. `Update Chip command Updates the selected chip. If you modify a design source file, you should update all implementations of the designfirst the unoptimized chips, then the optimized chips. [8l_Delete Chip command Deletes the selected implementation from the project and the Chips window. uView Results command Runs the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express TimeTracker and opens the constraint tables for the selected optimized chip. When you select View Results for an optimized chip, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables containing the requirements you entered with additional columns showing the results of optimization. For example, timing requirements are displayed beside the estimated delays calculated by TimeTracker. The Modules constraint table includes additional area detail such as cell count. You can use the constraint tables for the optimized chip to see how well your design meets your requirements. See also: Clocks Constraint Table After Optimization Paths Constraint Table After Optimization Ports Constraint Table After Optimization  Modules Constraint Table After Optimization Registers Constraint Table After Optimization\8E added to ease migration for FPGA Compiler users who are moving to to FPGA Compiler IIFPGA Compiler II Altera Edition. FST is capable of writing simple Design Compiler shell scripts that can be used as a starting point for synthesizing an ASIC version of an FPGA Compiler IIFPGA Compiler II Altera Edition chip. This feature is unique to FPGA Compiler IIFPGA Compiler II Altera Edition and not available in FPGA Express. Note You may read this document by paging through it with the << and >> buttons, or you may select topics from the Help Topics Contents tab. Introduction to FPGA Scripting Tool (FST) FPGA Scripting Tool (FST) implements a TCL-based command-line interface to all the synthesis and optimization features of FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. FST is designed for those users who Are more accustomed to command-line or keyboard-based interfaces than with graphical interfaces. Understand the capabilities of the tool and wish to specify operations as quickly as possible, thus, a specification that might require multiple mouse clicks and keyboard entries can be entered as a single command.  The data models defined by the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express GUI are preserved in command line form by FST. Command-line conventions established by the PrimeTime and Design Compiler products are followed so long as they are consistent with this data model. Since FST is used as the command-line interface for FPGA Compiler IIFPGA Compiler II Altera Edition, a few features are?8FST Summary of Features FST provides the following general features. Note that some are common to both FPGA Compiler II Altera Edition / FPGA Express, while others are specific to FPGA Compiler II. Features found in both FPGA Compiler II Altera Edition / FPGA Express: Tcl-based command-line editor A common command set with PrimeTime and Design Compiler, where applicable Command abbreviation Command logging User-controllable continuation on command errors Compatibility with projects created by the FPGA Compiler II Altera Edition / FPGA Express GUI Features available only in FPGA Compiler II Altera Edition / FPGA Express: Design Compiler compatibility with the ability to output Design Compiler scripts for a chip. FST Compatibility with FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express FST can read all projects created by corresponding versions of the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express GUI and earlier. ]8Invoking FST FST itself is invoked from either a UNIX or Windows command shell, using this command for FPGA Compiler IIFPGA Compiler II Altera Edition: fc2_shell or this command for FPGA Express: fe_shell FST can be invoked with the following options: -help Lists the options available -f[ile] filename Executes the FST script file filename. FST FPGA Compiler IIFPGA Compiler II Altera Edition files have an .fc2 extension, FPGA Express files have an .fes extension. -t[ime] timelimit Limits the CPU time for a shell session to timelimit, specified in seconds. After the specified number of CPU seconds, an error message will be displayed and the shell session will be terminated. -l[og] filename Specifies the name of a log file. Commands passed to the shell are saved in this log file. The default name for this file is either fc2_shell_command.log, for FPGA Compiler IIFPGA Compiler II Altera Edition, or fe_shell_command.log, for FPGA Express. Executing FST with no options inFST Commands The following objects defined by the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express data model are implemented in FST: project library file chip module clock group path group In addition, the following netlist objects are implemented in FST: design port padcell net pin For information on specific FST commands, see the man pages. See Variables and Attributes for more information. FST commands are in the form: __ Commands are organized into command groups, either by action or by object. A special command group built-in contains a list of supported Tcl keywords, as well as some generic command-line utilities common to Synopsys command-line interfaces. The list of available commands can be displayed by the help command. Additional detail for a particular command can be obtained by invoking the command with the -help option, or by invoking the help command with the command name as an argument. Commands and options that are not Z8in the built-in command group can be abbreviated as long as the abbreviation is unique. If the abbreviation is not unique, a list of matching commands is displayed. Current Project Most FST commands require a project to be opened. Once a project is open, it is referred to as the current project. Currently, only one project can be opened at a time. Some variables exist only when a project is opened. These variables have names beginning with "proj_". Current Chip Commands that operate on chips usually operate on the current chip. The current chip is set by the current_chip command. Modifications to the current chip are generally not saved until the user changes the current chip or closes the current project. The exceptions to this rule are commands that take a chip name as an argument. For example, some commands, such as export_constraint or export_netlist, export information from a chip to a file. These commands require a chip as an argument and will read a chip before it writes the necessary information. If the chip to be exported is the current chip, it will automatically be saved to disk. This behavior ensures that a file correctly reflects the state of a chip in a project. 98Variables and Attributes in FST The following command argument types should be replaced by values of the following forms: pad "/top/port_name" path_group "(RC,CLK):(O)" module "/top/cell_name" design "/lib/design_name" clock "clock_name" project "project_name" library "lib_name" file "path name" chip "/project_name/chip_name" pin "/top/cell_name/pin_name" cells "/top/cell_name" The variables and attributes listed below may take these values: proj_act_max_fanout = "16" proj_alt_insert_lcells = "yes" (default), "no" proj_altera_insert_lcell = "yes" (default), "no" proj_clock_default_frequency = "28" proj_export_timing_constraint = "yes" (default), "no" proj_fsm_coding_style = "onehot" (default), "binary" proj_fsm_optimize_case_default = "yes" (default), "no" ("when others"?) or proj_fsm_when_others = "fastest" (default), "safest" proj_gsr_ignore_unlinked_cells = "yes" (default), "no" proj_xlx_ppr = "M1" (default), "XACT" proj_xnfin_bus_style = "any string"; default is "%s<%d>" # FST Man Pages Help pages are available for FST commands. To access the shell prompt, On PC installations, go to the start menu and choose Programs > Synopsys > FPGA Compiler II Shell or FPGA Express Shell. On UNIX installations of FPGA Compiler II, enter fc2_shell in a shell window. At the shell prompt you can access man page help for FST: For a list of all FST commands, enter help For information about a particular command, enter man commandname For help about FST itself, enter this command for FPGA Compiler II: man fc2_shell or this command for FPGA Express: man fe_shell For help about the man pages, enter man help If you are working on a PC system and the information is not presented a page at a time, see Resizing the Shell Window on PC Installations. Ka8@Resizing the Command / MS-DOS Prompt Window on PC Installations On some PC systems, the man page text may not be presented one page at a time, but may scroll off the top of the screen instead. If this happens, Click the icon in the top left corner of the command / MS-DOS prompt window. Click the Layout tab. Change the Height settings under Screen Buffer Size and Window Size Height to larger numbers and click OK. (Screen buffer sizes are large as 999 can be entered.) In the dialog box that appears, select either to apply properties to current window only, or to modify the shortcut that starts the command / MS-DOS prompt window; then click OK. Enter the man page commands you wish and use the scroll bar to see the entire text. Note that man page text can also be redirected to a file.USchematic Viewer Vista (Visual Tools for Analysis), the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Schematic Viewer, works with TimeTracker to allow you to view your designs graphically. The Schematic window can display both preoptimized and optimized designs. For more information, see: Features of the Schematic Viewer Using the Vista Schematic Window Viewing Unoptimized Schematics Viewing Optimized Schematics 48i: contributor to routing congestion and timing degradation in many FPGA architectures. You can easily trace the fan-in and fan-out paths for a given cell using the Filters -> Fan-in cone and Filters -> Fan-out cone commands. Fan-in and fan-out analysis can be performed on both unoptimized and optimized designs. i chip in the Chips window. Select View Schematic.  Hierarchy Browsing Both unoptimized and optimized views are linked with the hierarchy browser. If the hierarchy for a given chip is expanded, you can use the hierarchy browser to walk up and down the different levels of hierarchy. This significantly simplifies the process of following signals to better understand a design. Critical Path Analysis The optimized view of a design is tightly integrated with the TimeTracker timing estimation engine: You can select a given clock group, path or cell within TimeTracker and see the corresponding information highlighted in the schematic. You can walk backwards and forwards on a critical path by using the Next Pin and Previous Pin commands. Placing the cursor on a given cell in the critical path causes fan-in, fan-out and timing information to be displayed for the cell. You can filter the highlighting on a schematic based on estimated timing. Fan-In and Fan-Out Analysis High fan-out is a keyc8iFeatures of the Schematic Viewer With the schematic viewer, you can view your designs in a number of ways: Preoptimized or RTL Schematic View By viewing your preoptimized design, you can evaluate the connectivity of a circuit, inspect the design for inferred operators, and get a feel for how the tool interpreted the RTL being processed. You can always step up and down through the levels of hierarchy of a preoptimized design. To view a preoptimized design: Right-click the elaborated chip in the Chips window. Select View Schematic.  Optimize or "Mapped" View Viewing an optimized design allows you to evaluate how the design has been mapped to a given technology. You can see features such as carry chains, cascade chains, LUTs, and other architecture-specific elements in the design. If the Preserve Hierarchy option is selected prior to synthesis, you can also step up and down through the levels of hierarchy in an optimized design. To view an optimized design: Right-click an optimized[Using the Vista Schematic Window The Vista Schematic window is a window within the program, and responds to all of the Windows window-management commands. General information on using the Schematic window: Opening the Schematic Window Zooming Into and Out of a View Hints on Managing FPGA Compiler II Altera Edition FPGA Express Windows 68lOpening the Schematic Window You can open a Schematic window in any of these ways: Select a chip in the Chips window on the right-hand side of the Project window, and choose Synthesis -> View Schematic from the main menu Right-click to select a chip in the Chips window on the right-hand side of the Project window, and choose View Schematic from the popup menu. Zooming Into and Out of a View You can zoom into and out of a view in several ways. To magnify the view by a factor of two: Use the Zoom In and Zoom Out buttons on the View tool bar. Use the hotkeys "i" (to zoom in) and "o" (to zoom out). Use the View -> Zoom In and View -> Zoom Out commands on the main menu. To zoom into an area: Left-click the Zoom In Tool button on the View tool bar, left-drag the mouse through the area of interest, then release the mouse button. Use the Zoom In button on the tool bar; then use the scroll bars in the Vista window. To return the view to "best-fit": Use the Zoom Full-Fit button on the View tool bar. Use the hotkey "f". Use the View -> Zoom Full command on the main menu. [8Hints on Managing FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Windows Schematics often take a large amount of screen to display;. You will soon find that the screen can never be big enough! The following hints may help you manage FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express window space. Close off any windows that are not required the tip bar and the Output window at the bottom of the screen, for example. Maximize the schematic window to increase the viewing size. Expand the hierarchy shown in the Chips window, and then resize the Chips to the left hand side of the screen. This allows easy navigation of the chip hierarchy. Use the Windows Ctrl-Tab key sequence to step through the windows within an application. This is particularly useful when switching between maximized windows in this case, the maximized schematic window and maximized TimeTracker window. Viewing Unoptimized Schematics To view an RTL or generic schematic, select an unoptimized chip in the Project window and follow the instructions under Opening the Schematic Window. Note that in a schematic of an unoptimized chip, the hierarchy is always preserved. Other information on viewing unoptimized schematics: Stepping Into and Out of the Chip Hierarchy Interpreting the Symbols in an Unoptimized Schematic ;48Stepping Into and Out of the Chip Hierarchy You can step into and out of the hierarchy of an unoptimized chip in a number of ways: Expand the chip hierarchy in the Chips window, and select any level of hierarchy. The schematic window displays the selected level. Left-double-click on a hierarchical block in a schematic, or a lookup table cell. The contents of the block or cell are displayed. Right-double-click anywhere in a schematic. The next level up is displayed. Interpreting the Symbols in an Unoptimized Schematic The cells used in an unoptimized schematic are generic cells, not mapped to any target technology. Operators are displayed along with blocks of hierarchy. .8Viewing Optimized Schematics To view an optimized or mapped schematic, select an optimized chip in the Project window and follow the instructions under Opening the Schematic Window. The TimeTracker window and optimized schematic will both be displayed. The cells displayed in the optimized schematic consist of vendor-specific cells. For more information on viewing optimized schematics: Using the Viewer with the TimeTracker Window Viewing Fan-In and Fan-Out Cones  Using the Viewer with the TimeTracker Window The TimeTracker window, displayed along with the optimized schematic, is a useful tool in debugging the design. Cross-highlighting between the Time Tracker window and the optimized schematic is available. Selecting a Timing Group in the Schematic To highlight all register cells in the schematic: Select a timing group from the top-left section of the TimeTracker window.  Highlighting Paths with Negative Slack To apply emphasis highlighting to paths with negative slack, or to hide paths with positive slack: Select Filters -> Delay Filter Value, and enter slack values in the Timing Slack Filter dialog box for paths to be hidden, and paths to be emphasized. Select Filters -> Show More to increment the values in the Timing Slack Filter dialog box by 4 ns. Select Filters -> Show Less to decrement the values in the Timing Slack Filter dialog box by 4 ns. Selecting Subpaths in the Group To highlight a subpath in the schematic: Select a timing pa58 th from the bottom-left section of the TimeTracker window.  Displaying Additional Information About a Cell To display additional information about a cell, for example, pin numbers in the critical path, fan-out values, and the path slack value: Pause the mouse pointer above the cell. Highlighting a Pin To highlight a pin in the schematic: Select a pin in the right-hand side of the TimeTracker window.  The schematic window may change to display a different level of hierarchy if necessary. Walking from Node to Node in a Subpath Step from pin to pin in the selected path in any of these ways: Select pins sequentially in the TimeTracker window. Click the Next Pin and Previous Pin buttons on the View tool bar. Select either Filter -> Next Pin or Filter -> Previous Pin from the main menu. ,Viewing Fan-In and Fan-Out Cones To highlight the fan-in and fan-out cones of logic for a cell: Select a cell on the schematic using the left mouse button or via Time Tracker. Click one of these buttonsFan-In, Fan-Out, Fan-In and -Out; or select one of these commandsFilters -> Fan-In Cone or Filters -> Fan-Out Cone. The fan-in and/or fan-out cones for the selected cell are highlighted. U8<Export DC Shell Script command Exports a DC shell script for the current chip (FPGA Compiler IIFPGA Compiler II Altera Edition). EUExport FPGA Shell Script command Exports an FPGA shell script for the current chip. $c8N!Place and Route Chip command Exports the EDIF, LMF, and TCL files for an optimized design targeting Alteras APEX20K devices and launches Quartus, Alteras place and route tool, in the background. Quartus messages are displayed in the Status bar at the bottom of the Output window. XView Schematic command Opens Vista (Visual Tools for Analysis), the FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express schematic viewer, for the selected implementation. ԰8YE Opens the selected design source file in the built-in HDL Editor. iEDFN-102 Message %1 Description The variables edifin_lib_ripper_cell_name and edifin_lib_ripper_view_name specify that the ripper cell attributes be included on that view of that cell. 78yEDFN-103 Message %1 Description The variable edifin_lib_ripper_cell_name specifies that the ripper cell attributes be included on that view (because it's the first view) of that cell. hEDFN-104 Message %1 Description The 'RIPPER' cellType of that cell specifies that the ripper cell attributes be included on the view of that cell that has been defined by setting the variable edifin_lib_ripper_view_name to be the correct view of the bus ripper cell, but the specified view wasn't found. What Next If that cell is the correct one to use as the bus ripper cell, then (1) determine which view of that cell is the correct one to use, (2) set the variable edifin_lib_ripper_view_name to define that view to be the correct one, and (3) execute the edif format read_lib command again. If that cell isn't the correct one to use as the bus ripper cell, then (1) determine which cell is the correct one to use, (2) set the variable edifin_lib_ripper_cell_name to define that cell to be the correct one, and (3) execute the edif format read_lib command again. 78EDFN-105 Message %1 Description This error occurs when the EDIF reader parses the EDIF file and detects an improperly formed identifier (one containing a character that cannot be part of an identifier). What Next To fix the problem, refer to the line number in the error message to locate the improperly formed identifier and correct it. Examples 1 (edif Synopsys.edif (edifVersion 2 0 0) (edifLevel 0) 2 (keywordMap (keywordLevel 0)) (status) 3 (external (rename ADDER_db "ADDER.db") (edifLevel 0) 4 (technology (numberDefinition)) 5 (cell ADDER (cellType GENERIC) ... Example Message Error: Line 1: invalid identifier token. (EDFN-105) EDFN-106 Message %1 Description This error occurs when the EDIF reader parses the EDIF file and detects an improperly formed integerToken (one containing a character that cannot be part of an integerToken). What Next To fix the problem, refer to the line number in the error message to locate the improperly formed integerToken and correct it. Examples 1 (edif Synopsys_edif (edifVersion 2B 0 0) (edifLevel 0) 2 (keywordMap (keywordLevel 0)) (status) 3 (external (rename ADDER_db "ADDER.db") (edifLevel 0) 4 (technology (numberDefinition)) 5 (cell ADDER (cellType GENERIC) ... Example Message Error: Line 1: invalid integer token. (EDFN-106) 78EDFN-116 Message %1 Description The 'RIPPER' cellType of that cell and the variable edifin_lib_ripper_view_name specify that the ripper cell attributes be included on that view of that cell. EDFN-117 Message %1 Description The 'RIPPER' cellType of that cell specifies that the ripper cell attributes be included on that view (because it's the first view) of that cell. 78nEDFN-120 Message %1 Description The variable edifin_lib_ripper_cell_name specifies that the ripper cell attributes be included on the view of that cell that has been defined by setting the variable edifin_lib_ripper_view_name to be the correct view of the bus ripper cell, but the specified view wasn't found. What Next If that cell is the correct one to use as the bus ripper cell, then (1) determine which view of that cell is the correct one to use, (2) set the variable edifin_lib_ripper_view_name to define that view to be the correct one, and (3) execute the edif format read_lib command again. If that cell isn't the correct one to use as the bus ripper cell, then (1) determine which cell is the correct one to use, (2) set the variable edifin_lib_ripper_cell_name to define that cell to be the correct one, and (3) execute the edif format read_lib command again. EDFN-121 Message %1 Description The 'RIPPER' cellType of that cell and the variable edifin_lib_ripper_cell_name specify that the ripper cell attributes be included on the view of that cell that has been defined by setting the variable edifin_lib_ripper_view_name to be the correct view of the bus ripper cell, but the specified view wasn't found. What Next If that cell is the correct one to use as the bus ripper cell, then (1) determine which view of that cell is the correct one to use, (2) set the variable edifin_lib_ripper_view_name to define that view to be the correct one, and (3) execute the edif format read_lib command again. If that cell isn't the correct one to use as the bus ripper cell, then (1) determine which cell is the correct one to use, (2) set the variable edifin_lib_ripper_cell_name to define that cell to be the correct one, and (3) execute the edif format read_lib command again. 78EDFN-122 Message %1 Description The 'RIPPER' cellType of that cell and the variables edifin_lib_ripper_cell_name and edifin_lib_ripper_view_name specify that the ripper cell attributes be included on that view of that cell. !EDFN-123 Message %1 Description The 'RIPPER' cellType of that cell and the variable edifin_lib_ripper_cell_name specify that the ripper cell attributes be included on that view (because it's the first view) of that cell. 780EDFN-127 Message %1 Description To reduce the amount of memory the EDIF format read command takes, a new method of reading rippers is being used. In this method, connections to a ripper with more than two pins are not supported. What Next If the EDIF file contains connections to a ripper with more than two pins, set the variable edifin_old_ripper_reading to TRUE. Then execute again the EDIF format read command. ATFPGA-ANALYZE-XNF-10 Message File '%1': 'C' pins of CY4 cell '%2' are not driven by a Carry Mode cell. Description The XNF analyzer has found that some of the pins 'C1', ..., 'C7' of the CY4 symbol / cell with given name are connected to nets that are not driven by a cell that can be identified as a CYMODE cell, which should the case. 188P5FPGA-ANALYZE-XNF-11 Message File '%1': CY4 cell '%2' does not have a correct set of 'C' pins. Description The symbol / cell whose name is given in the message is a CY4 symbol. It should have the pins 'C0', ..., 'C7'. Some of these pins are missing. The CY4 symbol / cell is thus declared to be incorrect. _FPGA-ANALYZE-XNF-12 Message File '%1': CY4 cell '%2' has no CYMODE parameter or an incorrect one. Description This message is generated in the case when a CY4 symbol / cell in the XNF design being analyzed does not have an associated CYMODE cell, and in addition, it does not have a value or it has an incorrect value for the XNF parameter 'CYMODE'. In this case, it is not possible to create the missing CYMODE cell associated with the CY4 symbol / cell so the design is declared incorrect. 688nFPGA-ANALYZE-XNF-13 Message File '%1': Cell '%2' is not a correct Carry Mode cell (missing or incorrect CYMODE parameter). Description The symbol / cell mentioned in the error message is driving the pins 'C0', ..., 'C7' of a CY4 symbol / cell. However, this cell is not a correct CYMODE symbol / cell. Its type is either not correct or not consistent with the value of the CYMODE parameter found on this symbol. }fFPGA-ANALYZE-XNF-14 Message File '%1': Carry Mode cell '%2' has no CYMODE parameter. Description The symbol / cell mentioned in the error message is driving the pins 'C0', ..., 'C7' of a CY4 symbol / cell. However, this symbol / cell does not have a value for the CYMODE parameter. The correct value has been automatically inferred from the symbol type. ;88FPGA-ANALYZE-XNF-15 Message File '%1': Cell '%2' has no LIBVER parameter or its value is less than 2.0.0. Description The XNF analyzer does not support XNF files with a version older than the version 2.0.0. FPGA-ANALYZE-XNF-18 Message File '%1': Ignores (record parameter) '(%2)': %3 time(s). Description This message indicates that the 'TNM' parameter, used in XNF to form timing groups, has been ignored on the symbols it's been found on. Please refer to warning FPGA-ANALYZE-XNF-19. A88UFPGA-ANALYZE-XNF-19 Message File '%1': Record '%2' is ignored: %3 time(s). Description Some symbols that can be found in XNF files are ignored when an XNF file is analyzed. These are the 'TIMESPEC' and the 'TIMEGRP' used to specify timing constraints, and the 'MODEL' symbol used to describe the simulation model of a CLB or IOB symbol. FPGA-ANALYZE-XNF-20 Message File '%1', line %2: Design '%3' has multiple associated file names: '%4' and '%5'. Description A macro should only one associated XNF file in the XNF design hierarchy being read. D88FPGA-ANALYZE-XNF-21 Message File '%1', line %2: Signals '%3' and '%4' of cell have the same PIN parameter '%3'. Description The 'PIN' parameter is used in XNF to describe how a design should be linked to a cell at a higher level in a hierarchy. It associates a signal / net of the design with a pin of the symbol / cell that will be linked to the design. It is an error if several signal / nets must be linked to the same pin. FPGA-ANALYZE-XNF-22 Message File '%1', line %2: Design named '%3' is being replaced with analyzed design. Description This message warns you that an analyzed design has replaced an design in the project that had the same name. H88FPGA-ANALYZE-XNF-23 Message File '%1', line %2: Symbol name '%3' has already been used. Description XNF requires that all 'SYM' records in a XNF files have different names. FPGA-ANALYZE-XNF-24 Message File '%1', line %2: Pin name '%3' has already been used in symbol. Description XNF requires that all 'PIN' records in a 'SYM' record have different names. K88 FPGA-ANALYZE-XNF-27 Message File '%1', line %2: Pin '%3' cannot be inverted. Description XNF allows some pins to be inverted using the 'INV' parameter. This parameter is not allowed on the pin whose name is given in the error message.  mFPGA-ANALYZE-XNF-29 Message XNF file '%1' cannot be opened to analyze macro '%2'. Description The path name of the XNF file for the macro whose name is given in the message is either the value of the 'FILE' parameter found on this symbol, or the name of the symbol to which is appended the string ".xnf". No file with this pathname could be opened for reading. L88 "FPGA-ANALYZE-XNF-30 Message File '%1', line %2: Pin '%3' is not driven by any net. Description A pin used in a logic equation of an EQN symbol should be connected to a net.  1'FPGA-ANALYZE-XNF-8 Message File '%1', line %2: Variable '%3' in equation is not a pin or is a pin without any net. Description An identifier used in the logic equation of a 'EQN' symbol should be the name of a pin of this symbol. In addition, this pin should be connected to a signal / net. >|8 @FPGA-CHECK-10 Message The net '%1' may have more than one driver. Description This message indicates that the net may have multiple drivers which are not 3-state. Even though design may be error, the tool will preserve this logic throughout optimization. OFPGA-CHECK-1 Message The pin '%1' is not connected to any net. Description This message indicates that a particular pin is not connected to any net. It is a possible design error. T88^FPGA-CHECK-2 Message The port '%1' is not connected to any net. Description This message indicates that a particular port of a design is not connected to any net in the design. It is a possible design error. mmFPGA-CHECK-4 Message The cell '%1' is not linked to any design. Description There are many reasons why a cell is not linked to any design. If the cell is not intentionally left unlinked, some errors must have been generated while creating an implementation. Check the error and warning messages associated with the implementation for more detailed explanation. Y88|FPGA-CHECK-5 Message The net '%1' has more than one driver. Description This message indicates that the net has true multiple drivers which are not 3-state. The tool will stop. FPGA-CHECK-6 Message The net '%1' has no driver. This may cause place-and-route tools to fail. Description This message indicates that the net has no driver. When a net has no driver, it is assumed by the tool that it can be either connected to constant zero or constant one. The tool will make the decision depending on how the net is used. Undriven nets should be avoided, as they may cause problems during placement and routing. >|8&FPGA-CHECK-7 Message The net '%1' has no load. Description This message indicates that the logical value of the net is not used in the design. When a net is not used, it will be removed, along with the logic driving it, by the tool. Please check the design description for possible errors. FPGA-CHECK-9 Message The net '%1' is a feed through net. Description This message indicates that the net connects one or more input ports directly to one or more output ports. Please check the design description for possible errors. [88FPGA-CLEAN-2 Message Duplicate cells '%2' and '%1' merged. Description A pair of duplicate cells have been found in the design. The first named cell was removed and the nets on the output pins of this cell were merged with the nets of the corresponding output pins on the second named cell. Two cells are duplicates if the cell reference types are identical and all corresponding pairs of input pins are connected to the same net. FPGA-DRCFIX-1 Message Cannot isolate ports with direction 'INOUT' on net '%1'. Description The Xilinx net-list reader requires that every net has at most one port on it. The named net has multiple ports attached to it and one of them has the direction 'INOUT'. Inserting a buffer to isolate this port maybe incorrect, and thus is not automatically performed. To fix this problem either modify the HDL or net-list such that the port has a direction input or output (if it is appropriate) or modify the design by merging all the ports on the named net and and in each cell instance of the modified design merging all the nets of pins corresponding to the merged ports. `889FPGA-DRCFIX-2 Message Cannot isolate ports on the net '%1' because it has tristate drivers. Description The Xilinx net-list reader requires that every net has at most one port on it. The named net has multiple ports attached to it and the driver of this net is a tristate. Inserting a buffer to isolate this port is incorrect, and thus is not automatically performed. To fix this problem modify the design by merging all the ports on the named net and and in each cell instance of the modified design merging all the nets of pins corresponding to the merged ports. FPGA-EDFN-1 Message Trouble reading EDIF file '%1'. Description The specified EDIF file does not exist, can not be read, or contains errors. c88EFPGA-EDFN-ALT-1 Message Incorrect variable name '%1' encountered while parsing equation string '%2'. Description The equation string for an Altera LUT is expected to be specified in terms of variables IN1 through IN4 only. The EDIF translator has encountered a different variable name and has hence generated this error. FPGA-EDFN-ALT-2 Message While parsing equation '%1' : '%2'. Description The equation string for an Altera LUT is expected to be specified using the EQN syntax. Please make sure that your input EDIF file uses this syntax. h886FPGA-EDFN-ALT-3 Message Cell '%1' has incorrect design name '%2', LUT expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the Altera primitive LUT. The cell is not an instantiation of one of these designs and hence the error. "UFPGA-EDFN-ALT-4 Message Cell '%1' has incorrect pin name '%2'. Only pin names "IN1", "IN2", "IN3", "IN4", and "A_OUT" expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the Altera primitive LUT. This has pins named "IN1", "IN2", "IN3", "IN4", and "A_OUT". k881FPGA-EDFN-ALT-5 Message Cell '%1' has '%3' input pins which exceeds the maximum allowed on design '%2'. Description The cell is a LUT and can have upto 4 input pins. Please make sure that the cell is of the correct type. @FPGA-EDFN-ALT-6 Message Cell '%1' has an incorrect lut_function property - the EQN string is of zero length. Description The cell has a lut_function property attached to it. This property describes the logic function of the cell and is a Boolean equation describing the function of the output of the cell in terms of its inputs. For this particular cell, this property string is empty. Please ensure that the EDIF input file has been generated correctly. n88OAFPGA-EDFN-O2A-1 Message Incorrect variable name '%1' encountered while parsing equation string '%2'. Description The equation string for an ORCA2A LUT is expected to be specified in terms of variables A through F only. The EDIF translator has encountered a different variable name and has hence generated this error.  ^FPGA-EDFN-O2A-2 Message While parsing equation '%1' : '%2'. Description The equation string for an ORCA2A LUT is expected to be specified using the EQN syntax. Please make sure that your input EDIF file uses this syntax. s88!mkFPGA-EDFN-O2A-3 Message Cell '%1' has incorrect design name '%2', ORCALUT4, ORCALUT5 or ORCALUT6 expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the ORCA primitives ORCALUT4, ORCALUT5 or ORCALUT6. The cell is not an instantiation of one of these designs and hence the error. "|FPGA-EDFN-O2A-4 Message Cell '%1' has incorrect pin name '%2'. Only pin names "A", "B", "C", "D", "E", "F" and "Z" expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the ORCA primitives ORCALUT4, ORCALUT5 or ORCALUT6. These primitives only have pins named "A", "B", "C", "D", "E", "F" and "Z". Further, ORCALUT4 cannot have pins "E" and "F", and ORCALUT5 cannot have pin "F". u88#[FPGA-EDFN-O2A-5 Message Cell '%1' has '%3' input pins which exceeds the maximum allowed on design '%2'. Description The cell is a LUT of type ORCALUT4, ORCALUT5 or ORCALUT6. ORCALUT4 can have only 4 input pins, ORCALUT5 can have only 5 input pins and ORCALUT6 can have only 6 input pins. Please make sure that the cell is of the correct type. $FPGA-EDFN-O2A-6 Message Cell '%1' has an incorrect lut_function property - the EQN string is of zero length. Description The cell has a lut_function property attached to it. This property describes the logic function of the cell and is a Boolean equation describing the function of the output of the cell in terms of its inputs. For this particular cell, this property string is empty. Please ensure that the EDIF input file has been generated correctly. ~88%FPGA-EDFN-XLU-10 Message Duplicate instance of property 'lut_function' on cell '%1'. Description The property 'lut_function' was found to be duplicated on cell '%1'. Please ensure that the application used to generate this property is functioning properly. &FPGA-EDFN-XLU-11 Message Duplicate instance of property 'INIT' on cell '%1'. Description The property 'INIT' was found to be duplicated on cell '%1'. Please ensure that the application used to generate this property is functioning properly. 88'BFPGA-EDFN-XLU-1 Message Incorrect variable name '%1' encountered while parsing equation string '%2'. Description The equation string for a Xilinx LUT is expected to be specified in terms of variables I0 through I3 only. The EDIF translator has encountered a different variable name and has hence generated this error. (FPGA-EDFN-XLU-2 Message While parsing equation '%1' : '%2'. Description The equation string for a Xilinx LUT is expected to be specified using the EQN syntax. Please make sure that your input EDIF file uses this syntax. 88)6FPGA-EDFN-XLU-3 Message Cell '%1' has incorrect design name '%2', LUT expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the Xilinx primitive LUT. The cell is not an instantiation of one of these designs and hence the error. *OFPGA-EDFN-XLU-4 Message Cell '%1' has incorrect pin name '%2'. Only pin names "I0", "I1", "I2", "I3", "LO" and "O" expected. Description The cell has an edif property "lut_function" attached to it. This property is to be attached only to cells of the Altera primitive LUT. This has pins named "I0", "I1", "I2", "I3", "LO" and "O". 88+FPGA-EDFN-XLU-5 Message Cell '%1' has '%3' input pins which exceeds the maximum allowed on design '%2'. Description The cell is a LUT and can have upto 4 input pins. Please make sure that the cell is of the correct type. ,FPGA-EDFN-XLU-6 Message Cell '%1' has an incorrect lut_function property - the EQN string is of zero length. Description The cell has a lut_function property attached to it. This property describes the logic function of the cell and is a Boolean equation describing the function of the output of the cell in terms of its inputs. For this particular cell, this property string is empty. Please ensure that the EDIF input file has been generated correctly. 88-!TFPGA-EDFN-XLU-7 Message VCC or GND cell from schematic netlist encountered. Pin '%2' of cell '%1' has been renamed to '%3'. Description The cell is either a VCC or GND cell. Xilinx schematic libraries have pin names for these cells that are different than HDL libraries. VCC pins will be renamed to P. GROUND pins will be renamed to G. .0FPGA-EDFN-XLU-8 Message '%2' defined inconsistently on cell '%1'. Description The cell '%1' has two or more of '%2', '%3' and '%4' properties. Unfortunately, these are not all consistent. Please ensure that the application used to generate these properties is functioning properly. 88/?FPGA-EDFN-XLU-9 Message Duplicate instance of property 'EQN' on cell '%1'. Description The property 'EQN' was found to be duplicated on cell '%1'. Please ensure that the application used to generate this property is functioning properly. 0NFPGA-ELABORATE-HDL-2 Message Elaboration of design '%1' failed (check reported errors). Description This is a summary information, indicating that some designs could not be elaborated correctly during hierarchical linking and elaboration. Following this message, there will be one section of messages for each elaborated design where detailed elaboration error messages can be found. 81]FPGA-ELABORATE-HDL-3 Message Elaboration of design '%1' done (check reported warnings). Description This is a summary information, indicating that some warning messages had been produced while elaborating some designs during hierarchical linking and elaboration. Following this message, there will be one section of messages for each elaborated design where detailed elaboration warning messages can be found. 2lFPGA-EXPORT-2 Message Unable to open file '%1' for writing. Description The file could not be opened for writing. Check the file permissions and close any programs which current have this file opened and locked. ?|83{SFPGA-EXPORT-3 Message Writing file '%1'. Description Writing the file to disk. 4rFPGA-EXTERNAL-edif-read-unknown Message %1 (%2) Description No further description is available at this time. 885FFPGA-EXTERNAL-edif2hnl-1 Message Cannot rename bus %2 to %3 on design %1. Description FPGA Express/Compiler II is trying to remove the range components of a bus. But the new name collide with an existing bus name. In this case, FPGA Express/Compiler II will leave the bus name unchanged. The potential problem with leaving the range component in the bus name is that linking this design into other designs may fail because of name mismatch. If you see this warning, we suggest you rename the bus on the design such that the bus names without the range components don't collide. 6IFPGA-EXTERNAL-edif2hnl-2 Message Cannot rename bus %3 to %4 on cell %1/%2. Description FPGA Express/CompilerII is trying to remove the range components of a bus. But the new name collide with an existing bus name. In this case, FPGA Express/CompilerII will leave the bus name unchanged. The potential problem with leaving the range component in the bus name is that linking this cell to its referenced design may fail because of name mismatch. If you see this warning, we suggest you rename the bus on the design such that the bus names without the range components don't collide. 887+FPGA-EXTERNAL-edif2hnl-3 Message %1: rename bus %2 to %3. Description If a bus name contains the range components, e.g., DATAIN[4:0], FPGA Express/CompilerII will convert it to DATAIN. This allows the linking of an edif design to other hdl designs in which the bus is called for example DATAIN. 8.FPGA-EXTERNAL-edif2hnl-4 Message %1/%2: rename bus %3 to %4. Description If a bus name contains the range components, e.g., DATAIN[4:0], FPGA Express/CompilerII will convert it to DATAIN. This allows the linking of an edif design to other hdl designs in which the bus is called for example DATAIN. 8894FPGA-GNRC-PMAP-0 Message Skipping pad mapping on port '%1' because there are pads connected to it already. Description When a port is already connected to some IO pads, pad mapping will not be preformed on that port. Also, no checking is made on the validity of the pad cell configuration for that port. :FPGA-GNRC-PMAP-1 Message No %1 pad in the target. Port %2 is unmapped. Description If a port needs particular pad cell that doesn't exist in the target library, the port is left unmapped. Typically, this means that the vendor's tool has the pad mapping capability and can perform the task with more accurate information. Please check with your FPGA/CPLD vendor for more information. 88;FPGA-GNRC-SMAP-0 Message Sequential element '%1' cannot be mapped to any of the sequential primitives in the target technology. Description A sequential element cannot be mapped to any of the sequential primitives in the target technology. This usually means that asynchronous set and/or clear are not supported in the target device. You probably need to change your circuit description. <FPGA-GSRMAP-10 Message Design has multiple GSR marker cells. All these cells have been deleted and any connections to the pins on these cells are permanently lost. Description The target technology allows only a single GSR marker cell. Your design contains multiple marker cells. FPGA Express/CompilerII deletes all these markers and then inserts a single marker to mark the GSR net, if such a net exists. Some target technologies (For example, Xilinx) have multiple pins on the GSR marker cell. When FPGA Express/CompilerII deletes the marker cell, the connections to all pins on the GSR cell are lost. If you intended to use some of these pins (eg., GTS), then your intention will not be realized. You need to ensure that there exists only a single GSR marker cell to prevent its deletion. 88=FPGA-GSRMAP-11 Message Net '%1' permanently sets/resets all the sequential devices in the design. Description GSR inferencing has detected that the net sets/resets all the sequential devices when it is set to logic 1 as well as when it is set to logic 0. As a result all sequential devices are permanently set/reset. A possible cause for this behavior is incorrect connection of a GSR marker cell. Please note that some FPGA vendors have GSR markers which implicitly invert the phase of the signal. It is highly recommended that the user explicitly specify set/reset behavior for all flip-flops instead of using GSR marker cells and rely on FPGA Express/CompilerII' built in optimization to automatically detect the presence of GSR signals in the design. >"?ing resources that it would have otherwise required is now free to be used for routing other critical signals. This design has an unlinked cell. The unlinked cell may contain sequential elements which may or may not be reset simultaneously with other sequential elements in the design. By default, the GSR mapper makes the conservative assumption that the unlinked cell has sequential elements which are not asynchronously set / reset by a GSR signal. However, since the user has explicitly requested that GSR mapper ignore the unlinked cell, GSR mapper has proceeded with the GSR optimization with the assumption that the unlinked cell(s) will not contain any sequential devices. If the unlinked cell in the design does contain unlinked cell(s), incorrect logic will be generated. I8?">FPGA-GSRMAP-12 Message GSR optimization has ignored unlinked cell '%1' in the design at the user's request. This could result in incorrect logic if the unlinked cell contains sequential devices. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose rout@4Anet has not been marked as GSR net because it connected to only those registers which are listed above, and not connected to some other registers. I8A4@FPGA-GSRMAP-13 Message Net "%1" sets/resets "%3". Net "!%1" sets/resets "%2". Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have otherwise required is now free to be used for routing other critical signals. This BECt/reset by the nets listed. But these nets are not inferred as GSR because they are either not connected to some cells or some of the cells are set/reset by positive phase and some by negative phase. I8CEBFPGA-GSRMAP-14 Message FlipFlops/Latches "%1" are set/reset by "%2". Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have otherwise required is now free to be used for routing other critical signals. The cell is seDVE_ is no net connected to the set/reset pin of this cell, therefore a gsr cannot be inferred. I8EVDFPGA-GSRMAP-16 Message No net is connected to the set/reset pin of Cell '%1'. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have otherwise required is now free to be used for routing other critical signals. ThereFgFPGA-GSRMAP-1 Message The pin '%1' had an implicit connection to the on-chip global set / reset (GSR) net. This connection has been made explicit. Description GSR optimization has detected the presence of a GSR net in your design. This happens if one or more of the following happen: a) There exists a net that sets or resets all the sequential elements in your design. b) There exists a GSR marker cell in your design identifying a net to be a GSR net. If case (b) occurs, then the net marked as GSR may not have explicit connections to the set or reset pin of all sequential elements in the design. The GSR mapper explicitly connects the marked net to the set/reset pins. 88GvFPGA-GSRMAP-2 Message Cell INIT attributes are inconsistent. Description Xilinx architectures allow a sequential element to be either preset-able or reset-able, but not both. The global set reset (GSR) mapper performs a check to ascertain that all sequential devices in the design meet this requirement. Specifically, a) A sequential element with an INIT value of "R" can only have an asynchronous clear pin. It must not have an asynchronous set pin. b) A sequential element with an INIT value of "S" can only have an asynchronous set pin. It must not have an asynchronous clear pin. If the design has a sequential element which violates either of the above two conditions, this error message is generated. HFPGA-GSRMAP-3 Message The design has multiple global set / reset (GSR) nets. Description The target technology allows only one GSR net per chip. The GSR mapper has detected that this design has more than one GSR. This could happen if one or more of the following has occurred: a) The design has more than one GSR marker blocks located on different nets. b) The design has a net that asynchronously sets or resets all sequential devices AND has a GSR marker block on a separate net. c) Some sequential elements have attributes (eg. INIT) that imply a connection that conflicts with the connections to the net marked by the GSR marker block. Please ensure that the GSR marker block is being used in a consistent manner before reading in the design into FPGA Express/CompilerII. 88IWFPGA-GSRMAP-4 Message Global set / reset (GSR) marker block is not used correctly. Description The target technology allows only one GSR net per chip. The GSR mapper has detected that this design has multiple GSR marker blocks located on different nets. Please ensure that all GSR marker blocks are on the same (logically connected) net. JKVotherwise required is now free to be used for routing other critical signals. This message warns you that your design does NOT have a GSR signal. If you feel that all the sequential elements in your design can be asynchronously set/reset simultaneously by a single signal, please make sure that your HDL description captures your intent. I8KJFPGA-GSRMAP-5 Message No global set / reset (GSR) net could be used in the design because there is not a unique net that sets or resets all the sequential cells. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have LMrms you that your design has such a GSR signal. No further action is required on your part -- this signal will be automatically assigned to on-chip dedicated GSR routing. I8MLFPGA-GSRMAP-6 Message Net '%1' is a global set / reset (GSR) net. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have otherwise required is now free to be used for routing other critical signals. This message infoNOo not support the GSR marker methodology. Hence it is not possible for FPGA Express/CompilerII to automatically assign the GSR signal in your design to on-chip GSR dedicated resources. Please refer to the target technology vendor's GSR methodology guide to perform the steps required to assign the GSR signal to on-chip GSR dedicated resources. If you do not wish to perform these vendor specific steps, then the GSR signal will be routed using the general purpose resources instead of the dedicated resources. This could impact the overall performance of the design because: a) The GSR signal will now have larger routing delay as compared to the situation when it would have used dedicated routing. b) The overall routing congestion on the chip increases since the GSR signal (which connects to every sequential element in your design) is using up some of the general purpose routing resource. I8ONFPGA-GSRMAP-7 Message Net '%1' is a global set / reset (GSR) net. If you wish to use the on-chip GSR resources to route this net, please refer to the application note on GSR methodology. If you do not wish to use the on-chip GSR resources, then no further action is required on your part -- the net will be routed using the general purpose routing resources. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. Some target technologies have backend place and route tools that let the front end synthesis tool place a technology specific GSR marker block on the GSR signal. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. However, for the target technology that you have chosen, the backend place and route tools dPQee to be used for routing other critical signals. This design has an unlinked cell. The unlinked cell may contain sequential elements which may or may not be reset simultaneously with other sequential elements in the design. The GSR mapper makes the conservative assumption that the unlinked cell has sequential elements which are not asynchronously set / reset by a GSR signal, and generates this warning. 98QPFPGA-GSRMAP-8 Message No global set / reset (GSR) net could be used in the design because the design contains the unlinked cell '%1'. Description The global set / reset (GSR) net is a signal that asynchronously sets or resets all the sequential elements in the design. FPGA Express/CompilerII has built in optimization to automatically detect the presence of such signals in your design. This signal is then marked by placing a target technology specific GSR marker block on it. The backend place and route tools use this marker to identify the GSR signal and then route this signal using dedicated routing. Automatic detection of GSR thereby helps improve the performance of your design in two ways: a) By assigning the GSR signal to dedicated routing, the signal has very little routing delay as compared to routing it through the general routing resources. b) By assigning the GSR signal to dedicated routing, the general purpose routing resources that it would have otherwise required is now frRFPGA-GSRMAP-9 Message The net '%1' had an implicit connection to the on-chip global set / reset (GSR) net. This connection has been made explicit. Description Implicit connections to the on-chip global set / reset net can happen due to either a) Presence of a net connection to the global set /reset pins of sequential elements in your design. b) Presence of a target technology specific GSR marker cell in your design. The net driving the GSR related port of this marker cell is treated as the GSR net. This GSR net has been explicitly connected to the set/reset pins of every sequential element in the design. If this is not the intended behavior, please remove the cause (connection to the global set / reset pin or/and the instantiated GSR marker cell) from the design. Note that the presence of implicit GSR connections in your design is not an FPGA Express/CompilerII recommended methodology. Specifying set/reset behavior explicitly in HDL is the preferred methodology. @|8S-FPGA-IMPLEMENT-WRONG-PART Message '%1' is not a valid part for '%2' Description Chip has been implemented with a part that is obsolete. It was likely created with a previous version of FPGA Express/CompilerII. The chip cannot be updated, however, you can view the chip and export its constraints. TRFPGA-INVALID-CHIP-1 Message The target, device, or speed grade for the chip '%1' does not exist in this installation of FPGA Express/CompilerII. Description The target, device, or speed grade for the chip either does not exist in the current version of FPGA Express/CompilerII or was not selected during installation of the software. 98UFPGA-LINK-12 Message Pin group number %1 of cell '%2' and design '%3' have different sizes. Not linked. Description When using position-based binding, the pins on a cell and on a design are referred to by their position numbers in the input description, starting from number 0. The corresponding pin group on the cell and on the design must have the same size, or linking will fail. V.>FPGA-LINK-14 Message Positional binding is not allowed when linking the cell '%1' to the XNF design '%2'. Description When referencing a XNF primitive cell, the binding has to be name-based or linking will fail. The for exact names of pins on a XNF primitive cell, please refer to Xilinx Unified Library Databook. I8W=FPGA-LINK-15 Message The bus '%3' of the cell '%1' cannot be found in the design '%2'. Description The linking of a cell to a XNF design is strictly name-based. Each pin groups (buses) of the cell must have a corresponding port groups in the design, specified at the input description. The port group of the design is created from the net group of the same name. The net group is a collection of nets having the specified port name as their base name with bus extension. For example, if the referenced port is FM_CTRL, then nets FM_CTRL_0, FM_CTRL_1, FM_CTRL_2 are grouped and connected to a newly created port FM_CTRL prior to the actual linking. Notice that the same nets can also be named FM_CTRL<0, FM_CTRL<1, and FM_CTRL<2, or some other bus-naming convention. The bug-naming format used in identifying the net groups is specified in the tool option page at the time the XNF design is loaded. XLFPGA-LINK-16 Message The width of the bus '%3' of the cell '%1' is different from the width of the bus '%3' of the design '%2'. Description The width of the pin-bus is different from the width of the port-bus. One possible cause is that the port-bus naming style is not correctly specified when the XNF design was loaded. To correct the problem, set the appropriate bus naming style in the option page and reload the XNF design. I8Y[FPGA-LINK-17 Message The pin '%3' of the cell '%1' does not have an associated signal in the XNF design '%2'. Description Unlike VHDL and Verilog, XNF designs do not have to have ports. In FPGA Express/CompilerII, the port name of a XNF design is interpreted as signal (net) name. The signal name is identified by a base name and a bus-position extension. For example, the base name of signal FM_CTRL<2 is FM_CTRL and 2 is the position of the signal in the bus FM_CTRL. One possible cause of this error could be incorrect specification of bus naming style. To correct this, set the correct bus naming style in the tools option page, reload the XNF design, and update or create a new implementation. ZjFPGA-LINK-18 Message The cell '%1' referencing the design '%2' has been left unlinked to avoid creating cyclic design hierarchy. Description The cell is left unlinked because linking it with the referenced design would have created cycles in the design hierarchy. One possible cause of this error is that the design project contains multiple designs of the same name differing only in cases. If these designs come from case-insensitive input descriptions such VHDL, linker may not have enough information to make the correct choices. 8[y<FPGA-LINK-19 Message Positional binding is not allowed when linking the cell '%1' to the target primitive design '%2'. Description When referencing a target primitive cell, the binding has to be name-based or linking will fail. Please consult your vendor primitive library book for the exact naming of the pins. \FPGA-LINK-1 Message Linking aborted by user. Description This message is generated that the user aborted creating implementation by clicking on the STOP button. @|8]FPGA-LINK-2 Message Cannot link cell '%2' to its reference design '%1'. Description This message indicates that either the referenced design cannot not be found, or the referenced design is found but cannot be properly linked to the cell due to mismatched pins on the cell and the referenced design. The the later case, there are more detailed messages preceding this message to indicate the exact reasons for the linking failure. ^FPGA-LINK-3 Message Cell '%2' has been linked to design '%3', because design '%1' could not be found. Description This is a warning message indicating that the design with the exact referenced name could not be found, but another design with case-mismatched name was found and used. This message only appears when both the referencing cell and the referenced design come from case-sensitive input descriptions such Verilog. A|8_@FPGA-LINK-4 Message Cell '%3' is being linked to design '%1' instead of design '%2'. Description This message indicates that there are multiple designs which can be used to link to the cell and the tool had to arbitrarily pick one. Usually, these designs all come from case-insensitive input descriptions such VHDL. `FPGA-LINK-5 Message The cell '%1' and the design '%2' do not have the same number of pin / port buses. Not linked. Description The pins of a cell and ports of a design are grouped into buses (sometime called bundles). For a cell to link to a design, the number of pin-buses and the port-buses have to be the same. Furthermore, the number of pins and the number ports in the corresponding pin-bus and port-bus must also be the same. Otherwise, linking will fail. A|8aFPGA-LINK-6 Message The pin '%1' of the cell '%2' has a direction that is different from the direction of the port '%3' of the design '%4'. Not linked. Description For some input description, the direction of the pins on a cell can be specified, such as VHDL. When the direction of cell-pins are specified, linker will check the direction against the corresponding port directions and issue an error message if there is an inconsistency. b\FPGA-LINK-7 Message The pin '%1' of '%2' has no corresponding port on the design '%3'. Not linked. Description The binding of pins to ports can either be name-based or position-based. Almost all input descriptions support name-based binding, e.g., VHDL and Verilog. Some input description languages also allow position-based binding, e.g., Verilog. In name-based binding, the corresponding pin names and port names are completely specified in the input description and are verified and enforced by the tool during linking. Linking will fail when the required port name cannot be found on the design. !98cFPGA-LINK-9 Message Cell '%1' will be treated as blackbox. Description This message is to alert the user that a cell is not linked due to some problems and will be left unlinked and treated as blackbox through out the optimization process. It is then the user's responsibility to combine the netlist produced by FPGA Express/CompilerII with the appropriate implementation of the linked cell in the vendor implementation tools. d FPGA-ORCA3C-PADMAP-1 Message Port '%1' is connected to a FPSC core pin having inbuilt pads - no pad cells inserted at this port Description Some of the pins on the FPSC core cell have primitive I/O interface - no additional pad cell is to be inserted at the nets on such pins. Please check the Lucent FPSC related documentation for further details on such pins and the type of inbuilt pads at these pins. 098e FPGA-ORCA3C-PADMAP-2 Message The FPSC pin '%1' is incorrectly connected. Description FPGA Express/CompilerII' FPSC specific optimizer has detected that there are extra pins on the net connected to the FPSC core pin '%1'. Certain pins on the FPSC core have inbuilt pads. Such pins can connect only to top level port pins. They must not be connected to other cells in the design. Your design has such incorrect connections. Please check the Lucent FPSC data sheets for proper usage of the FPSC core cell. f FPGA-PADMAP-1 Message Existing pad cell '%1' is connected to the port '%2' - no pads cells inserted at this port. Description The pad mapping optimization step has detected that the named port has an instantiated pad cell attached to the port's net. No other pads will be mapped at this port. If the pads at this port are the desired type then this message can be ignored. If the pads are not desired either remove the pad cell instances from the design description or set the check box keep-pads to remove all pads in the design. 298g- FPGA-PADMAP-2 Message Port '%1' has no net attached to it - no pad cells inserted at this port. Description The pad mapping optimization step assumes that if a port in the top design does not have a net attached to it that no pad cells are required. h< iFPGA-PADMAP-3 Message The pad mapping optimization can not determine the type of pad to insert at the port '%1'. Please see the extended error message for more details. Description The pad mapping optimization program cannot determine the type of pad to be inserted at this port. Examine the HDL description or netlist and determine what other ports, internal three-state cells and unlinked black-box cell pins are attached to this port's net. The following cases can cause this error to occur. Each case includes a short description of what to do next. If none of these cases applies to this design, hand instantiate pad cells at this port, making sure that "Keep User Pads" is selected in the Create Implementation dialog box. a) A single three-state cell drives multiple output or inout ports. What to do - If only one of the ports must be three-stated and if all other output and inout ports on this net can be defined as output pads, edit the Ports constraint spreadsheet to define the othe8i< hjr pads as outputs. Open the design implementation and select the Ports tab. For each port to be defined as an output pad, double-click the cell in the Pad column to open the "Define Pad" dialog box. Select the pad type "Output." If more than one of the ports must be three-stated, modify the HDL or net-list description to duplicate the three-state cell for each of the three-state ports. The pad mapping optimization will not automatically duplicate three-stated cells for this purpose. b) Multiple three-state cells driving a single output or inout port. What to do - If an output or inout port does not require a three-state pad, edit the Ports constraint spreadsheet to define the pads as outputs. Open the design implementation and select the Ports tab. For each port to be defined as an output pad, double-click the cell in the Pad column to open the "Define Pad" dialog box. Select the pad type "Output." If an output or inout port requires a three-state pad then you must modify the HDL oj< ikr net-list description to create a single three-state cell driving this output or inout port. c) Multiple three-state cells drive multiple output or inout ports. What to do - Define the other port pad types as "Output" as in the previous cases. d) The port net is attached to an unlinked cell and the pin of the unlinked cell has no direction specified in the HDL or netlist description. The pad mapping optimization program automatically defines a pin with an unknown direction as a three-state pin. The port is considered to be three-state because of the black-box's three-state pin on the port's net. An error occurs because there is no three-state to bring into the pad cell. What to do - If the black box is instantiated in a VHDL file, then define the port directions for each of the pins of the black-box in the component declaration. If the black box is instantiated in a Verilog or netlist file, hand-instantiate each pad cell. e) The port is defined as "output" or "inout" and is alway598k< js driven to high impedance (Z) condition. What to do - In the HDL description, for each port assigned to a constant high impedance (Z) remove the assignment statement. f) The port has instantiated pads, but "Keep User Pads" is not selected in the Create Implementation dialog box. In this case, all manually instantiated pads are replaced by generic logic and remapped. In the HDL or netlist descriptions, determine which additional ports would be connected to this port's net assuming that the instantiated input and output buffers were replaced by a net. Then, using the ports directly connected to this port and those ports which are indirectly connected through input and output buffers, use the previous cases to find an applicable solution. lX OFPGA-PADMAP-4 Message Register optimization for pad mapping the input component of port '%1' has been disabled. Description The pad mapping register optimization has disabled the register optimization for this port. This means that pad mapping will not make an attempt to detect and pull a register into an input pad at this port. 998mg FPGA-PADMAP-5 Message Clock-enable pins '%2' and '%3' found on the input and output registers at port '%1' are conflicting: either they have different inversions or are tied to different nets. Description This technology requires that the input and output register pads instantiated at the same port must share the same clock-enable net. Pad mapping has detected that the clock-enable nets of two registers which could be mapped as input and output pads at this port have different clock-enable nets. nv FPGA-PADMAP-6 Message The I/O pad cells at port '%1' are configured incorrectly. Description Pad mapping has detected that the instantiated pads at this port are not correct for this technology. This may be caused by incorrect attribute values (i.e. slew, input voltages, etc.) or by illegal connection of at the port's net (i.e. a non-pad cell is on the net in addition to the pad cells). Please check the pad cells instantiated at this port and modify the cells or attributes which define the pad configuration at this port. A|8o uFPGA-PLACE-AND-ROUTE-ERROR Message %1 Description Please refer %2 documentation for extended help on this topic. p xFPGA-PLACE-AND-ROUTE-WARNING Message %1. Description Please refer %2 documentation for extended help on this topic. @98q FPGA-SEQMAP-1 Message Sequential mapping has detected that the cell '%1' implements an RS-latch. The target architecture library does not contain an RS latch. Description The named cell is an RS-latch which cannot be implemented efficiently in the target technology. Modify your HDL description to implement to a register which can be efficiently mapped in your target technology. r FPGA-SEQMAP-2 Message Sequential mapping has detected that the cell '%1' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. Description The named sequential cell appears to use both asynchronous set and asynchronous clear. The target architecture does not support this type of register. Please modify your HDL code to remove one of the asynchronous assignments (possibly making it a synchronous assignment if it is appropriate). P98s FPGA-SEQMAP-3 Message Sequential mapping has detected that the cell '%1' uses the 'QN' pin which cannot be mapped on the target architecture. Description The QN pin of the sequential is driving logic in design and this pin is not equal to the inverted value of the Q pin on that same sequential cell. This occurs when register has been hand instantiated and this register has been described to have special (non-inverting) behavior at the Q and QN pins when both asynchronous clear and asynchronous set are active. The target technology does implement this behavior in its registers and thus this cell is not mapped. Please modify the net-list or HDL description to use a sequential cell which does not have this behavior. t FPGA-SEQMAP-4 Message The sequential cell '%1' has been implemented using a combinational feedback loop. Description The named sequential cell is a latch. A latch is not implemented as gate in this technology. It has been implemented using a combinational feedback loop circuit, which can cause serious timing problems in your design. Review your design description and verify that a latch is really intended. Latches are infered from an HDL when a switch or if-then-else block does not specify an assignment to the variable under all conditions - a missing case in a case-statment block or no "else" part in an if-then-else block. If combinational logic is intended, then modify the HDL description to assign the variable under the missing cases. ^98u 3FPGA-SEQMAP-5 Message The sequential cell '%1' has been implemented using the CLR and PRE pins of a flip-flop. Description The named sequential cell is a latch. However, there is no latch in the target technology. Therefore, the sequential cell has been implemented using additional combinational logic fed to the CLR and PRE pins of a flip-flop. This can cause serious timing problems in your design. Review your design description and verify that a latch is really intended. Latches are infered from an HDL when a switch or if-then-else block does not specify an assignment to the variable under all conditions - a missing case in a case-statment block or no "else" part in an if-then-else block. If combinational logic is intended, then modify the HDL description to assign the variable under the missing cases. v FPGA-SEQMAP-6 Message Sequential mapping has detected that the cell '%1' uses the asynchronous set which is not supported by this technology. Description The named sequential cell uses asynchronous set and the target technology does not efficiently implement this kind of behavior in its registers. Please modify the HDL or net-list description to eliminate the asynchronous set signal. o98w FPGA-SEQMAP-7 Message Sequential mapping has detected that the cell '%1' uses both asynchronous set and reset and the behavior which occurs when both set and reset are enabled is not supported by this technology. Description The named sequential cell uses asynchronous set and asynchronous reset. The behavior when both asynchronous signals are enabled (i.e. the Q pin goes to unknown, or it toggles) cannot be efficiently implemented by the target technology. Please modify the HDL or net-list description to infer or instantiate registers which have asynchronous behavior which can be efficiently implemented in the target technology. x !eFPGA-TC-0 Message The port '%1' will be absent in the subgroup created. Description You are importing constraints from a design that does not exactly correspond to the current design. As a result, there is a mis-match. In particular, the port '%1' is not in the current design and is being dropped from the subgroup defined in the imported constraints. t98y!fFPGA-TC-1 Message The cell '%1' will be absent int the subgroup created. Description You are importing constraints from a design that does not exactly correspond to the current design. As a result, there is a mis-match. In particular, the cell '%1' is not in the current design and is being dropped from the subgroup defined in the imported constraints. z*!DFPGA-TC-2 Message The subgroup '%1' could not be created. Description You are importing constraints set on a design that does not exactly correspond to the current design. As a result, there is a mis-match and it is not possible to create the subgroup '%1'. Please verify that you are importing the correct constraints. x98{9!BFPGA-TC-3 Message The subpath '%1' could not be created. Description You are importing constraints set on a design that does not exactly correspond to the current design. As a result, there is a mis-match and it is not possible to create the subpath '%1'. Please verify that you are importing the correct constraints. |H!FPGA-TC-4 Message The subgroup '%1' could not be created due to absence of its full group. Description You are importing constraints set on a design that does not exactly correspond to the current design. As a result, there is a mis-match and it is not possible to create the subgroup '%1' since its full group is not present in the current design. Please verify that you are importing the correct constraints. 98}W!FFPGA-TECH-1 Message The port '%1' is not used in the design and will not be included in the exported optimized net-list. Description The named port has no net attached to it or the net has no cells in the design connected to it. The port will not be included in the optimized net-list exported by FPGA Express/CompilerII. ~f!FPGA-alt-acf-0 Message %1 Description This is the error message produced while parsing the ACF file. Whenever there is an error in parsing the ACF file, the contents of the file is discarded and a new ACF is created. 98u!FPGA-alt-acf-1 Message cannot create '%1' Description Cannot create the specified file. This usually means that the specified directory does not exist, or the user has no write permission in the directory, or the file already exists but is not writeable by the current user. !FPGA-alt-acf-2 Message cannot read '%1' Description Cannot read the specified ACF file. This usually means that the ACF file does not exist or the current user has no read permission on the file. 98!FPGA-alt-acf-3 Message error while reading '%1'. Description Cannot parse the specified ACF file. There is usually another message preceding this one to indicate the reason. !bFPGA-dm-hdlc-information Message %1 Description General information produced by HDL Compiler. 98!FPGA-dm-hdlc-read-magic Message Reading control file `%1' Description This message indicates that FPGA Express/CompilerII is using the control file to set certain tool options. The control file is a binary file and can and should only be obtained through FPGA Express/CompilerII support staff. The control file obtained from FPGA Express/CompilerII support staff is constructed to alter the tool behavior for a specific project for specific reasons and should not be copied to any other project. !gFPGA-dm-hdlc-unknown Message %1 (%2) Description No further description is available at this time. 98!FPGA-lct-1 Message Library '%1' does not contain any design named '%2'. Description Your design requires a primitive cell not in the target architecture's library. Please make sure that you are selecting the right architecture family for your design. !CFPGA-lpm-0 Message The LPM design linked to cell instance '%1' has a parameter '%2' that is not an LPM parameter. Description The design linked to the named cell instance has a parameter which does not begin with the prefix LPM. If this design is an LPM design then all the parameters should begin with the prefix LPM. 98!(FPGA-lpm-1 Message The type of the generic parameter '%2' on the LPM design linked to cell instance '%1' has an unsupported type. Description The type of the parameter must be either integer, natural, positive or string. Please modify the design entity description to use one of these types. !FPGA-pmap-17 Message Ignoring '%1' attribute on port '%2'. Description The target technology requires that the pad location be specified if the DIN/DOUT attributes are to be considered. Since the port does not have a pad location specified, the DIN/DOUT attribute on the port is ignored. If you wish the DIN/DOUT to be taken into consideration, please enter a pad location for this port. 98 "YFPGA-pmap-18 Message The port type of port '%1' is unknown. An output pad will be inserted. Description Pad mapping will insert an output pad at the named port. If the net attached to the port is driven by three-state drivers or is connected to multiple inout ports, then the optimized circuit may not match simulation results at this port. "BFPGA-tmap-4 Message %1 contains internal three-state logic that is not supported by the chosen architecture. Description The chosen architecture does not support internal three-state logic. The only three-state logic supported is on the output pads. Remove the internal three-state logic and re-synthesize the design. >:8)"mFPGA-ucf-1 Message Cannot translate the waveform of clock '%1' to UCF constraint. Description There is a restriction in UCF that one of the clock edges have to be zero. FPGA Express/CompilerII is unable to translate a clock with non-zero rising and falling edges to the UCF constraint. If the design contains only one clock, then re-specify the clock waveform such that either the rising or the falling edge of the clock is at zero. If you have multiple clocks and the clocks have a common edge, you should use that common edge as a common reference point of time zero and describe the clock waveforms accordingly. If your circuit does have multiple clocks with non-overlapping edges, you can ignore this warning. FPGA Express/CompilerII will write out correct timing constraints to M1 in the form of maxdelay's. However, you may experience some long running time in M1. :"HDL-100 Message %1 Description This error occurs if the type of an aggregate is an unconstrained type such as bit_vector. What Next Modify your HDL description so that the type of the aggregate is a constrained type. B|8K"HDL-101 Message %1 Description This error occurs if you attempt to do a slice or index operation on an unconstrained array (such as bit_vector). What Next Modify your HDL description to make the array constrained. \"HDL-103 Message %1 Description This warning occurs if (in VHDL) the return statement for a function does not return a value or (in Verilog) a function does not return a value by assigning a value to a variable that has the same name as the function. What Next Modify your HDL description to ensure that the function returns a value. If you do not need to return a value, use a procedure (in VHDL) or a task (in Verilog). B|8m"HDL-104 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. ~"HDL-105 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. D:8"HDL-106 Message %1 Description This error occurs when values are assigned to some but not all bits of a variable whose type is a range. This usually happens when the variable is converted into an array and some bits of the array are assigned values. If this array is now converted back into a range and used, this error will occur. What Next Modify your HDL description so that either all or none of the bits are driven. "ss; toggle <= temp; -- OK end; Example Message Error: Tried to use a synchronized value in routine test line 14 in file 't.v' (HDL-107) D:8"HDL-107 Message %1 Description This error occurs when you assign a value to a variable inside an "if(clock'event)" block, and then attempt to read it after the "end if" statement. In the following example, temp is improperly read: entity test is port(clock: in bit; toggle: out bit); end; architecture a of test is begin process (clock, toggle) variable temp: bit; begin if(clock'event and clock = '1') then temp := not temp; end if; toggle <= temp; -- ERROR end process; end; What Next Move the statement that reads the value into the "if" block, or change the variable into a signal and read the signal outside the process. The following example shows how to move read of temp outside the process of the previous example: entity test is port(clock: in bit; toggle: out bit); end; architecture a of test is signal temp: bit; begin process (clock, toggle) begin if(clock'event and clock = '1') then temp <= not temp; end if; end proce"HDL-108 Message %1 Description This is a non-fatal internal error. What Next Contact you Synopsys support representative. Lָ8" if(clock'event and clock = '0') then z2 <= a; end if; end process; end; Example Message Error: This use of clock edge specification not supported in routine test line 13 in file 't.v' (HDL-109) "HDL-109 Message %1 Description This error occurs if you use more than one "if clock'event" expression in a process or if you embed the 'event expression inside a subprogram or loop. The following example shows a positive- and negative-edge trigger in the same process. entity test is port(clock, a: in bit; z1, z2: out bit); end; architecture a of test is begin process (clock) begin if(clock'event and clock = '1') then z1 <= a; end if; if(clock'event and clock = '0') then -- ERROR z2 <= a; end if; end process; end; What Next Restructure your code to have a single "if clock'event" construct at the start of the process. The previous example can be fixed by splitting the process into two processes. entity test is port(clock, a: in bit; z1, z2: out bit); end; architecture a of test is begin process (clock) begin if(clock'event and clock = '1') then z1 <= a; end if; end process; process (clock) begin G:8##HDL-10 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. 4# e an "if" statement to insure that either that the asynchronous or synchronous assignments fire in any execution of the process. Make sure that the condition controlling this "if" (the asynchronous reset condition) is level sensitive, not edge sensitive. The following examples show how to fix the previous code: entity test is port(clock, a, b, reset: in bit; z: out bit); end; architecture a of test is begin process (clock, a, b, reset) begin if(reset = '1') then z <= b; -- OK, since the if clock'event won't fire if we get here elsif(clock'event and clock = '1') then z <= a; end if; end process; end; Example Message Error: Illegal assignment to 'z'. It depends on a non-edge in routine test line 12 in file 't.v' (HDL-110) G:84#The behavior of these examples cannot be synthesized by the HDL Compiler. Notice that "z" behaves like a D flip-flop just after each clock event, but whenever a positive or negative transition is on either "a" or "b", the value is asynchronously reset to "b". A variable can receive both asynchronous and synchronous assignments, but the asynchronous assignments must take precedence. That is, there must be a Boolean condition that enables the asynchronous part and disables the synchronous part. The following example is still illegal since the asynchronous enable condition (reset) does not override the synchronous assignments: entity test is port(clock, a, b, reset: in bit; z: out bit); end; architecture a of test is begin process (clock, a, b, reset) begin if(reset = '1') then z <= b; -- ERROR, Since the if clock'event is not disabled by reset end if; if(clock'event and clock = '1') then z <= a; end if; end process; end; What Next Us4#HDL-110 Message %1 Description This error occurs when a value is assigned in the FALSE branch of an "if clock'event". This error can happen if a value is assigned on the "else" part of the "if clock'event", or if a value is assigned before the "if clock'event" and in the TRUE branch. The first example below shows an illegal assignment in the FALSE branch: entity test is port(clock, a, b: in bit; z: out bit); end; architecture a of test is begin process (clock, a, b) begin if(clock'event and clock = '1') then z <= a; else z <= b; -- ERROR end if; end process; end; The second example behaves like the previous one because the assignment from "b" takes effect only when there is no event on the clock. entity test is port(clock, a, b: in bit; z: out bit); end; architecture a of test is begin process (clock, a, b) begin z <= b; -- ERROR if(clock'event and clock = '1') then z <= a; end if; end process; end; P:8# HDL-111 Message %1 Description This error occurs when you use the 'event construct in VHDL, or the positive-edge construct in Verilog, on a value that is not a single-bit simple signal or variable. What Next Change your code to refer to a single-bit clock signal. #; end process; end a; P:8#TD_LOGIC_1164.all; use IEEE.STD_LOGIC_SIGNED.all; use IEEE.STD_LOGIC_ARITH.all; package tp is subtype i4 is integer range 0 to 3; procedure p (signal x:in integer; signal y:inout STD_LOGIC_VECTOR(0 to 1)); end tp; package body tp is procedure p (signal x:in integer; signal y:inout STD_LOGIC_VECTOR(0 to 1)) is begin y <= CONV_STD_LOGIC_VECTOR(x + CONV_INTEGER(y), 2); end; end tp; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_SIGNED.all; use IEEE.STD_LOGIC_ARITH.all; use work.tp.all; entity good is port (a: in i4; b: inout i4; clk: in BIT; z: out i4); end good; architecture a of good is signal ax : i4; signal bx : STD_LOGIC_VECTOR(0 to 1); begin process (clk, a, b) begin if (clk'event and clk = '1') then ax <= a; bx <= CONV_STD_LOGIC_VECTOR(b, 2); p(ax, bx); z <= CONV_INTEGER(bx); end if#HDL-112 Message %1 Description This error occurs when the inout (out) signal parameters of a procedure are of range (integer) type, which the VHDL Compiler does not support for synthesis. What Next Convert range type to a bit-vector type. For example, modify "bad.vhdl" to "good.vhdl". -- "bad.vhdl" package tp is subtype i4 is integer range 0 to 3; procedure p (signal x: in integer; signal y: inout integer); end tp; package body tp is procedure p (signal x: in integer; signal y: inout integer) is begin y <= x + y; end; end tp; use work.tp.all; entity bad is port (a: in i4; b: inout i4; clk: in BIT; z: out i4); end bad; architecture a of bad is signal ax, bx : i4; begin process (a, b) begin if (clk'event and clk = '1') then ax <= a; bx <= b; p(ax, bx); z <= bx; end if; end process; end a; -- "good.vhdl" library IEEE; use IEEE.SY:8$/HDL-113 Message %1 Description This error occurs if the width of a port is different for different instances of a subdesign (component) in the same parent design. What Next Modify your HDL description so that the width of the port is consistent across various instances of the instantiated design. #$ HDL-114 Message %1 Description This error occurs when the same subdesign (component) is instantiated with differing number of ports in the same parent design. What Next Modify your HDL description so that the number of ports is the same for all instances of the instantiated design. h:84$HDL-115 Message %1 Description This error occurs if, in instantiating a subdesign (component), named and positional styles of port association are mixed. What Next Use either named style of positional style of specifying port association. E$HDL-116 Message %1 Description This error occurs if a parameter (generic) is specified but no value is assigned to it. What Next Specify a value for the parameter (generic). C|8V$HDL-117 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. g$HDL-118 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. C|8x$HDL-11 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. $HDL-123 Message %1 Description This error occurs when the type of an aggregate or concatenation cannot be determined. What Next Modify your HDL description to qualify the operation with a type. l:8$HDL-124 Message %1 Description This error occurs when the values specified for an aggregate do not cover all the possible elements or if more than one value is specified for the same element or if the values specified are for elements that are not part of this aggregate. What Next Modify your HDL description to ensure that there is one to one correspondence between elements of the aggregate and the values specified for it. $HDL-127 Message %1 Description The arguments to a VHDL concatenation must either 1) be the same type (two BITs, or two BIT_VECTORS), or 2) one must be an array and the other must be a member of that array (one BIT_VECTOR and one BIT). This error indicates that the arguments to the VHDL concatenation operator are invalid (an array of BITS concatenated with an array of INTEGERS). What Next Make the concatenation arguments compatible. C|8$HDL-12 Message %1 Description This error occurs when a declared constant or generic parameter is used before the value has been assigned. Remember that generic parameters can be used in the design name. What Next Assign a value to the constant where it is declared. $HDL-130 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. C|8$HDL-131 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. $PHDL-139 Message %1 Description This error occurs when the HDL Compiler can't find a file in the search path. The search path lists directories where HDL Compiler should look for source files. What Next First, check the spelling of the file name. If it is correct, fix your search path to include the directory that holds the file. x:8%HDL-140 Message %1 Description This error occurs when reading a "threestated" or "don't cared" value. For example: if(ENABLE) then X := A; else X := 'Z'; -- Threestate assignment end if; Y := W and X; -- Error: reading a threestated value. What Next Generally, you should read these values in a separate process or always block. If you must read them in the same process or always block, read the value before any don't care or threestate assignments. %HDL-146 Message %1 Description This error occurs when the type function identified with the type_function pragma cannot be found. Used in conjunction with the the map_to_operator pragma, the type_function pragma defines the return type of the function in which the type_function pragma is used. What Next Provide the function referred to in the type_function pragma. NOTE Use of type_function is discouraged. Use output_port_type instead. :8*%KHDL-147 Message %1 Description This error occurs when the ports in the function identified by the type_function pragma do not match the ports in the function in which the type_function is embedded. What Next Modify the type function so the ports match. NOTE Use of type_function is discouraged. Use output_port_type instead. =%HDL-148 Message %1 Description This error occurs when the subrange of an enumerated type does not match the type declaration. This can occur if the range is out of order or the direction does not match. What Next Change the subrange expression to match the enumeration declaration. r:8N%HDL-149 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. _%HDL-14 Message %1 Description This error can occur when you try to assign a value to a literal. Literals include: numbers such as 567, vectors such as "1101", or enumeration literals as STATE_7. Assignments can be made with assignment statements or output parameters of subroutines. What Next If the literal is an subroutine actual parameter, change the mode to "out". If the literal lies on the left-hand side of an assignment, move it to the right. :8p%(HDL-150 Message %1 Description This error occurs when you use a subroutine with a map_to_entity attribute, and one of the subroutine's ports is unconstrained. All port types must be constrained before you can use map_to_entity. What Next Add range constraints to the port type declarations. %HDL-151 Message %1 Description This error indicates that the state_vector attribute was used more than once in an entity or module. Each entity or module is allowed a single state vector. What Next If you need two state vectors (to implement communicating state machines, for example) put each state machine in a separate entity or module. If you only need one state vector, then remove the extraneous state vector attribute. C|8%VHDL-152 Message %1 Description This error occurs when an enumeration literal is expected, but something else is supplied. For example, this can occur in an enumeration subrange where the bounds should be specified by enumeration literals, but are instead specified by integers. What Next Use an enumeration literal where it is expected. %HDL-154 Message %1 Description This error occurs when port names in subroutine calls do not match the names in the subroutine definition. What Next Make sure the subroutine call and subroutine definition port names match. :8%HDL-155 Message %1 Description This error occurs when the index value is not within the bounds specified for the array. What Next Modify the description so that the index value lies within the array bounds. Examples Verilog: reg [3:0] my_bus; wire foo; assign foo = my_bus[4]; /* 4 is outside the array bounds [0,3] */ VHDL: variable my_bus: bit_vector (0 to 3); signal foo: bit; foo <= my_bus(4); -- 4 is outside the array bounds [0,3] %-HDL-156 Message %1 Description This error occurs when the index range is not within the bounds defined for the array. What Next Modify the description so that the index range is within the bounds defined for the array. Examples Verilog: reg [3:0] my_bus; wire [1:0] foo; assign foo = my_bus[4:3]; /* 4 is outside the array bounds [0,3] */ VHDL: variable my_bus: bit_vector (0 to 3); signal foo: bit_vector (0 to 1); foo <= my_bus(4 downto 3); -- 4 is outside the array bounds [0,3] I8% process begin -- This will fail because the wait is disabled -- wait until clock'event and clock = '1'; state <= state xor a; end process; z <= state; end; /* Verilog */ module e(clock, a, z); input clock, a; output z; reg state; /* The variable name is misspelled */ /* synopsys state_vector statex */ always @(posedge clock) begin state = state ^ a; end assign z = state; endmodule Example Message Warning: State vector 'statex' was specified, but is not a valid state vector. (HDL-158) %HDL-158 Message %1 Description The state vector directive identifies the variable that holds the state of a state machine. See or for more information on the state vector directive. This error occurs when the variable identified in the directive either does not exist, or did not get a flip-flop to hold its value. For more information on how to get the HDL Compiler to build a flip-flop to hold the value of a variable, see or . What Next Spell the variable in the state vector directive so it matches the variable declaration. Next, check the inferred devices report (see \). If the state variable does not appear in the report, or if the memory device listed is not a flip-flop, modify your description to assign the variable on the edge of a clock. Examples -- VHDL entity e is port(clock, a: in bit; z: out bit); end; architecture a of e is signal state : bit; attribute state_vector : string; attribute state_vector of a:architecture is "state"; begin :8*&VHDL-159 Message %1 Description The operator defined by a map_to_operator attribute was not described in any of the synthetic libraries in the synthetic_library variable (and was not found in standard.sldb). What Next If you want to use the synthetic library operator, make sure it can be found in the files defined by synthetic_library. ;& HDL-15 Message %1 Description 0, 1, Z, D, or U are the only values recognized by this compiler. This error occurs when you specify some other value, such as 'X' (see the example below). What Next Rewrite your description to use one of the recognized values. Examples VHDL: attribute ENUM_ENCODING: string; type color is (red, green, blue); attribute ENUM_ENCODING of color: type is "00, 01, 1x"; the specification of X as an encoding in the literal will cause this error.  :8V&HDL-160 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. g&HDL-162 Message %1 Description This error occurs when you state that two resources may merge and also that they may not merge. For example, if you indicate that resource R0 may merge with R1, but that R1 may not merge with R0, you will get this error. For more information see the "User Directive Conflicts" section of the "Resource Sharing" chapters in either of the the reference manuals for VHDL and Verilog compiler. What Next Modify your directives so that the may_merge_with and dont_merge_with directives do not disagree. :8x&HDL-163 Message %1 Description The VHDL Compiler does not support arbitrary resolution functions. It supports wired_and, wired_or and three_state as resolution methods. Any function that is used as a resolution function must include a resolution_method pragma that indicates which of the three supported resolution methods is to be used. This error occurs when the resolution_method pragma is missing. What Next Add one of the following resolution_method pragma to the resolution function: wired_and, wired_or, or three_state &XHDL-164 Message %1 Description The VHDL Compiler does not support arbitrary resolution functions. It supports wired_and, wired_or and three_state as resolution methods. Any function that is used as a resolution function must include a resolution_method pragma that indicates which of the three supported resolution methods is to used. This error occurs when the resolution_method pragma indicates a resolution method other than the three methods supported. What Next Modify the resolution_method pragma for the resolution function to be one of the following: wired_and, wired_or or three_state. D|8&HDL-165 Message %1 Description The indicated function could not be found. This happens when the name of the function is spelled incorrectly. What Next Check to make sure all resolution functions are provided and spelled correctly. &+HDL-167 Message %1 Description This error occurs when an environment variable should have a string value, but instead the value has some other type. What Next When you assign the value of the environment variable, you can use double quotes around the value you assign to insure it is a string. :8&8HDL-169 Message %1 Description HDL Compiler removes all logic which does not eventually fan out to out or inout ports. This warning occurs when the state vector flip flops are deleted due to a lack of fanouts. This does not necessarily indicate an error, but it probably means that the state machine is not hooked up properly. What Next If you know that the state vector is unused, then you can safely ignore this warning. Otherwise, check the connections in your state machine to be sure the output ports, next-state logic and state vector communicate properly. & begin .. .. end; -- -- workaround will be to move the constant declaration after the -- function body -- begin end; :8&HDL-16 Message %1 Description This error occurs when reading an unconstrained variable, port, or signal. For synthesis, all values must have a fixed bit width. The error occurs, for example, when you declare an entity port to have the type: BIT_VECTOR. The error can also occur if a function with a built_in pragma is invoked before the function body is analyzed. In such a case, the workaround is to define the function and its body before the function is invoked. What Next Use an array-bound constraint when you declare the object. In the above example, you can change the entity port type to BIT_VECTOR(1 to N), where N is a constant, literal, or generic value. Examples entity foo is end foo; architecture bar of foo is function func_with_built_in (i, size: integer) return bit_vector; constant x:bit_vector(31 downto 0) := func_with_built_in(3, 32); function func_with_built_in (i, size: integer) return bit_vector is -- pragma built_in SYN_INTEGER_TO_SIGNED&HDL-170 Message %1 Description Comparisons in hardware are inherently different than in the simulator. Digital hardware comparators can only distinguish between ones and zeros. Thus, it makes no sense to synthesize comparisons to three-state, don't-care or unknown literals. Since signals are assumed to carry a value of one or zero, equality tests to non-one/zero values always return false in synthesis. What Next There is probably no need to modify your HDL if the comparison was used for simulation purposes only. For example, if you want to print an message when an input port is in the high-impedance state, it is ok to compare its value to 'z'. If you are using the comparison to affect the state of your circuit, you should consider recoding your HDL. For example, if you need a four-state state-machine, don't declare a single-bit variable and use 0, 1, x, and z as your states. In hardware, each bit only holds two useful states: 1 and 0. :8'HDL-173 Message %1 Description The value shown is not valid. The value assigned for add_ops must be either "true" or "false". What Next Assign either "true" or "false" for add_ops. ' HDL-174 Message %1 Description This error occurs when a task is instantiated such that one of its output ports is connected to a variable of type wire. What Next Modify your description so that the variable connected to the output port of the task is of type reg. :8*'aHDL-175 Message %1 Description The synthesis policy does not support the use of a value as both clock and data in the same process. What Next If you need to compute a value that is based on a clock signal (for example, to generated a gated clock), then you must perform the computation outside any process that that is sensitive to the clock edge. ;'ata; /* WARNING */ else z = a; end assign z = state; endmodule The problem with this description is that the simulation model does not react to changes in reset_data while reset_enable is held high. What Next In VHDL the solution is to add reset_data to the process sensitivity list. In Verilog, you can't add reset_data to the sensitivity list without breaking the model. Thus, In the above case Synopsys recommends that you verify that your model does not rely on the fact that during reset, the simulator holds z steady even though reset_data changes. The synthesized register will be transparent during reset. :8;'HDL-176 Message %1 Description This warning occurs in the asynchronous reset part of a process or always block. It occurs when a value not in the sensitivity list or block timing control is read. This typically occurs when a non-constant value is assigned on the asynchronous reset. In the following example reset_data is incorrectly read: -- VHDL entity e is port(clock, a, reset_enable, reset_data: in bit; z: out bit); end; architecture a of e is begin process (clock, reset_enable) begin if(reset_enable = '1') then z <= reset_data -- WARNING elsif(clock'event and clock = '1') then z <= a; end if; end process; end; /* Verilog */ module e(clock, a, reset_enable, reset_data, z); input clock, a, reset_enable, reset_data; output z; reg z; always @(posedge clock or posedge reset_enable) begin if(reset_enable) z = reset_dl'HDL-177 Message %1 Description HDL Compiler assumes that processes should run whenever doing so would change an output value. If a description is written so that the simulator might not execute a process even though doing so could change an output, HDL Compiler displays a warning. The incomplete sensitivity list warning (see HDL-179) tells when a signal is read but it is not on the sensitivity list. A simulation/synthesis mismatch can occur when the signal changes because the synthesized hardware reacts immediately, whereas the simulator waits for an event on the sensitivity list. This warning is similar to HDL-179, but it happens with variables instead of signals. The difference is that you can't fix the problem by adding to the sensitivity list because variables are not allowed in the sensitivity list. The following example shows how such a situation can cause a simulation/synthesis mismatch: entity e is port(a: in bit; z: out bit); end; architecture a of e is begin D|8l' process(a) variable temp: bit; z <= temp; -- WARNING temp := a; end process; end; HDL Compiler builds a circuit with 'a' feeding directly to 'z'. The simulator, however, feeds the opposite value. Consider what happens when 'a' transitions from '0' to '1'. At the start of the process, 'temp' holds a '0', so 'z' is driven with '0'. At the end of the process, 'temp' is assigned '1', the new value of a. When 'a' transitions from '1' to '0', the process runs a second time, and the '1' in temp finally makes it to the output. Notice that 'z' lags one step behind 'a'. In this case it means that 'z' is really equal to 'not a'. What Next You can fix this problem by making default assignments to all variables as the first step in a process. Or you can reorder the computations in the process to read variables only after they have been set. The following example shows a fixed version of the previous example. Notice that the assignmentl's are reordered. entity e is port(a: in bit; z: out bit); end; architecture a of e is begin process(a) variable temp: bit; begin temp := a; z <= temp; -- OK end process; end; Example Message Warning: Local variable 'temp' is being read before its value is assigned, in routine e line 7 in file 't.v'. This may cause simulation not to match synthesis. (HDL-177) D|8'HDL-178 Message %1 Description The list of variables to which a process (in VHDL) or an always block (in Verilog HDL) is sensitive must contain simple variable names. Lists that contain indexed variables or not-processed variables are ignored. What Next If possible, rewrite the description so that the sensitivity list contains only simple names. As you rewrite the description, be careful not to introduce errors by making the process or block sensitive to more variables than necessary. The usual workaround is to assign to a temporary variable the required bit or slice of the variable, and to make the process or block sensitive to this temporary variable. Examples VHDL process ( bus(1) ) begin -- bus(1) is not a simple variable. The workaround follows: temp := bus(1); process ( temp ) begin Verilog always @ (bus[1]) begin /* bus[1] is not a simple variable. The workaround follows: temp = bus[1]; always @ ( temp ) b'egin :8'Fin the sensitivity list to ensure an accurate modeling of the hardware. If you want to leave values out (for simulation efficiency, for example), you should convince yourself that leaving them out does not change the results computed by the simulator, and then ignore this warning. If you are not sure whether delaying the execution of a process will affect the results, it is safer to simply add the value to the list. For example, the above description would be much safer if written: entity e is port(a, b: in bit; z: out bit); end; architecture a of e is begin process(a, b) begin z <= a xor b; end process; end; Example Message Warning: Variable 'b' is being read in routine e line 8 in file 'b.v', but is not in the process sensitivity list of the block which begins there. (HDL-179) 'HDL-179 Message %1 Description Since the hardware generated by the HDL compiler is sensitive to to all inputs, you should normally include all read signals in a process's sensitivity list. This warning is displayed when you don't. The following example shows why it is important to include all read signals in the sensitivity list: entity e is port(a, b: in bit; z: out bit); end; architecture a of e is begin process(a) begin z <= a xor b; end process; end; HDL Compiler builds a circuit with an 'xor' gate reading 'a' and 'b', and driving 'z'. Whenever either 'a' or 'b' changes, the hardware immediately computes a new value for 'z'. The simulator, in contrast, executes the process only when 'a' changes, since 'b' was left out of the sensitivity list. Thus, while 'a' keeps a steady value, the simulator does not propagate changes in 'b' to the output. This can cause a simulation/synthesis mismatch. What Next It is always safer to include values :8'HDL-17 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. ( there. (HDL-180) :8( Thus, while 'a' keeps a steady value, the simulator does not propagate changes in 'b' to the output. This situation can cause a simulation/synthesis mismatch. What Next To ensure an accurate modeling of the hardware, it is always safer to include values in the sensitivity list. If you want to omit values (for simulation efficiency, for example), first verify that leaving them out won't change the results computed by the simulator then ignore this warning. If you are not sure whether delaying the execution of a block will affect the results, it is safer simply to add the value to the list. For example, the previous description would be much safer if written module e(a, b, z); input a, b; output z; reg z; always @( a or b ) begin /* Much safer */ z = a ^ b; end endmodule Example Message Warning: Variable 'b' is being read in routine e line 6 in file 'b.v', but does not occur in the timing control of the block which begins (HDL-180 Message %1 Description A variable is missing from the timing control, also known as the sensivity list. This warning indicates which variable is missing from the list. Leaving a variable out of the sensitivity list can cause simulation to disagree with synthesis. Simulation only propagates changes for variables when they appear in the sensivity list. Synthesized hardware will propagate changes even for variables missing from the sensitivity list. The following example shows the importance of a complete sensitivity list: module e(a, b, z); input a, b; output z; reg z; always @( a ) begin /* Incomplete sensitivity list */ z = a ^ b; end endmodule HDL Compiler builds a circuit with an 'xor' gate reading 'a' and 'b', and driving 'z'. Whenever either 'a' or 'b' changes, the hardware immediately computes a new value for 'z'. The simulator, in contrast, executes the always block only when 'a' changes, since 'b' was left out of the sensivity list.D|80(HDL-183 Message %1 Description This error occurs when the variable that serves as the clock for a description is greater than 1 bit in width. The clocking variable for a design is the one that is specified in VHDL statements such as: wait until clock'event and clock = '1' ; and in Verilog statements as: always @ (posedge clock) What Next Rewrite your description to specify a 1-bit wide clock. A(HDL-184 Message %1 Description This error occurs if none of the case statement alternatives match the case expression in a case statement. What Next Modify your HDL description so that at least one case statement alternative can match the case expression. 8R(HDL-185 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. c({HDL-186 Message %1 Description This error happens when the argument to the elaborate command includes a combination of order-based and name-based parameter values, and all the order-based parameters are not specified before name-based parameters. What Next Modify the arguments to the elaborate command so that all order-based parameters occur before name-based parameters. 8t(HDL-187 Message %1 Description This error occurs when the argument to the elaborate command includes more parameter values than the number of generics (parameters) that exist in the design. What Next Modify the arguments to the elaborate command to remove the extra parameters. (HDL-188 Message %1 Description This error occurs when the argument to the elaborate command includes a parameter value for a generic (parameter) that does not exist in the design. This error can also occur when a parameterized design is instantiated in VHDL with a named parameter that does not exist in the intantiated entity. What Next Remove the incorrect parameter from the arguments to the elaborate command. E|8(HDL-189 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. (HDL-18 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. :8(HDL-190 Message %1 Description This error occurs when the format specified for naming the template of a design ("template_name_style") or for naming the architecture of a design (when writing out VHDL) has an invalid character. What Next See the "Design Compiler Interface" chapter of the VHDL Compiler manual for the correct way to set this variable. Modify the appropriate variable to be of the specified format. (HDL-191 Message %1 Description This error occurs when the value specified for a generic (parameter in Verilog) is not an integer. What Next Rerun the elaborate command with the correct value for the parameter. 8(HDL-193 Message %1 Description This information message is issued when a new design is being built as a result of the read or elaborate command. (pHDL-194 Message %1 Description This error occurs when the template specified to the elaborate or similar commands does not exist or was not found because of incorrect library specification (in VHDL). What Next Check to see if the name of the template has been correctly spelled. If using VHDL, check to make sure that the libraries have been correctly specified. :8(HDL-195 Message %1 Description This error can happen if a design unit is analyzed with a package, and then is elaborated with another package. Normally, this will be flagged as an error. However, if both versions of the package were analyzed before the entity was, the timestamp checking will think that this is okay, but if the packages are significantly different, problems may occur. What Next Reanalyze all of the source code from scratch.  )HDL-19 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. =:8)HDL-1 Message %1 Description The compiler for your Verilog HDL or VHDL description could not find the file verilog.prims or vhdl.prims. This happens when Synopsys software is incorrectly installed on your machine. What Next Reinstall the Synopsys software. -)HDL-200 Message %1 Description In a Verilog HDL case statement, the default clause must be the last clause. This error occurs if this condition is not met. What Next Rewrite your description so that the default clause occurs last in the case statement. :8>)HDL-201 Message %1 Description This error occurs when the format specified for separators in the name of a template ("template_seperator_style") contain illegal characters. This error may also occur if the format for naming an architecture (when writing out VHDL) contains illegal characters. What Next See the "Design Compiler Interface" chapter of the VHDL Compiler manual for the correct way to set this variable. Modify the format so that it contains only legal characters. O)HDL-202 Message %1 Description This information message is issued when a design (module, entity, or architecture) or a package is being saved to the disk. 8^)HDL-203 Message %1 Description This information message is issued when the new design or package that is being processed overwrites an existing design or package of the same name. m)ZHDL-204 Message %1 Description This error occurs when more generics are specified as arguments to the "elaborate" command than are specified in the description of the design being elaborated. What Next Check the design description to find the correct number of generics and rerun the "elaborate" command with the correct number of generics. 8~)iHDL-205 Message %1 Description This error occurs when the value specified for a generic is bigger than the maximum or smaller than the minimum allowable value for the generic. What Next Check the description of the design being elaborated to find the allowable value of the generic and rerun the "elaborate" command with the correct value for the generic. )kHDL-206 Message %1 Description This error occurs if a generic map is used and if a port is indexed (or sliced) on the left hand side of a port map clause of a component instantiation statement. What Next Modify the HDL description to (a) replace the generic with a constant or (b) not slice or index the port on the left hand side of the port map statement. :8) HDL-207 Message %1 Description This error occurs when the dc_shell variable "vhdlout_conversion_functions" is set to an incorrect value. What Next See the "Design Compiler Interface" chapter of the VHDL Compiler manual for the correct way to set this variable. )HDL-208 Message %1 Description This warning occurs when the dc_shell variable "hdlin_source_to_gates_mode" is not set to a valid value. What Next Set the variable to a correct value. E|8)HDL-209 Message %1 Description This warning occurs if a design is read in using the "read" command. Use the "analyze" command if you want to elaborate this design with different values for the generics. )HDL-20 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. :8)HDL-211 Message %1 Description VHDL source files that contain configurations must be read in using the analyze command. If they are read in using the read command, the configuration statements are ignored. What Next If the configuration statements should not be ignored, read in the VHDL source file using the analyze -f vhdl command. You can then build the design by using the elaborate command. )HDL-213 Message %1 Description All library names have a mapping to a UNIX directory in dc_shell. These mappings are done either in your '.synopsys_vss.setup' file or by the dc_shell command 'define_design_lib'. The 'read -f vhdl' command writes intermediate files to the library WORK. The corresponding UNIX directory was not writeable, or did not exist at the time the read command was invoked. What Next Change the mapping for library WORK either in your .synopsys_vss.setup file or by using the define_design_lib command. Also make sure the corresponding UNIX directory exists and has the necessary permissions. The .synopsys_vss.setup file is read only once, at program start up. Hence, if you change the mapping here you must re-start dc_shell or design_analyzer for the change to take effect. Note that there is a search path involved for the .synopsys_vss.setup file. If there is one in the directory where the dc_shell is started it will be used. Else if there is one in your home direct:8)ory it will be used. Else the one in <synopsys_root>/admin/setup/ will be used. If only some setup information was found in a file outside <synopsys_root>/admin/setup/.synopsys_vss.setup, the next one is read to get the missing information. *HDL-21 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. :8*[=i+1) C[i] = B[i]; end endmodule Example Message Warning: Variable 'i' is driven in more than one process or block in file t.v This may cause mismatch between simulation and synthesis. (HDL-220) Warning: Variable 'C' is driven in more than one process or block in file t.v This may cause mismatch between simulation and synthesis. (HDL-220) The first warning in this example is serious because the first block drives a '1' onto 'i', and the second block drives a '3'. The second warning is not serious because different bits of 'C' are driven from each block. *h changed most recently. HDL Compiler simply shorts 'A' and 'B' to 'C'. module VERILOG_Example ( A, B, C ); input A, B; output C; reg C; always @( A ) begin C = A ; end always @( B ) begin C = B; end endmodule Example Message Warning: Variable 'C' is driven in more than one process or block in file /home/mine/design/dir/x220.ver This may cause mismatch between simulation and synthesis. (HDL-220) SECOND Example In the following example, 'i' is used as a loop index in two always blocks. The result is that 'i' is driven in both processes by different constants. Both power and ground are shorted onto 'i'. This is a serious problem that should be fixed by declaring separate loop variables for each block. module VERILOG_Example ( A, B, C ); input [3:0] A, B; output [3:0] C; reg [3:0] C; integer i; always @( A ) begin for (i=0; i<=1; i=i+1) C[i] = A[i]; end always @( B ) begin for (i=2; i<=3; i:8*HDL-220 Message %1 Description In simulation, the always block last fired up drives the variable (the drivers are multiplexed). In synthesis, the drivers are shorted together. This situation is especially serious if the values driven by two always blocks are different constants, since this will short power to ground. The HDL Compiler does not keep track of individual bits in a bus when issuing this warning. If bits of a bus are driven from different always blocks, and each bit is driven from one block only, this warning is still issued even though simulation and synthesis match. What Next If individual bits of a bus are driven from a single block, you can ignore this warning. Otherwise, move the drivers of the variable into the same always block or use a three-state bus. If the problem came from the reuse of a loop variable, declare separate loop variables for each block. FIRST Example In the following example, the simulator will assign 'C' from either 'A' or 'B', depending on whicV*Tment must not appear in a function or a process which has a sensitivity list. :8V*HDL-222 Message %1 Description The use of wait statement in a function or process is mutually exclusive with the use of a sensitivity list. What Next Remove the sensitivity list or re-write the offending code to not make use of the wait statement. Example entity MULTWAIT_VHDL is port( I1, I2: in BIT ; CLOCK : in BIT ; Out_Port : out BIT ); end MULTWAIT_VHDL; architecture test_behavior of MULTWAIT_VHDL is begin process ( clock ) begin wait until clock'event and clock = '1' ; Out_Port <= I1 ; wait until clock'event and clock = '1' ; Out_Port <= I2 ; end process; end test_behavior; Example Message wait until clock'event and clock = '1' ; ^ **Error: vhdlan,1044 /home/mine/design/dir/x222.vhd(10): Wait statement must not appear in a function or a process which has a sensitivity list. wait until clock'event and clock = '1' ; ^ **Error: vhdlan,1044 /home/mine/design/dir/x222.vhd(12): Wait state*vHDL-223 Message %1 Description What Next Remove the timing control statement or re-write the offending code to not make use of embedded event expressions. Examples module multwait_V( I1, I2, CLOCK, Out_Port); input CLOCK; input I1, I2; output Out_Port; reg Out_Port ; always @( posedge CLOCK) begin : process_blk @(posedge CLOCK) Out_Port = I1; @(posedge CLOCK) Out_Port = I2; end endmodule Example Message Error: Always block in routine multwait_V line 7 in file '/home/mine/design/dir/x223.ver' has both a timing control statement as well embedded event ('@') expressions. (HDL-223) :8*HDL-224 Message %1 Description All wait statements in same process must be triggered by same clock edge. What Next Modify the offending process' wait statements to be triggered by same clock edge. Examples In this example one wait statement is triggered by a rising clock edge while the other is triggered by the falling clock edge. entity MULTWAIT_VHDL is port( I1, I2: in BIT ; CLOCK : in BIT ; Out_Port : out BIT ); end MULTWAIT_VHDL; architecture test_behavior of MULTWAIT_VHDL is begin process begin wait until clock'event and clock = '1' ; Out_Port <= I1 ; wait until clock'event and clock = '0' ; Out_Port <= I2 ; end process; end test_behavior; Example Message Error: Wait statements in process in routine MULTWAIT_VHDL line 0 in file '/home/mine/design/dir/x224.vhd' use different clocks or clock edges. (HDL-224) *HDL-225 Message %1 Description What Next Modify the offending always block's event ('@') expressions to be triggered by same clock edge. Examples In this example the event expressions are triggered by positive and negative clock edges respectively. module multwait_V( I1, I2, CLOCK, Out_Port); input CLOCK; input I1, I2; output Out_Port; reg Out_Port ; always begin : process_blk @(posedge CLOCK) Out_Port = I1; @(negedge CLOCK) Out_Port = I2; end endmodule Example Message Error: Event ('@') expressions in always block in routine multwait_V line 7 in file '/home/mine/design/dir/x225.ver' use different clocks or clock edges. (HDL-225) ;8*lways block in routine V1 line 9 in file '/home/my/design/x227.ver' contains unsupported event ('@') expressions. (HDL-227) *HDL-227 Message %1 Description Event expressions are not supported in subprograms or for loops. What Next Modify subprograms not to contain event expressions or "inline" them. Change for loops into forever loops. Examples Example of unsupported for loop: module V1(a, b, clock, d); input [0:3] a, b ; input clock ; output [0:3] d; reg d; integer i; always begin for (i = 32'd0; /* for-loop enclosing event expression, not supported */ i < 32'd4; i = i + 32'd1) begin @ (posedge clock) d[i] = a[i] & b[i]; end end Above example rewritten into supported format: module V2(a, b, clock, d); input [0:3] a, b ; input clock ; output [0:3] d; reg d; integer i; always begin i = 32'd0; /* init of loop-invariable */ forever begin : infinite_label i = i + 32'd1; /* increment loop-invariable */ @ (posedge clock) d[i] = a[i] & b[i]; if( i > 32'd4) disable infinite_label; /* loop exit */ end end Example Message Error: A;87+#HDL-22 Message %1 Description This error occurs when you use a VHDL "next" or "exit" statement, or a Verilog "disable" statement and the identifier you uses does not refer to an enclosing loop name. What Next Change the indentifier in your statement to refer to an enclosing loop name. H+'HDL-230 Message %1 Description You have defined a package name that conflicts with a built-in package. The built-in packages are "vhdl," "verilog," and VHDL's predefined "standard." What Next Because these packages are built in, they are always present. Hence, the VHDL library clause is of no help here. You must modify the name of the conflicting package. Examples -- VHDL package standard is end; Example Message Error: "standard" is used as a name for an internal package. Please use a different name for your package. (HDL-230) ;8d+<HDL-231 Message %1 Description The Synopsys state machine compiler only accepts 0 or 1 encodings for its states. For example, a don't care state is not passed to the state machine compiler during the subsequent extract information. The logic for the state is still treated correctly but the encoding for the state will not be shown by the report_fsm command. For a don't care state, it is possible that every time the state is referenced, it will receive a different encoding. What Next Be aware that state machine encodings other than 0 or 1 will not not be saved. v+HDL-232 Message %1 Description Valid states that can be passed to the Synopsys state machine compiler are vectors of 0's and 1's. don't care states are parsed and ignored, but no other states are valid. What Next Change the encoding for the state to a valid encoding. ;8+0HDL-233 Message %1 Description There were two states in your design with identical encodings. The second state name will not be saved. What Next To avoid this warning, replace all references to the duplicate state name with the original state name and remove the definition for the duplicate state. +HDL-234 Message %1 Description VHDL allows you to define multiple architectures for one entity. When using the read command, however, only one design is built per entity. As a result, only the first architecture encountered is used. What Next You can use the analyze or elaborate commands to build architectures other than the first one defined in your design. Examples ENTITY A_VHDL IS END ; ARCHITECTURE DOIT OF A_VHDL IS BEGIN END ; ARCHITECTURE DOIT_AGAIN OF A_VHDL IS BEGIN END ; Example Message Warning: Design 'A_VHDL' has multiple architectures defined. The first architecture defined ('DOIT') will be used to build the design. (HDL-234) ;8+HDL-235 Message %1 Description This error message indicates that your installation of the Synopsys tools has been corrupted. You need to reread "libraries/syn/gtech.db" from your Synopsys release tape. +Kxpression, the second branch always fires, making 'z' zero. What Next If you know that the expression in the case-item is never 'x' or 'z', then you may ignore this warning. You can eliminate the warning by omitting expressions from the case-items of casex and casez statements. If you need an expression as a case-item, use a regular case statement. Example Message The code fragment above receives the following message: Warning: Non-constant case-item used in casex or casez. HDL Compiler assumes the expression is never 'x' or 'z' in routine e line 10 in file 'b.v' (HDL-236) ;8+HDL-236 Message %1 Description This warning is not serious unless the expression used in the case-item may take the value 'x' or 'z'. HDL Compiler builds the logic of a casex or casez assuming the case-item expression will yield ones and zeros. Under simulation, when some bits of the expression are 'x' or 'z', they are ignored. This can generate a simulation/synthesis mismatch in the following example: module e(a, z); input a; output z; reg z; wire ctl; assign ctl = a ? 1'b0 : 1'bx; always @(ctl) begin casex(1'b1) ctl: z = 1'b1; default: z = 1'b0; endcase end endmodule Under simulation, when 'a' is false, 'ctl' is assigned 'x', and the first branch of the casex always fires making 'z' one. Under synthesis, the 1'bx is treated as a dont-care, and ?: operation optimizes away leaving 'ctl' always equal to zero ('b' is left unconnected). Since 'ctl' never matches the case e+HDL-23 Message %1 Description This error occurs when any array element is indexed outside the bounds of the specified array. What Next Modify your description so that access occurs within the specified bounds of the array. Examples Verilog: reg [0:7] bus; single_bit = bus[8]; VHDL: variable bus_array: bit_vector(0 to 7); single_bit := bus_array(8); F|8  ,HDL-240 Message %1 Description Pragma map_to_entity is not supported for procedures with IN/OUT ports. When a port is used as input and output at the same clock cycle, a combinational loop results. Usually, in a circuit with an IN/OUT port, a control (switch) logic determines the port's direction in each clock cycle. The use of IN/OUT ports implies multiple-cycle behavior of a procedure, and Synopsys does not support procedures with multiple-cycle behavior. What Next Change the IN/OUT port to one IN port and one OUT port.  ,HDL-241 Message %1 Description This error message is issued following a LINK error message. What Next See the LINK error message. F|8 0, HDL-250 Message %1 Description There is no hardware device to produce an UNKNOWN signal. The UNKNOWN value is for simulation purpose only. What Next Use '-- pragma translate off' and '-- pragma translate on' to direct the VHDL Compiler to skip this assignment.  A,(HDL-25 Message %1 Description This error occurs when you use an unconstrained range. The bounds of a range must be fixed before it may be used to specify an array range or declare a new object. What Next Change your description so that a bound will be placed on the range before it is used. ;8 R,HDL-260 Message %1 Description All parameters must be integers for instantiation. This parameter is treated as uninitialized when using the get_attribute command. What Next Change the parameter to an integer within 32 bits. c,HDL-26 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. !;8t,HDL-270 Message %1 Description Synopsys does not synthesize logic for HDL description in a constant declaration. All constants must be computable during HDL compilation. Therefore, the computation in constant declarations is restricted to operations of integer type. Moreover, arithmetic operations on integer constants greater than 32 bits is not supported. What Next Cast constants to integer type if you need to perform an arithmetic operation in constant declaration. Otherwise, move the computation outside of constant declaration. For example, you can change the constant to a variable and perform the arithmetic operations on the variable. Note that computations on variables always produce logic. ,rHDL-272 Message %1 Description When one selector of a MUX is always one, the selected input is always being transferred to the output. Hence this input could override all other inputs. Such a situation could occur in Verilog if a casex statement is used and one of the conditions is x in all the bits. This is useful as a default condition, but should not be used along with Synopsys parallel-case directive. What Next Designers should check their HDL descriptions to confirm their intention to have one selector of a MUX always be logic one. If such is not the intention, the designer should modify the HDL description. F|8,HDL-27 Message %1 Description This error occurs when the HDL Compiler requires a constant value, but can not calculate it. For example, the actual parameters in a VHDL generic map or Verilog parameter binding must be constant. This error occurs if you supply a VHDL signal, or Verilog wire value instead. What Next Change the value to one that can be computed at compile-time. Computable values include: constants, literals, generics, parameters, and expressions that depend only on these. ,~HDL-281 Message %1 Description Check the condition used in branch constructs (for example, "if then else" case). If a branch has an asynchronous set/reset assignment, each variable appearing in the branch's conditional expression must have the asynchronous set/reset attribute. In nested branch constructs, the condition for the else branch includes negation for the if branch. F|8,HDL-282 Message %1 Description Check the condition used in branch constructs (for example, "if then else" case) inside a clocked process. If a branch has a synchronous set/reset assignment, each variable appearing in the branch's conditional expression must have the synchronous set/reset attribute. In nested branch constructs, the condition for the else branch includes negation for the if branch. ,HDL-283 Message %1 Description Check the condition used in branch constructs (for example, "if then else" case) inside a process. If a branch has an asynchronous set/reset assignment, each variable appearing in the branch's conditional expression must have the asynchronous set/reset attribute. In nested branch constructs, the condition for the else branch includes negation for the if branch. F|8,HDL-284 Message %1 Description Check the condition used in branch constructs (for example, "if then else" case) inside the process. If a branch has a synchronous set/reset assignment, each variable appearing in its conditional expression must have the synchronous set/reset attribute. In nested branch constructs, the condition for the else branch includes the negation of that for the if branch. ,GHDL-285 Message %1 Description Both master and slave processes must have labels. A master process must be attributed with the label of the slave process. Similarly, a slave process must be attributed with the label of the master process. What Next Check the labels of master and slave processes, and make sure they match. F|8,HDL-287 Message %1 Description A pair of latches defined as a master-slave latch cannot be paired because the data input of the slave latch does not connect directly to the output of the master latch. -HDL-288 Message %1 Description A pair of latches defined as a master-slave latch cannot be paired because their asynchronous set/reset conditions are not the same. #;8-HDL-289 Message %1 Description A pair of latches defined as a master-slave latch cannot be paired because their asynchronous set conditions are not the same. !- HDL-28 Message %1 Description This error occurs where the HDL Compiler expects a value but finds something else (such as a type). Legal values include: constants, variables, signals, regs, wires, strings, and literals. What Next Change the operand to a value. G|82-HDL-290 Message %1 Description A pair of latches defined as a master-slave latch cannot be paired because their asynchronous set/reset conditions are not the same. A-HDL-292 Message %1 Description A pair of flip-flops defined as a master-slave flip-flop cannot be paired because their asynchronous reset conditions are not the same. G|8P-HDL-293 Message %1 Description A pair of flip-flops defined as a master-slave flip-flop cannot be paired because their asynchronous set conditions are not the same. _-HDL-294 Message %1 Description A pair of flip-flops defined as a master-slave flip-flop cannot be paired because their asynchronous data load conditions are not the same. G|8n-HDL-295 Message %1 Description A pair of flip-flops defined as a master-slave flip-flop cannot be paired because they are loaded with different asynchronous data.  }-HDL-296 Message %1 Description A pair of flip-flops defined as a master-slave flip-flop cannot be paired because their asynchronous set/reset conditions are not the same. G|8!-HDL-297 Message %1 Description The only synchronous data loaded on the slave flip-flop must be the state output of the master flip-flop. "-HDL-298 Message %1 Description The only synchronous data loaded on the slave flip-flop must be the state output of the master flip-flop. G|8#-HDL-299 Message %1 Description The only synchronous data loaded on the slave flip-flop must be the state output of the master flip-flop. $-HDL-29 Message %1 Description This error occurs where the HDL Compiler expects a type but finds something else (such as a variable). What Next Change the operand to a type. G|8%-?HDL-2 Message %1 Description The compiler for your VHDL or Verilog HDL description could not read in the primitive package vhdl.prims or verilog.prims. This occurs when the primitive package is from a previous version of the Synopsys software release. What Next Reinstall the current version of Synopsys software. &-hHDL-300 Message %1 Description Cannot tap off the internal state of a master-slave latch/flip-flop. G|8'-{HDL-301 Message %1 Description The pair of latches defined as a master-slave latch is not really a master-slave latch. (-HDL-302 Message %1 Description The pair of flip-flops defined as a master-slave flip-flop is not really a master-slave flip-flop. $;8).HDL-303 Message %1 Description A latch (flop-flop) inferred in a master process does not directly drive any latch (flop-flop) in the matching slave process to form a master-slave latch (flip_flop). *.HDL-304 Message %1 Description A latch (flop-flop) inferred in a slave process is not directly driven by any latch (flop-flop) in the matching master process to form a master-slave latch (flip-flop). G|8+&.~HDL-305 Message %1 Description The attributed asynchronous set/reset can be attached only to a port or a variable/signal. ,5.}HDL-306 Message %1 Description The attributed synchronous set/reset can be attached only to a port or a variable/signal. &;8-D.HDL-307 Message %1 Description The variable hdlin_check_no_latch directs the read command to ensure no latch is inferred in the HDL file. .S.<HDL-308 Message %1 Description See VE-109 or VHDL-2252. *;8/b.HDL-30 Message %1 Description This error occurs where the HDL Compiler expects a string but finds something else (such as a variable). What Next Change the operand to a string. 0s.HDL-312 Message %1 Description Because of the nature of the resource sharing problem, the search space grows quickly as the number of operations increase. When running in timing driven resource sharing mode, this results in a large number of calls to the timing verifier. As a result, this can cause very long run times. What Next If you turn resource allocation and resource implementation to area only, the performance should increase significantly. This can be done either with the hlo_resource_allocation and hlo_resource_implementation variables, or it can be done with the set_resource_allocation and set_resource_implementation commands on a design by design basis (maybe included in an embedded script for the designs that you wish to run in area based mode). :;81.HDL-31 Message %1 Description This error occurs when a subroutine is supplied less input arguments than it expects. What Next Compare the subroutine declaration with the call identified in the error message. Change the arguments in the call to match the definition. 2.3te value. process 1 begin if (c1) Q = high-impedance; else if (c2) Q = d; end process 2 begin W = Q; end <;83.2HDL-320 Message %1 Description An HDL description similar to the following example may cause a mismatch between RTL simulation and a gate-level simulation of the netlist resuling from synthesis. Discrepancy for the value of 'W' may occur if in simulation cycle t-1 'c1' is Logic1, and in simulation cycle t both 'c1' and 'c2' are Logic0. if (c1) Q = high-impedance; else if (c2) Q = d; W = Q; The HDL description in the next example may cause a mismatch between RTL simulation and gate-level simulation of the netlist resulitgng from synthesis. Discrepancy for the value of 'W' may occur if in simulation cycle t-1 both 'c1' and 'c3' are Logic1, and in simulation cycle t both 'c1' and 'c3' are Logic0. if (c1) Q = high-impedance; else if (c2) Q = d1; else Q = d2; if (c3) X = Q; W = X; What Next Separate the statement into two processes. One process assigns the three-state value and the other process reads the three-sta4.HDL-321 Message %1 Description An HDL description similar to the following example is beyond synthesis policy. for (i = 0; i<loop_max; i = i + 1) begin ... i = loop_max; // exit the loop ... end What Next Use "disable" statement to exit a loop. begin : my_loop for (i = 0; i<loop_max; i = i + 1) begin ... disable my_loop; // exit the loop ... end end ?;85.HDL-322 Message %1 Description The bus_naming_style variable variable has been incorrectly defined. It should be of the type "%s_%d". What Next Define the variable to be something like "%s_%d", or dont define it all and the default will be used. 6/HDL-325 Message %1 Description Synopsys does not support constant propagation on a constant larger than 32 bits. This error occurs when a constant needs to be expanded to a value greater than 32 bits. In the following example, constant 'h100 needs to be expanded to 64 bits wire [63:0] sum; assign sum = 127 + 'h100; What Next Use a temporary variable within 32 bits range, such as in the following example: wire [31:0] temp; wire [63:0] sum; assign temp = 127 + 'h100; assign sum = temp; G;87$/HDL-326 Message %1 Description Synopsys does not support enumeration type definition in a VHDL generate statement. In the following example, the type definition of STATE_TYPE is not supported. architecture a of e is begin G: for copy in 0 to 1 generate P : process type STATE_TYPE is (S1, S2); variable state : STATE_TYPE; begin if (c = '1') then state := S1; else state := S2; end if; end process P; end generate G; end a; What Next Move the type definition from the generate statement to the architecture declaration region, as in the following example: architecture a of e is type STATE_TYPE is (S1, S2); -- new location begin G: for copy in 0 to 1 generate P : process variable state : STATE_TYPE; begin if (c = '1') then state := S1; else state := S2; end if; end process P; end generate G; end a; 8Z/#HDL-327 Message %1 Description In the following example, the signal temp_out connected to the port Y is too wide when represented in hardware. architecture A of E is component C1 port (A : integer range 0 to 15; Y : integer range 0 to 15); end component; signal temp_in : integer range 0 to 15; signal temp_out : integer range 0 to 31; begin U1: C1 port map (A => temp_in, Y => temp_out); end A; What Next Define a temporary signal/variable with the proper bit width. architecture A of E is component C1 port (A : integer range 0 to 15; Y : integer range 0 to 15); end component; signal temp_in : integer range 0 to 15; signal temp_out : integer range 0 to 31; signal temp : integer range 0 to 15; begin temp_out <= temp; U1: C1 port map (A => temp_in, Y => temp); end A; I89/%HDL-328 Message %1 Description In the following example, the signal temp_out connected to the port Y is too narrow when represented in hardware. architecture A of E is component C1 port (A : integer range 0 to 15; Y : integer range 0 to 31); end component; signal temp_in : integer range 0 to 15; signal temp_out : integer range 0 to 15; begin U1: C1 port map (A => temp_in, Y => temp_out); end A; What Next Define a temporary signal/variable with the proper bit width. architecture A of E is component C1 port (A : integer range 0 to 15; Y : integer range 0 to 31); end component; signal temp_in : integer range 0 to 15; signal temp_out : integer range 0 to 15; signal temp : integer range 0 to 31; begin temp_out <= temp; U1: C1 port map (A => temp_in, Y => temp); end A; :/HDL-32 Message %1 Description This error occurs when a subroutine is supplied more input arguments than it expects. What Next Compare the subroutine declaration with the call identified in the error message. Change the arguments in the call to match the definition. M;8;/< B in CI in Z out ADD_TC_OP A in B in Z out . . . </;HDL-330 Message %1 Description The formal parameter names of the subprogram do not match those of the synthetic operator defined by the map_to_operator pragma. What Next When using map_to_operator, make sure the formal parameter names of the subprogram matches those of the synthetic operator defined by the map_to_operator pragma. The match is also case-sensitive. To check the port names of a synthetic operator, use the report_synlib command. For example: dc_shell> read standard.sldb dc_shell> report_synlib standard.sldb **************************************** Report : library Library: standard.sldb Version: v3.1a Date : Wed Jun 29 06:50:37 2001 **************************************** Library Type : Synthetic Tool Created : v3.1a Date Created : Dec. 16, 1776 Library Version : 3.1 Operators: Operator Ports Dir ---------------------------------------------------------------------- ADD_TC_CI_OP A in I8=/HDL-33 Message %1 Description This error occurs when a subroutine call supplies less output arguments than are defined. What Next Compare the subroutine declaration with the call identified in the error message. Change the arguments in the call to match the definition. >0HDL-34 Message %1 Description This error occurs when a subroutine call supplies more output arguments than are defined. What Next Compare the subroutine declaration with the call identified in the error message. Change the arguments in the call to match the definition. H|8?0 HDL-350 Message %1 Description The parameter value is not acceptable in this particular context. The usual cause is a syntax error, value of incorrect type, or value out of bounds. You may also find that the value being parsed is either shorter of longer than you expect. Perhaps the value reported above was intended to represent two values. In this case, make sure that you separate your parameter values by commas, and make sure that your parentheses and quotes match. What Next Check the expected parameter type and syntax carefully. @#0HDL-351 Message %1 Description A value was specified for an unconstrained array, but the value is not legal because the number of bits is not a multiple of the array element size. What Next You must specify a number of bits that is a multiple of the array element size. P;8A40HDL-352 Message %1 Description The value specified is not legal because it is too large or too small for the parameter's type. What Next You must specify a number of bits that exactly fits the type. BE0HDL-353 Message %1 Description This message indicates that no .typ file can be found for the specified type. Possible reasons for this situation might be that no .typ file has been created for this package; or that the .typ file was removed from the design library. What Next Create the .typ file using the create_types executable. Alternatively, you can change the types of the generic parameters to use types in the VHDL standard package; the types in the VHDL standard package are built in, so no .typ file is needed for those types. V;8CV0HDL-354 Message %1 Description The directory cannot be accessed. It either does not exist or is protected. What Next Check the value of the dc_shell variable that sets the path to the directory. Dg0E that uses the package.  V;8Eg0DHDL-360 Message %1 Description This warning occurs when the hdlin_files variable is used. This variable is supported for v3.3a and v3.3b but not for subsequent releases. Please refer to the What Next section below for the solution. What Next The variable hdlin_files specifies a list of file pathnames to be used by the read -format vhdl or read -format verilog commands. The files specified in hdlin_files are read before files specified in the read command. This variable is normally used to list VHDL source files that contain packages used by the current_design. Instead of using hdlin_files, use the analyze command to analyze any packages currently specified in hdlin_files. The analyze command is a better solution for the following reasons: You can analyze packages to different design libraries via the -w option of analyze. When analyze is used, packages are not analyzed multiple times, thereby saving time. Any VHDL packages listed in hdlin_files are input each time a design is readF{0HDL-361 Message %1 Description This warning occurs when the hdlin_source_to_gates_mode variable is used. This variable is obsolete with v3.3a. What Next Remove this variable from your script to disable this warning message. ];8G0+HDL-362 Message %1 Description The design symbol corresponding to the cell's reference can not be found in the symbol table. This may happen if you are using pragmas or synopsys directives, ie. translate_on/off or synthesis_on/off. What Next Check the pragmas or synopsys directives for typos. H0HDL-36 Message %1 Description This error occurs when you try to assign an unconstrained value to something. All arrays must be constrained before you use them. What Next Place a constraint on the value. H|8I0JHDL-370 Message %1 Description HDL Compiler assumes that all the conditions which are not covered cannot occur in practice. This means that these conditions are treated as don't cares, which may result in mismatches between synthesis and simulation. Following is an example that will result in this mismatch: module test (a, b, c, d); input a, c, d; output b; reg b; always @( a or d or c) begin case (a) 1'b0: b = d; endcase case (a) // synopsys full_case 1'b1: b = c; endcase end endmodule The second case statement is indicated as a full case, but the case when a = 1'b0 is not covered. This means that this condition can never occur, so HDL Compiler treats it as a don't care condition. As a result, the first case statement becomes redundant and is optimized out. The compiler assumes that all the conditions which are not covered cannot occur in practice. This means that these conditions are treated as don't cares which may affect the logic generated by other sJ0I~tatements. What Next Specify all the possible branches in the case statement, if you want to avoid a simulation mismatch. b;8K0lHDL-371 Message %1 Description There is more than one case-item that evaluates to true in the case statement with the parallel_case directive. This may lead to logic which is not the same as the simulated description. The use of the parallel_case directive under these circumstances is discouraged. Following is an example of this: module test (c[1:0],y); input [1:0] c; output y; reg y; always@(c) begin case {c[1:0]} //synopsys parallel_case 2'b1x: y = 0; 2'bx1: y = 1; endcase end endmodule For this case statement, if c = 2'b11, y = 0 in simulation, but in synthesis both case-items are executed, so y = 1. For the condition c = 2'b11, HDL Compiler assumes the output is a don't care. What Next Rewrite the conditons of this case statement in such a way that the different branches do not overlap any more, or don't use the parallel_case directive. L0HDL-37 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. m;8M1HDL-380 Message %1 Description The variable hdlin_dont_infer_mux_for_resource_sharing is set to true causing this MUX_OP not to be inferred. This MUX_OP is connected to two or more synthetic operators, which can not be shared by a MUX_OP. (They might be sharable otherwise.) What Next Set hdlin_dont_infer_mux_for_resource_sharing to false, or re-write the case statement as to not share synthetic operators. N16HDL-381 Message %1 Description The variable hdlin_dont_infer_mux_for_resource_sharing is set to false and a MUX_OP was inferred for a case statement that has two or more synthetic operators. What Next Set hdlin_dont_infer_mux_for_resource_sharing to true, or don't infer a MUX_OP for this case statement. };8O'1P end if; when "10" => DOUT <= DIN(2); when "11" => DOUT <= DIN(0); when others => DOUT <= DIN(2); end case; What Next Don't infer a MUX_OP for this "case" statement. P'1QOOUT <= DIN(2); end case; 5. Nested conditionals Nested conditionals refer to "if" statements inside "case" statements and "case" statements inside "case" statements ("case" statements inside "if" statements are not supported for MUX_OP inference). The inner "if" or "case" condition becomes one of the select lines to the MUX_OP, so data inputs to the MUX_OP are duplicated to size the MUX_OP according to the number of select lines. The logic could be more optimal if MUX_OPs were not inferred for nested conditionals. Following are examples of "if" statements nested in "case" statements: Verilog ------- case (SEL) 2'b00: DOUT <= DIN[0]; 2'b01: if (DIN[0]) DOUT <= DIN[1]; else DOUT <= DIN[0]; 2'b10: DOUT <= DIN[2]; 2'b11: DOUT <= DIN[0]; endcase VHDL ---- case SEL is when "00" => DOUT <= DIN(0); when "01" => if (DIN(0) = '1') then DOUT <= DIN(1); else DOUT <= DIN(0); };8Q'1RPMissing assignment to DOUT when "11" => DOUT <= DIN(0); DOUT2 <= DIN(0) when others => DOUT <= DIN(2); DOUT2 <= DIN(2); end case; 4. Use of "dont_cares" The use of "dont_cares" ("x") in a "case" statement branch results in duplicate inputs to the inferred MUX_OP. If a MUX_OP is not inferred, the logic can be optimized. Following are examples of "case" statements that result in this message: Verilog ------- case (SEL) case (SEL) 2'b00: DOUT = DIN[0]; 2'b00: DOUT = DIN[0]; 2'b0x: DOUT = DIN[1]; OR 2'b01: DOUT = DIN[1]; 2'b10: DOUT = DIN[2]; 2'b10: DOUT = 1'bx; 2'b11: DOUT = DIN[0]; 2'b11: DOUT = DIN[0]; endcase endcase VHDL ---- case SEL is when "00" => DOUT <= DIN(0); when "0X" => DOUT <= DIN(1); when "10" => DOUT <= DIN(2); when "1X" => DOUT <= DIN(0); when others => DR'1SQmissing assignments in a "case" statement branch result in duplicate inputs to the inferred MUX_OP. If a MUX_OP is not inferred, the logic can be optimized. Following are examples of "case" statements with missing assignments that result in the HDL-382 message. These examples infer two MUX_OPs, one for the output DOUT and one for DOUT2. Notice, an assignment to DOUT is missing in one of the branches, which results in the HDL-382 message. Verilog ------- case (SEL) 2'b00: begin DOUT = DIN[0]; DOUT2 = DIN[0]; end 2'b01: begin DOUT = DIN[1]; DOUT2 = DIN[1]; end 2'b10: DOUT2 = DIN[2]; // Missing assignment to DOUT 2'b11: begin DOUT = DIN[0]; DOUT2 = DIN[0]; end endcase VHDL ---- case SEL is when "00" => DOUT <= DIN(0); DOUT2 <= DIN(0); when "01" => DOUT <= DIN(1); DOUT2 <= DIN(1); when "10" => DOUT2 <= DIN(2); -- };8S'1TR "00" => DOUT <= DIN(0); when "01" => DOUT <= DIN(1); when others => DOUT <= DIN(2); -- covers "10" and "11" branches end case; 2. Missing case branches Missing branches in a "case" statement in Verilog (all "case" statements need to be completely specified in VHDL) result in duplicate inputs to the inferred MUX_OP since all branches of the "case" statement are enumerated. If a MUX_OP is not inferred, the logic can be optimized. This is also true if the "case" statement uses the Synopsys "full_case" directive. Following is an example: Verilog ------- case (SEL) case (SEL) //synopsys full_case 2'b00: DOUT <= DIN[0]; 2'b00: DOUT <= DIN[0]; 2'b01: DOUT <= DIN[1]; OR 2'b01: DOUT <= DIN[1]; 2'b10: DOUT <= DIN[2]; 2'b10: DOUT <= DIN[2]; endcase endcase 3. Missing assignments Similar to missing "case" branches, T'1SHDL-382 Message %1 Description A MUX_OP has been inferred for a case statement that has an incomplete specification. Because MUX_OP's are hierarchical (the logic is in a separate level of hierarchy), this may result in a nonoptimal design. The following five "case" statement coding styles result in this message: Default branch A default branch refers to an "others" statement in a VHDL "case" statement or a "default" statement in a Verilog "case" statement. When a default branch covers more than one possible value, the inputs to the inferred MUX_OP are duplicated for the branches that are not covered in the "case" statement. The logic could be more optimal if a MUX_OP was not inferred. Following are examples of "case" statements that contain default branches covering more than one possible value:  Verilog ------- case (SEL) 2'b00: DOUT = DIN[0]; 2'b01: DOUT = DIN[1]; default: DOUT = DIN[2]; // covers 2'b10 and 2'b11 branches endcase VHDL ---- case SEL is when;8U1HDL-383 Message %1 Description A attempt to infer a MUX_OP from a case statement with a branching factor larger than hdlin_mux_size_limit was attempted. This is usually the result of nested if or case statements with disjoint supports. It is best to not infer a MUX_OP in these situations, for then the optimizer will be able to effectivly optimize the assignments. What Next Increase hdlin_mux_size_limit, rewrite the case statement to avoid the large branching factor, or do not infer a MUX_OP. V1HDL-384 Message %1 Description A hdlin_infer_mux setting of "none" will override a local infer_mux attribute. What Next Set hdlin_infer_mux to "all" or "default." ;8W1HDL-385 Message %1 Description A hdlin_infer_mux setting of "al" will infer a MUX_OP for every possible case statement. What Next Set hdlin_infer_mux to "none" or "default" and use the infer_mux directive when necessary. X1HDL-386 Message %1 Description The number of enumeration encoding values defined via the ENUM_ENCODING attribute must match the number of enumeration values for the type. What Next Modify the number of enumeration or enumeration attribute values. ;8Y1HDL-387 Message %1 Description Certain invalid arguments (like a wire or function name) to pragma map_to_module can trigger this error message. The map_to_module pragma requires a module or component name as its argument. The following VHDL code demonstrates the problem: function FUNC; //synopsys map_to_module FUNC //synopsys return_port_name DBUS input DBUS; FUNC = DBUS; endfunction What Next Supply a module name or component name to the appropriate map_to_module pragma. Z2HDL-388 Message %1 Description It can happen if the use clause for the package in which the component is declared is surrounded by a synthesis off/on pair What Next Either remove the synthesis off/on pair enclosing the use clause or do not instantiate the component ;8[2HDL-389 Message %1 Description This message is issued when a design name exceeds 64 characters. Long design names may be a problem for external downstream tools. If the design contains parameters (generics), the design name is generated automatically based on the following variable settings: template_naming_style template_parameter_style template_separator_style  What Next If the design name was generated automatically, modify one or more of the variables listed above to reduce its length. \(2HDL-38 Message %1 Description This message indicates that the target of an assignment is not compatible with the assigned value. In VHDL, you may assign only between closely related types of equal size. What Next Check the sizes of the source and target of the assignment. If they differ, then make them the same. If they already are the same size, then use a type conversion to change the source type into the target type. I|8]92HDL-390 Message %1 Description This statement contains HDL constructs that are outside of the "turbo" subset. The statement cannot be accelerated and may result in excessive run time to elaborate the containing module. What Next Refer to the "turbo" subset document to determine what prevents the statement from being accelerated. Modify the HDL code to adhere to the "turbo" subset. ^J2UHDL-391 Message %1 Description This error occurs when a net has the same name as an other object in your design (net, instance, etc). What Next Generally, the culprit is in the bus_naming_style. Choosing a poor bus_naming_style can cause this error: bus_naming_style=%s%d is problematic. Try the default bus_naming_style=%s_%d instead. ;8_[20HDL-392 Message %1 Description This error occurs when a net coming from (or getting to) a sequential element contains a loop. What Next Typically, this error signals that some simulation statements remain in the HDL code. For example: CLK <= not CLK after 10 ns; process(CLK) begin if CLK'event and CLK='1' then B <= A; end if; end process; will create a loop on the CLK net. The simulation-only statements should be isolated with synthesis_on and off directives, like in: -- synopsys synthesis_off CLK <= not CLK after 10 ns; -- synopsys synthesis_on `o2HDL-393 Message %1 Description A MUX_OP was not inferred for a case statement that had too few unique assignments, as this may have negatively affected elaboration time and quality of results. This situation arises when many assignments of a case statement are missing or identical. Discrete logic may be more desirable than a MUX_OP. For a more detailed description of incompletely specified case statements, see HDL-382. What Next Don't infer a MUX_OP for this "case" statement. ;8a2HDL-394 Message %1 Description The following example shows an unconditional concurrent assignment to tristate value in Verilog. module e(m); output m; assign m = 1'bz; endmodule The following example shows an unconditional concurrent assignment to tristate value in VHDL. library IEEE; use IEEE.std_logic_1164.all; entity E is port(m : out std_logic); end E; architecture A of E is begin m <= 'Z' ; end A; Since the output port 'm' is always driven to tristate value, HDL Compiler will leave the port unconnected. Example Message Warning: Unconditional concurrent assignment to tristate in routine e line 6 in file 'b.v', may not result in hardware. (HDL-394) b2c n1, in2, in3 : in bit ; c1, c2 : in boolean ; out1 : out bit ); end foo; architecture bar of foo is begin process ( in1, in2, in3, c1, c2 ) begin if (c1 or c2) then out1 <= in1; else if (c1 and c2) then out1 <= in2; else out1 <= in3; end if; end if; end process; end bar; Example Message Warning: The statement in routine e line 6 in file 'b.v', is never reached. (HDL-395) ;8c2bHDL-395 Message %1 Description HDL Compiler will automatically eliminate unreachable statements. The following example shows an unreachable statement in Verilog. The statement: 'out1=in2' is never reached. This is because the first condition '(c1 | c2)' will always be true when the condition '(c1 & c2)' is true. Conversely, if '(c1 | c2)' is false, '(c1 & c2)' has to be false. module foo(in1, in2, in3, c1, c2, out1); input in1, in2, in3, c1, c2; output out1; reg out1; always @(in1 or in2 or in3 or c1 or c2) begin if (c1 | c2) out1=in1; else if (c1 & c2) out1=in2; else out1=in3; end endmodule The following example shows an unreachable statement in VHDL. The statement: 'out1 <= in2' is never reached. This is because the first condition '(c1 or c2)' will always be true when the condition '(c1 and c2)' is true. Conversely, if '(c1 or c2)' is false, '(c1 and c2)' has to be false. entity foo is port( id2|HDL-396 Message %1 Description HDL Compiler does not remove the feedbacks for latches or the asynchronous feedbacks for latches. The following examples illustrate the cases mentioned above. The first has latch whose output is being fed back in its input module foo(in1,c1, c2, out1); input in1,c1, c2; output out1; reg out1; always @(in1 or c1 or c2) begin if (c1) out1=in1; else if (c2) out1=out1; // This statement results in a feeback in the latch end endmodule The second example shows a flip-flop which has an asynchronous feedback module foo(in1,c1, clk, out1); input in1,c1, clk; output out1; reg out1; always @(posedge clk or posedge reset) begin if (reset) out1=out1 // This statement results in a feeback in the latch; else out1=in1; end endmodule ;8e3HDL-397 Message %1 Description This error is issued when some buffers or inverters form a combinational feedback loop in boundary logic. For example, the following Verilog description is invalid because the CLK input of the flip-flop has a feedback loop. CLK = ~CLK; always@(posedge CLK) begin Q = D; end What Next Check the HDL description and remove the combinational feedback loop. f'3HDL-398 Message %1 Description A loop index is used under one set of conditions, but remains uninitialized when used under another set of conditions. This can happen when moving code from a for loop in one "if" branch into the "else" branch. Once a variable is used as a loop iterator, it is handled as a "loop index" for the rest of its scope. What Next The most likely cause is code moved outside a for loop. In this situation, the for loop probably needs to be duplicated in both places to properly initialize the loop index. ;8g93HDL-399 Message %1 Description This message indicates that parameters to STD_MATCH have different lengths. Result will be FALSE. hH3HDL-39 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. I|8iY3HDL-3 Message %1 Description This message indicates that an HDL Compiler primitive is missing from the installation of the Synopsys software. It can occur when trying to mix system files from different releases. What Next Reinstall the Synopsys software. jj3HDL-400 Message %1 Description This message indicates that clock signal is not in the sensitivity list which could cause a simulation and synthesis mismatch. ;8ky3HDL-401 Message %1 Description The default setting for resource implementation has been changed from area_only to use_fastest. If the resource allocation is not performed in constraint driven mode the fastest implementation will always be selected. What Next If you do not want the fastest implementation to be selected set resource implementation to area_only or constraint_driven. l3-HDL-402 Message %1 Description Each synthetic library module (e.g. DW01_add) needs at least one implementation (e.g. rpl) to be usable for synthesis. In this particular case no implementation is available for one module. Possible reasons for this are: dont_use statements have forbidden the use of all implementations that are in the synthetic library or the synthetic library itself is incomplete. What Next Check dont_use statements in your dc_shell scripts or look at your synthetic library source code, if you are using your own synthetic library. I8m3HDL-40 Message %1 Description This error occurs when the target of an assignment is not compatible with the assigned value. In VHDL, you may assign only between closely related types of equal size. What Next Check the sizes of the source and target of the assignment. If they differ, then make them the same. If they already are the same size, then use a type conversion to convert the source into the type of the target. n3HDL-41 Message %1 Description This error occurs when it finds an unexpected argument to a subroutine. For example, if enumeration literal with a "U" encoding is supplied to a boolean function, HDL Compiler will report that a "value" was expected, but an "unknown" was supplied instead. What Next Check the argument identified in the message, and change it to one the of the expected types. I|8o3HDL-42 Message %1 Description This error occurs if you omit the type specification on a port declaration. What Next Specify the type of the port. p3SHDL-43 Message %1 Description This error occurs when you attempt to take a slice out of a non-array. What Next Modify your description to convert the variable in question into an array. Examples Verilog: wire foo, bar; assign foo[1:3] = bar; /* foo is not an array. This will cause the error to occur */ J|8q3HDL-44 Message %1 Description HDL Compiler reports this error when it detects a difference in the bit-width of the arguments to a boolean operator. What Next Make the arguments the same width. r3iHDL-47 Message %1 Description This error occurs where HDL Compiler detects division by a constant value: zero. The zero may be entered directly, or, more commonly, it is the result of an expression. For example, the expression: (WIDTH/(M-N)) will divide by zero if both M and N are equal constants. What Next Remove the divide by zero from the expression. ;8s 4}HDL-48 Message %1 Description This error occurs where HDL Compiler detects a negative exponent. The exponent may be entered directly, or, more commonly, it is the result of an expression. For example, the expression: (2**(M-N)) will have a negative exponent when both M and N are constant, and N is a larger than M. What Next Remove the negative exponent from the expression. t4]HDL-4 Message %1 Description This error occurs when the condition tested in an 'if' statement does not evaluate to a Boolean (single bit). What Next Rewrite your description so that the condition tested in the 'if' statement is a Boolean (single bit). Example VHDL: process variable condition_expr: bit_vector (0 to 3); begin condition_expr := in_value; if (condition_expr) then -- use of condition_expr is incorrect out_value := in_value and previous_value; end if; J|8u;4HDL-50 Message %1 Description This error occurs when you use an object as though it were an array, when it was not declared that way. What Next Either declare the object as an array, or don't use it like an array. vL42HDL-51 Message %1 Description This error occurs when you index a non-array variable. What Next Modify your description to remove the attempt to index into the non-array variable. Examples Verilog: reg foo, bar; bar = foo[0]; /* Indexing into variable 'foo' is an error */ ;8wg4HDL-52 Message %1 Description This error occurs when an aggregate is used as a non-array. For example, HDL Compiler will error if you qualify an aggregate with an integer type. What Next Change the use of the aggregate to be consistent with its array type. xx4LHDL-53 Message %1 Description This error occurs when you use an array index construct on an object that was not declared as an array. For example, if X is declared as an INTEGER, the expression (X(1)) will get this error. This error occurs in Verilog when an object is declared as an enumerated type with the /* synopsys enum */ directive, and is then accessed with a bit select. What Next Either change the object type to an array, or don't perform an array index directly on it. One way to avoid array indexing is to assign the value to a temporary array and index the temporary. ;8y4HDL-54 Message %1 Description Currently, only integer values and integer ranges are supported with named associations in aggregates. This error occurs when something else is used. What Next Change the aggregate to include only integer values and/or integer ranges. z4HDL-55 Message %1 Description This error occurs when a slice of an array is assigned an expression that has a different bit-width. Usually this is the result of a problem in expression the calculates the slice range. In the following example, the target is one bit larger than the source: Z(A'width downto 0) <= A; The following shows one way to fix the problem: Z(A'width - 1 downto 0) <= A; What Next Modify either the source or target to make the widths equal. ;8{4HDL-56 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. |46HDL-57 Message %1 Description This error occurs when an operation that is supported only on arrays and ranges is used on something else. For example, the 'first attribute is supported only on array and ranges. The expression: (STATE'first) would get this error if STATE were declared as an enumerated type. The 'first attribute is not supported for synthesis on enumerated types yet, even though this is legal VHDL. What Next Change the object declaration to an array or range (integer) type. In the above example, STATE could be changed to an INTEGER subtype. J|8}4(HDL-58 Message %1 Description This error occurs when you use an unconstrained range. The bounds of a range must be fixed before it may be used to specify an array range or declare a new object. What Next Change your description so that a bound will be placed on the range before it is used. ~4HDL-5 Message %1 Description An increment of zero prevents a for or while statement from ever making progress. An infinite loop is not synthesizable. What Next Rewrite your description so that the loop statement has a non-zero increment. J|84(HDL-60 Message %1 Description This error occurs when you use an unconstrained range. The bounds of a range must be fixed before it may be used to specify an array range or declare a new object. What Next Change your description so that a bound will be placed on the range before it is used. 5HDL-61 Message %1 Description Use the keyword downto when the first value in the range is greater than the last value. Use the keyword to when the first value in the range is less than the last value. This error occurs these conditions are not met. What Next Rewrite your descriptions so the above conditions are met. Examples VHDL: signal my_bus : bit_vector ( 15 to 0 ); -- downto should be used here because 15 is greater than 0 J|85HDL-62 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. *5HDL-63 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. I8;5HDL-64 Message %1 Description This error occurs when an unconstrained value is assigned different sized values on separate branches of an "if" or "case". What Next Change the assignments so they agree on the bit-width assigned to the unconstrained value. L5HDL-65 Message %1 Description This error prefix is used by the primitive routines that implement the builtin VHDL and Verilog functions. What Next Find the part of your code that is identified by the message, and change it according to the message. I8]5HDL-66 Message %1 Description This error occurs when a function that determines if its input is a positive power of 2 is supplied a number less than or equal to zero. What Next Modify your description so that the input to this function is a positive number. n5!HDL-67 Message %1 Description This error occurs when identifiers or character literals listed by an enumeration type definition are not distinct. What Next Modify your HDL description so that each identifier or character literal is used only once in each enumeration type definition. ;85HDL-68 Message %1 Description You can specify encoding for enumerated data types using the enum_encoding attribute. The encoding must be valid in terms of the values that the attribute specifies for the enumeration. The enum_encoding attributemust also be valid in terms of the length of the encoding. This error occurs if either of these conditions is not met. What Next Modify the encoding specified for the enumeration to meet the above conditions. Examples VHDL: attribute enum_encoding: string; type color is (red, green); attribute enum_encoding of color: type is 00 1; -- the encoding string for red is two bits long; it should be one -- bit long. 5HDL-69 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. J|857HDL-6 Message %1 Description This warning occurs when the upper bound and lower bound specified for iteration are the same. This specification will cause the loop to iterate zero times. What Next This is only a warning. Rewrite your description if you intended a non-zero number of iteration for the loop. 5HDL-70 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. J|85HDL-71 Message %1 Description This error occurs when the value assigned to a target is smaller than the lower bound or bigger than the upper bound of the range defined for the target. What Next Modify your HDL description to make the allowable range larger. 5HDL-72 Message %1 Description This error occurs when the width specified for a slice operation on an array is less than zero. What Next Rewrite your HDL description so that the width specification is positive. ;85HDL-73 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. 5HDL-74 Message %1 Description This error occurs when no arguments are specifed for operators such as "and", "or", "xor" or "max". What Next Modify your HDL description to provide at least one argument to the operator. K|8 6HDL-76 Message %1 Description This error occurs when an attempt is made to use the 'others' construct is used as part of an association list on the left hand side of an assignment. What Next Modify your HDL description to remove this use of 'others' 6HDL-77 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. K|8-6?HDL-78 Message %1 Description This error occurs if a variable is declared to be of a type that is unconstrained(such as BIT_VECTOR). The VHDL compiler for synthesis requires that all the type of a variable be constrained. What Next Modify your HDL description to specify a constraint for the type of the variable. >6HDL-79 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. K|8O62HDL-7 Message %1 Description This warning occurs if the number of iterations specified in a loop statement is greater than 1,000. Large number of iterations can cause slow run times. What Next Check whether you intended such a large number of iterations for the loop. If not, modify your description. `6HDL-80 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. ;8q6Dxed-name' called from e line 11 in file 'e.vhd' (HDL-81) q6HDL-81 Message %1 Description If the design reported is called 'indexed-name', an array index in the reported line is non-integer. Enumerated types are not supported. Synopsys supports indices of any type of integer. entity e is end; architecture a of e is TYPE mytype IS (first, second ); TYPE my_type_array IS array (first to second) of integer range 0 to 7; SIGNAL this_index : mytype; SIGNAL this_array : my_type_array; SIGNAL other_array : my_type_array; begin other_array(first) <= this_array(this_index); -- this is line 11 end; What Next If the line reported in the error message contains an array whose index is not type integer, modify your VHDL so that the type is integer. If your VHDL does not have an array indexed by a non-integer type, contact your Synopsys support representative. SAMPLE Message Error: Can't find a design 'indexed-name' that has correct parameter profile (Could be a type mismatch) in call to 'indeK|86HDL-82 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. 6UHDL-83 Message %1 Description This error occurs if the file "vhdl.prims" (for VHDL descriptions ) or "verilog.prims" (for Verilog descriptions) cannot be found. This could be because of an error in installing Synopsys software on your machine. What Next Check to make sure that the software has been correctly and completely installed. K|86HDL-84 Message %1 Description This error occurs when a function that computes the logarithm of a number is supplied a negative number as its argument. What Next Provide a positive number as an argument for this function. 6"HDL-85 Message %1 Description This error occurs when a function is specified without specifying the function's subprogram. This error also occurs when you elaborate a design for which no architecture has been specified. What Next Provide the appropriate architecture or function body. K|86HDL-86 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. 6HDL-87 Message %1 Description This is a non-fatal internal error. What Next Contact your Synopsys support representative. ;86HDL-8 Message %1 Description This error can occur when a VHDL "exit" or Verilog "disable" referrs to something other than an enclosing loop. What Next Modify your HDL Source to "exit" or "disable" an enclosing loop. 7HDL-90 Message %1 Description This error occurs if the direction ('to' or 'downto') specified for a slice operation on an array does not agree with the direction specified in the definition of the array. What Next Modify the HDL description to correct the direction of the slice. ;8 7HDL-91 Message %1 Description This error occurs when the object for which an attribute is specified cannot be found. For example, if the arrival_time attribute for a port is specified and if the port does not exist in the design, then this error would occur. What Next Check your HDL description to see if you have misspelt the name of the object or specified an attribute for a non-existent object. 17HDL-92 Message %1 Description This error occurs if an incorrect number of values are specified for the EQUAL or OPPOSITE attributes. What Next Modify your HDL description to provide exactly two values to these attributes. J8B7"ple Example problem for VHDL comparisons between bit arrays of different widths: signal sigvec : std_logic_vector(2 downto 0); ... if (sigvec > "00") then -- even when sigvec is "000", it is greater than "00". -- this branch will always be taken. end if; B7HDL-93 Message %1 Description This warning prefix is used by the primitive routines that implement the builtin VHDL and Verilog functions. An example of when this message is issued is if the VHDL compares bit arrays of different widths. VHDL comparisons between bit arrays of different widths generate logic for dictionary order (VHDL LRM 7-4) rather than arithmetic ordering. For instance, "10" is considered greater than "011". Most significant bits are compared first, with missing least significant bits treated as null values (which are less than all other bit values). See "Relational Operators" in the VHDL Compiler Reference manual for more detail and examples. What Next Find the part of your code that is identified by the message, and change it according to the message. For comparisons between VHDL bit arrays of different widths, check that lexigraphic ordering ('dictionary order') is appropriate. If not, one operand should be altered to match the width of the other operand. ExamK|8a7HDL-94 Message %1 Description This error occurs when the number of elements specified for an aggregate is greater than the implicit size of the aggregate. What Next Modify your description to provide the appropriate number of elements. Examples VHDL: signal my_bus: bit_vector ( 0 to 3); my_bus <= (0, 1, 1, 0, 1); -- this is an error because five elements are specified. The aggregate's size is four [0,3}; so four elements should have been specified. w7HDL-95 Message %1 Description This error occurs when the number of elements specified for an aggregate are less than the implicit size of the aggregate. What Next Modify your description to provide the appropriate number of elements. Examples VHDL: signal my_bus: bit_vector ( 0 to 3); my_bus <= ('0', '1', '1'); -- this is an error because only three elements are specified. The aggregate's size is 4 [0,3] so four elements should be specified. ;87_ function f(a: in bit) return bit is begin return(f(a)); -- Infinite recursive call end; begin z <= f(a); end; /* Verilog */ module e(a,z); input a; output z; function f; input a; f = f(a); /* Infinite recursive call */ endfunction assign z = f(a); endmodule Example Message Error: Infinite recursion detected in routine f line 6 in file 't.v' called from f line 7 in file 't.v' called from f line 7 in file 't.v' called from f line 7 in file 't.v' ... 7HDL-96 Message %1 Description A function that calls itself is recursive. Recursive functions call themselves directly, or call others functions that eventually call back. Recursive functions usually check a condition that terminates the recursion. The number of nested calls made before termination is called the depth of the recursion. The HDL compiler allows recursive functions only if the depth of the recursion can be determined at read time. This error is invoked whenever HDL compiler can not determine the depth of a recursive call. What Next Modify the recursive function to make the recursive call only under a condition that will eventually prove false after a few nested calls. For example, you can add a parameter to the function that is decremented for each nested call. If you return immediately from the function when the parameter reaches zero, HDL compiler will allow the recursion. Examples -- VHDL entity e is port(a: in bit; z: out bit); end; architecture a of e is ;87HDL-97 Message %1 Description This error occurs if the type of an operand cannot be determined. What Next Modify your to HDL description to qualify the operand with its type. 7wait is added end process; end RTL; Verilog module correct (a, clk , b , enable); input [7:0] a; input clk, enable; output [7:0] b; reg [7:0] b; always begin @ (posedge clk) while (enable) begin @ (posedge clk); b <= a; end end endmodule Example Message Error: Non-static loop or event waits in only some branches detected in routine HDL_98 line 7 in file 'HDL_98.v' (HDL-98) ;87RTL; Verilog module HDL_98 (a, clk , b , enable); input [7:0] a; input clk, enable; output [7:0] b; reg [7:0] b; always while (enable) begin @ (posedge clk); b <= a; end endmodule What Next If it is an RTL description modify your description to include an event wait in each branch and loop in your description. If it is a behavioral description use command elaborate -s. In the following example, the above description is modified to include an event wait for the process. VHDL library IEEE; use IEEE.std_logic_1164.all; entity correct is port( a : in std_logic_vector(7 downto 0); clk : in std_logic; enable : in std_logic; b : out std_logic_vector(7 downto 0) ); end correct; architecture RTL of correct is begin process begin while (enable = '1') loop wait until clk'event and clk ='1'; b <= a; end loop; wait until clk'event and clk = '1'; -- this 7HDL-98 Message %1 Description This error occurs in one of two cases: (1) It is an RTL description and a process, loop, or branch within a loop was not broken with event waits and (2) It is a behavioral description and elaborated without -s option. Example The following example is an RTL description that triggers the HDL-98 error message. In the example, the while loop is broken with an event wait. However, the process must also be broken with an event wait. If enable = '0', the description doesn't have an event wait because there isn't one for the process. VHDL library IEEE; use IEEE.std_logic_1164.all; entity HDL_98 is port( a : in std_logic_vector(7 downto 0); clk : in std_logic; enable : in std_logic; b : out std_logic_vector(7 downto 0) ); end HDL_98; architecture RTL of HDL_98 is begin process begin while (enable = '1') loop wait until clk'event and clk ='1'; b <= a; end loop; end process; end K|898"HDL-99 Message %1 Description This error occurs when a construct that does not return a value is used in an expression. An example of such a construct is the 'task' construct in Verilog and the 'procedure' construct in VHDL. What Next Modify your HDL description to correct the error. J8HDL-9 Message %1 Description This error can occur when a VHDL "exit" or Verilog "disable" referrs to something other than an enclosing loop. What Next Modify your HDL Source to "exit" or "disable" an enclosing loop. T<8[8LBR-10 Message %1 Description This message indicates that the given environment variable has not been set. What Next Set the environment variable to a legal value. l8LBR-11 Message %1 Description This message indicates that the specified library name has been pre-defined by Synopsys; this name cannot be re-defined. What Next Use the define_design_lib command to define a library name that has not already been defined by Synopsys. ]<8}8LBR-12 Message %1 Description This message indicates that the the specified library name has been predefined by Synopsys; this name cannot be re-mapped. What Next Use the define_design_lib command to define a library name that has not already been defined by Synopsys. 8@LBR-13 Message %1 Description This message indicates that the specified library name has been predefined by Synopsys; this name cannot be used. What Next Use the define_design_lib command to define a library name that has not already been defined by Synopsys. Then map the logical library nameto that library name. e<887LBR-14 Message %1 Description This message indicates that the given design unit's type in the specified library does not match the expected type, probably because of a naming conflict between two different design unit types. What Next Ensure that all primary design units in the library have unique names. 8LBR-15 Message %1 Description This message indicates that the source file containing the given design unit is out of date, and will be re-analyzed. What Next This is only an informational message. The design will be re-analyzed automatically. n<88LBR-16 Message %1 Description This message indicated that you attempted to write a library file to an existing file that has the same name; this is not allowed. What Next Choose a unique filename for this library information. 8/LBR-17 Message %1 Description This message indicates that you attemped to write to the directory that is mapped to the working library; this directory is not writable. What Next For information on mapping between design libraries and paths, refer to the write_design_lib_paths command manual page. u<880LBR-18 Message %1 Description This message indicates that the program could not figure out where to write the results of the write_design_lib_paths command. What Next Set the specified environment variable, or use the -filename, or -dc_setup options when issuing the write_design_lib_paths command. 8LBR-19 Message %1 Description This message indicates that during an elaborate command, an entity was encountered which did not have any associated architecture analyzed for it. What Next Analyze an architecture for this entity and then re-issue the elaborate command. x<89LLBR-1 Message %1 Description This message indicates that the design unit given is not in the library specified. What Next The report_design_lib command can be used to determine the contents of a library. If the design unit is not present, re-analyze the design unit using the analyze command with the -library or -work option. 9LBR-20 Message %1 Description This message indicates the elaborate command was executed with the -architecture on a configuration. What Next Re-issue the elaborate command without the -architecture option. <8'9LBR-21 Message %1 Description This message indicates that parameter(s) have been specified for a design that does not require parameters. The parameters specified will be ignored when building the design. What Next Use the dc_shell command report_design_lib library_name to generate a report on the contents of the design library that contains the design. In the report table, an entry with a 'p' notation identifies a design that has parameters. Ignore this warning message if you have a DesignWare library module that requires parameter(s) to select a specific implementation but the implementation itself does not accept parameters. An example of this is an elaborated and compiled gate-level .db implementation. 99?LBR-22 Message %1 Description This message inidicates that you tried to map the given libraries to the same directory. This is illegal. What Next Re-map one of the libraries to a different directory using the define_design_lib command with the -path option, or specify the mapping in the .synopsys_vss.setup file. <8J9LBR-23 Message %1 Description The library manager tried to remove the specified file but couldn't. This should only happen if the permissions on the file are such that you do not have permission to remove it. What Next Check the permissions on the specified file. If appropriate, change them to allow you to remove the file in question. Otherwise contact your system administrator for assistance. [9LBR-24 Message %1 Description The specified db file does not contain the entity that was expected. What Next Rewrite the db file to the library, using the command "write -library". This produces a file in the format that dc expects. <8l9%LBR-25 Message %1 Description The specified db file contains multiple entities. db files stored in design libraries must contain only one entity per file. What Next Rewrite the db file to the library using the command "write -library". This produces a file in the format that dc expects. }9LBR-26 Message %1 Description An attempt was made to elaborate an entity out of a design library, and the elaboration failed. What Next The db file is probably corrupt. Regenerate the db file, and overwrite the existing file in the design library. <89xLBR-27 Message %1 Description Each design library is only allowed to have one architecture associated with a particular entity. As a result, when you write an architecture into a library, the system overwrites existing architectures. This message simply lets you know that the overwriting is in progress. What Next Do not take any further action regarding this message. 9LBR-28 Message %1 Description This message inidicates that the given design unit is out of date with respect to a design unit on which it depends. What Next Re-analyze the dependant design's source file. <89LBR-29 Message %1 Description It is illegal to have two design libraries mapped to the same directory. Doing so can cause library aliasing problems. What Next One of the two libraries must be mapped to a different directory. 9LBR-2 Message %1 Description This message indicates that a command was issued which tried to read from, or write to a library mapped to a directory for which the desired permissions are not set. What Next Check the permissions on the specified directory. <89LBR-30 Message %1 Description This error should never happen because it is impossible to create recursive dependencies amongst design units. This check is there simply for completeness to eliminate the chance of infinite recursion while checking design units. What Next Check the dependency hierarchy of the design unit that is in question. If you can find the recursion (which would be illegal vhdl), remove one of the links in the loop to prevent the recursion. 9LBR-31 Message %1 Description A logical library with the specified name has already been defined. Synthesis does not allow there to be logical and design libraries both specified with the same name. Example 1 .synopsys_vss.setup file: DW03: ./work DW03 > DEFAULT Example 2 .synopsys_vss.setup file: SOME_LIB > SOME_LIB SOME_LIB: ./work In example 1 DW03 is both a logical library and a design library. In example 2 SOME_LIB is both a logical library and a design library. What Next This is a limitation in the synthesis support of design libraries. As the error message states, you should be able to get the desired effect by using the ':' operator (or the define_design_lib command) to redefine the library in question. In example 1 the logical library DW03 can be renamed to something else like DW_03. In example 2 the line 'SOME_LIB > SOME_LIB' can be eliminated since it is implied by the line 'SOME_LIB: ./work'. <8:LBR-32 Message %1 Description When -update is specified, a .update file must be found in the directory of your HDL source. The given .update file was not found. The analyze command has failed. What Next Contact your part vendor to obtain the necessary .update file(s). :LBR-33 Message %1 Description When -update is specified, a .update file must be found in the directory of your HDL source. The .update file must have been generated using "analyze -create_update" on exactly the same HDL source file as you are using now. The HDL source file you are using has been modified, so the analysis failed. What Next Use the original HDL source file, or don't specify the -update flag. Contact your part vendor if you think you have been given the wrong .update or HDL source file. <8$:LBR-3 Message %1 Description This message indicates that the file containing the design unit has been modified since the last time the design unit was analyzed. What Next To avoid this warning in the future, re-analyze the file containing the design unit with the analyze command. 5:LBR-4 Message %1 Description This message indicates that the file which contains the design unit given cannot be located. What Next Ensure that the file in question has not been re-named or moved. <8F:'LBR-50 Message %1 Description This error occurs when the -parameters option of the elaborate command includes a combination of order-based and name-based parameter values, and all the order-based parameters are not specified before name-based parameters. It is possible that a syntax error has caused a named-base parameter to be accidentally treated as an order-based parameter. What Next Modify the -parameters option of the elaborate command so that all order-based parameters occur before name-based parameters; or, correct the syntax error. W:LBR-51 Message %1 Description This message indicates that the same parameter appears more than once in the parameter list specified when executing elaborate. Each parameter can be specified only once. Parameters are not case sensitive. You might have specified two names that differed only in case (upper and lower). What Next Specify the parameter only once. To ensure that each parameter name is unique, refer to the parameter syntax explanation in the elaborate manual page. <8i:LBR-5 Message %1 Description This message indicates that the design unit specified depends on more recently analyzed files. What Next Use the analyze command to re-analyze the file which contains the given design unit. z:WLBR-6 Message %1 Description This message indicates that you attempted to access a library which does not have a valid directory path associated with it. What Next For information on mapping between design libraries and paths, refer to the define_design_lib command manual page. Mapping can also be done via the .synopsys_vss.setup file. <8:>LBR-7 Message %1 Description This message indicates that the file could not be opened for writing. What Next For previously existing files, check the write permissions. When trying to create a new file, check the full directory path for existence, and ensure that the file name is not an existing directory name. :LBR-9 Message %1 Description This message indicates that the .mra file has been incorrectly modified, with extra character(s) after the architecture name, by a source other than this program. The .mra file should only contain a single architecture name per line, directly followed by a newline. What Next To avoid this warning in the future, re-analyze the design. This will automatically generate a new .mra file. G>8:VE-0 Message %1 Description A syntax or internal error has surfaced during verilog parsing. The message specifies where the error appeared and why it was issued. What Next Internal errors indicate a problem which should be reported to your Synopsys representitive. :VE-103 Message %1 Description A set/reset or multibit pragma was specified on the same signal more than once. For set/reset pragmas, a pragma may have been specified on the same block more than once. This warning is issued at the point where the duplicate pragma usage was detected. What Next Find the first usage of the pragma, then determine which use of the set/reset or multibit pragma can be removed. L>8:2VE-104 Message %1 Description When a pragma is defined for an object, an attribute is placed on the object. If the object cannot be found, this pragma has no effect. What Next Check HDL source to make sure that the object--usually a port, wire, or variable--is specified before the pragma is defined. :i+1) a[i] = 1'b1; /* Error */ for(i=1; i>=0; i=i-1) a[i] = 1'b1; /* OK */ end endmodule Q>8:VE-108 Message %1 Description This error occurs when you use a "<" or "<=" with a decrementing loop, or a ">" or ">=" with an incrementing loop. What Next Change the loop termination comparison to match the direction of the loop index. Example The follow example demonstrates all eight possible combinations of loop bounds, termination conditions, and index directions. The loops labeled "Zero Iterations" are legal, but they have no effect since the loop initialization already violates the termination condition. module test(a); output [0:1] a; reg [0:1] a; integer i; always @( a ) begin for(i=0; i<=1; i=i+1) a[i] = 1'b1; /* OK */ for(i=0; i<=1; i=i-1) a[i] = 1'b1; /* Error */ for(i=0; i>=1; i=i+1) a[i] = 1'b1; /* Error */ for(i=0; i>=1; i=i-1) a[i] = 1'b1; /* Zero Iterations */ for(i=1; i<=0; i=i+1) a[i] = 1'b1; /* Zero Iterations */ for(i=1; i<=0; i=i-1) a[i] = 1'b1; /* Error */ for(i=1; i>=0; i=i;VE-109 Message %1 Description Directive 'one_hot' indicates at most one object in its group can have a Logic1 value at any instance of time, all other objects must have a Logic0 value. Directive 'one_cold' indicates at most one object in its group can have a Logic0 value at any instance of time, all other objects must have a Logic1 value. This information is used when inferring sequential logic. What Next For a directive //synopsys one_hot "set, reset", add a block in the design like the following example. // synopsys translate_off always @(set or reset) begin if (set + reset > 1) $write("ONE-HOT violation for set, reset"); end // synopsys translate_on For a directive //synopsys one_cold "set, reset", add a block in the design like the following example. // synopsys translate_off always @(set or reset) begin if ({~set} + {~reset} > 1) $write("ONE-COLD violation for set, reset"); end // synopsys translate_on R>8);VE-10 Message %1 Description The same port has been declared with differing directions. What Next If the port needs to be used as both input and output, declare the port to be of type "inout". Example The declarations below seek to declare 'result' as both input and output: input [3:0] result; output [3:0] result; To resolve the conflict, declare the port as inout: inout [3:0] result; The port will allow input and output operations, and the VE-10 error message will no longer be triggered. @;VE-112 Message %1 Description What Next Create a label for the 'always' block in which you want to apply this directive. Use the directive after 'begin:label'. `>8P;VE-120 Message %1 Description The circuit synthesized by the (V)HDL Compiler can have a potential mismatch with simulation if a wire (signal in VHDL) or reg (variable) drives (through the use of the 'assign' construct in Verilog, '<=' construct in VHDL) more than one wire(signal) whose resolution is of type 'wired_and' or 'wired_or'. In the following example, 'a' drives two wires(signals) 'e' and 'f' which are of resolution 'wired_or'. Examples Verilog wor e,f; assign f = a; assign f = b & d; assign e = a; assign e = c & d; What Next Instantiate explicit buffers to do the assignment to the wor or wand net. Do not use the Verilog 'buf' construct. Use a GTECH BUF gate or a buffer from your target library Examples Verilog wor e,f; GTECH_BUF U1 (.A(a), .Z(f)); // assign f = a; assign f = b & d; GTECH_BUF U2 (.A(a), .Z(e)); //assign e = a; assign e = c & d; ;VE-121 Message %1 Description The circuit synthesized by the (V)HDL Compiler can have a potential mismatch with simulation if an assignment in verilog contains event. Examples Verilog q = @ (posedge ck) d; Only one reg will be inferred if above assignment is used. What Next Use the following assignments to replace above assignment if you want to have two regs inferred. reg temp; temp = d; @ (posedge ck); q = temp; l>8;IVE-122 Message %1 Description Some simulators may ignore the range specification and expand the parameter to 32 bits. The circuit synthesized by the (V)HDL Compiler can have a potential mismatch with simulation if range specification is used in parameter declaration. For the following example, the value of "out" from simulator may be 0, while (V)HDL Compiler gives the value 16. Example1 Verilog output [4:0] out; parameter [3:0] a = 0; assign out = {1'b1, a}; For the following example, the value of "a" from simulator may be 10, while (V)HDL Compiler gives the value 2. The leftmost bit is chopped out. Example2 Verilog parameter [2:0] a = 4'b1010; What Next Accordance between synthesis and simulation must be checked by the user where the bit width of the parameter is referred. ;VE-123 Message %1 Description The circuit synthesized by the (V)HDL Compiler can have a potential mismatch with simulation if an expression containing wire is assigned to a reg. Examples Verilog input a; reg p; reg q; wire x = p; always @(posedge CLK) p = a; q = x; end Two regs will be inferred for synthesis. While for certain simulation tools, it may simulate only as one reg. (e.g. VCS will simulate the above code as one reg) r>8;VE-124 Message %1 Description The value of the right-hand side is outside the range of the left-hand side. Example Verilog parameter [2:0] a = 14; parameter [2:0] b = 4'b1110; What Next Declare a proper range for the left-hand side. Or check the value on the right-hand side to ensure that the range of the left-hand side covers that of the right-hand side. ;VE-125 Message %1 Description FPGA attributes in Verilog should always be defined on the same line as the instance declaration. Examples DFF U1 (.D(D), .C(C), .Q(Q)); // synopsys attribute attr_name "attr_value" t>8 <VE-1 Message %1 Description The specified file cannot be opened, which is most likely caused by the file being outside the search_path. This error is also triggered if the file permissions prohibit read access. What Next If the file exists in the current directory, ensure "." is present in the search_path. For files in other directories, add the directory to your search_path. Permissions problems can be ruled out by trying to view the file in an editor. Errors of this variety are not specific to Verilog. <VE-21 Message %1 Description The sensitivity list contains both level-sensitive and edge-sensitive registers. Edge-sensitive registers are indicated by the use of either posedge or negedge in the sensitivity list. All registers in an always block must either be edge-sensitive or level-sensitive. What Next A mix of level- and edge-sensitive registers requires separate always blocks. Move the level-sensitive registers into their own always block. |>81<RVE-25 Message %1 Description This error occurs if a reg or wire that is not specified in the timing control of an 'always' block is tested inside an 'if' statement in the always block. In the example below, reset2 is tested in the 'if' statement but does not occur in the timing block (reset1 appear instead). Examples module err (d, reset1, reset2, clk, q); input d, clk; input reset1, reset2; output q; always @ (posedge clk or negedge reset1) if (! reset2 ) q = d; end endmodule What Next Introduce the offending reg or wire in the timing control of the 'always' block. T<uVE-41 Message %1 Description Typically this warning occurs when unusual characters are used to form a port name. The use of brackets in a port name is an example of when this warning can be triggered. HDL Compiler renames the original port so that it can process the design. What Next For port names containing brackets, change the name so it no longer uses brackets. >8e<TVE-50 Message %1 Description A comment, directive or dc_script crossed the end of file boundry, indicating it wasn't terminated appropriately. This problem likely involves an unbalanced "/*", which will need a terminating "*/". What Next For run-on comments or dc_script_begin, examine the lines immediately after the one specified in the error. Mark the boundry between code and comment with a terminating "*/". For (preprocessor) directives, its very likely an `ifdef or `else was not completed with an `endif. Determine what code should fit within the `ifdef, and end it with an `endif. w<AVE-52 Message %1 Description A missing or misformed include filename can trigger this error. Here is an example usage of `include: `include "myfile.v" What Next Provide the filename, if missing. Preface the filename with a double-quote ("), and place another double-quote after the last character in the filename. >8<"VE-53 Message %1 Description A circular dependency was found in the use of an `include directive. This error is issued to prevent a file from including itself in an endless loop. Breaking the need for an `include loop will avoid triggering this error. A file that directly includes itself most likely meant to include another file with a similiar name. What Next Examine the need for the nested `include. Most likely, several files all depend on each other. The dependencies should be split up so that one file does not depend on any of the others. This can be achieved by moving needed code or `defines to one central file. When one file no longer depends on the others, the corresponding `include(s) can be removed from that file. This should break the `include loop and avoid the VE-53 error. <VE-54 Message %1 Description This error occurs when RTL assignments and blocking delays are specified in the same module. RTL assignments are assignments made using the "<=" operator. Blocking delays are delays specified using the "#" construct (as in foo = #5 bar; or as in #7 foo = bar;). What Next If you need to use RTL assignments, remove the blocking delays from your description. (Delays are ignored by the synthesis tool.) 8P8<ld procedural assignment. always @(posedge clk) begin tmp1 = input1 + input2; output1 = tmp1; tmp1 <= input1 + input2; output2 <= tmp1; end The intent appears to be providing the value of (input1 + input2) on output1, and the same value should be delayed one clock cycle before appearing on output2. Since tmp1 is the target of both methods of assignment, a VE-57 error is triggered by the aforementioned HDL. To retain the same intent, a second variable is introduced which interacts with the RTL assignments: always @(posedge clk) begin tmp1 = input1 + input2; output1 = tmp1; tmp2 <= tmp1; output2 <= tmp2; end The previous example avoids targeting the same variable with RTL and procedural assignments. Register tmp1 is targeted by the procedural assignment, while new variable tmp2 is targeted by the RTL assignment. <cycles. In the netlist, this method of assignment shows up as flip-flop B getting its input from the output net of flip-flop A. The value held by flip-flop A will take one clock cycle to propagate to flip-flop B. A given register can only follow one of the assignment methods. The VE-57 error message indicates a single register is assigned with both procedural and RTL assignment methods. This usage does not clearly specify if the register's value should be available in the current cycle or the next cycle. What Next Decide if a register's value, when passed on, should be that of the current clock cycle or the next clock cycle. If only one method of assignment was intended, fix the unintended use of the other method of assignment. If both styles of assignment are needed, two variables are required in place of the original. One variable will be the target of procedural assignments and uses, while the other is used in RTL assignments. Example The following example illegally mixes RTL an>8<VE-57 Message %1 Description The two different methods of assignment are incompatible. Procedural assignments provide access to assigned values in the current clock cycle. A value passed along from variable A to variable B to variable C through a procedural assignment winds up with all three having the same value in every clock cycle. In the netlist, procedural assignments are indicated when the input net of one flip-flop is also connected to the input net of another. Both flip-flops will input the same value in the same clock cycle. Values generated by RTL assignment are passed on in the next clock cycle. An assignment from variable A to variable B takes place after one clock cycle, provided that variable A has previously been the target of an RTL assignment. An assignment from variable B to variable C will always take place after one clock cycle, since B was the target of an RTL assignment of variable A's value. Variable A will transmit its current value to variable C in two clock <VE-60 Message %1 Description The specified file cannot be opened, which is most likely caused by the file being outside the search_path. This error is also triggered if the file permissions prohibit read access. What Next If the file exists in the current directory, ensure "." is present in the search_path. For files in other directories, add the directory to your search_path. Permissions problems can be ruled out by trying to view the file in an editor. Errors of this variety are not specific to Verilog. >8<yVE-7 Message %1 Description Only continuous assignment is allowed for wire types. Most likely, a wire type was assigned inside an always block. What Next The assignment to a wire type should be moved outside the always block, or the assignment's target should be changed to a register type. Example The following example will trigger error VE-7: wire tmp; always @(inp) begin tmp = inp; ... end If continuous assignment is desired, move the assignment outside the always block. wire tmp; assign tmp = inp; always @(inp) begin ... end If the assignment inside an always block is appropriate, the target of the assignment should be changed into a register type. reg tmp; always @(inp) begin tmp = inp; ... end &='VE-95 Message %1 Description In a previous release, the HDL Compiler provided limited support for global references. This is no longer true. What Next Please rewrite your description without using globals. Normally, this can be done by passing signals through module inputs and/or outputs. >87=~VE-96 Message %1 Description Object redefined when it is not allowed What Next Change the name in the second definition H=VE-97 Message %1 Description Compiler directive used with wrong coupling. For example, an "`endif" is used without a corresponding "`ifdef" before it. What Next Delete the mismatched directive or add the missed one. >8Y=VE-98 Message %1 Description The same macro name is provided two different definitions, leading to a single macro name having different meanings in separate parts of the HDL. Although not an error, this is a potentially hard to find and confusing problem. What Next If the duplicate macro definition was accidental, provide a different name for one of the usages. If the duplicate usage is intentional, this warning can be avoided by performing an `undef of the macro name before each duplicate definition. k=HVHDL-10 Message %1 Description This warning is generated when the type needs to be renamed because of the illegal VHDL character. It is generated internally for the returned types of subprograms. What Next Check the returned type defined for the subprograms; if it is an anonymous type, try to change it to be a real type. N|8|=VHDL-11 Message %1 Description This warning is generated when there is more than one constraint set for the same port. It takes the first constraint you set. What Next Make sure the constraints are setting once, or the first constraint is the one you want. =VHDL-12 Message %1 Description This warning is generated when EQUAL and OPPOSITE attributes exist on multi-bit ports. What Next Make sure the attributes are consistently set for multi-bit ports. >8=VHDL-13 Message %1 Description This warning is generated when the identifier contains illegal VHDL character. What Next Please refer to VHDL reference manual and change it to legal VHDL character if you do not it to be renamed. =VHDL-15 Message %1 Description The variable vhdlout_conversion_functions should contains list of list which contains exactly three strings in it. They are "from_type", "to_type" and "function_name". What Next Type "help vhdlout_conversion_functions" for more details. >8=VHDL-16 Message %1 Description The write -f vhdl command is intended primarily for the creation of a simulation model of the contents of the dc_shell database. This error occurs if there is more than one bidirectional port (port mode "inout") in the same net. Note that a bidirectional port driving a bidirectional pin will not cause this error. This connectivity cannot be correctly modeled for simulation in VHDL, because it would require one assign statement for port A driving port B and one for port B driving port A. This circular assignment does not work. What Next The preferred remedy is to change the HDL source so that it does not contain more than one bidirectional port per net. The least preferred remedy is to use the dc_shell disconnect_net command to disconnect all but one of the bidirectional ports in the same net. Then re-write the design. If necessary, these ports can be reconnected manually in the resulting VHDL text file. =ut_single_bit = USER and vhdlout_preserve_hierarchical_types = VECTOR and The suggested remedy for this situation is to set vhdlout_preserve_hierarchical_types = USER To see the possible settings and their meanings, refer to the man page for the vhdlout_single_bit variable. With either of these two changes, no type conversions are created. If the above setting does not work, then it could be this port connects to an component pin that is buffer. >8=VHDL-17 Message %1 Description VHDLout encountered a bidirectional port when it was creating type conversion functions. Because information about the current direction of the signal is not available at any given time, it is not possible to create a working type conversion function for bidirectional signals. Hence, one does not know whether to convert for a source or a sink signal. Beyond looking at the port's mode, VHDLout also analyzes the net to see if the port is used both as a sink and a source. If it is used only as a unidirectional signal, VHDLout treats it as such and creates a type conversion for it. Of course, this error does not occur in that case. What Next Note that type conversion functions are created in two situations: vhdlout_single_bit = VECTOR and vhdlout_write_top_configuration = TRUE. To write a VHDL description for the design in this situation, change the setting of vhdlout_single_bit to "not equal VECTOR" or set vhdlout_write_top_configuration = FALSE. vhdlo=VHDL-18 Message %1 Description This warning is generated when vhdlout_target_simulator is set to an unknown simulater. What Next Reset vhdlout_traget_simulator to a valid simulator. >8=VHDL-19 Message %1 Description The warning is generated when vhdlout_target_simulator is set to a "xp" or "xp100" simulator and vhdlout_equations is set to TRUE. What Next Change vhdlout_equations to FALSE or change vhdlout_target_simulator.  >VHDL-1 Message %1 Description This error is generated when vhdlout_single_bit is not set to BIT and if there are no bus information, then the design probably came from a format that doesn't put bus information on, and the user will expect the ports to be bit-blasted anyways. What Next Try to read in a different format of netlist which can represent buses. They can be EDIF,Verilog, VHDL, etc. Or change vhdlout_single_bit to BIT. N|8>VHDL-2047 Message %1 Description Attributes that need to be applied to processes must occur inside of the architecture that contains them. What Next Move the attribute to inside of the architecture. />VHDL-2048 Message %1 Description The attribute '%s' is meant to apply to processes only, and the process defined could not be found. What Next Check the names of the processes and the definition of the attribute for errors. >8@>VHDL-2049 Message %1 Description The name attribute is only allowed to attribute certain classes. What Next Check to make sure that the attribute is applied to the correct object. Q>When this isn't possible, then "translate_off" parts of a construct that aren't part of VHDL syntax. In the modified example below, the "if", "then" and "else" constructs are all "translated", the "else" clause is interpreted to synthesis as a "null". Example 1 . . . temp := (others => "X"); if (svec /= temp) then if ( t > 20) then -- synthesize this RTL . . . else -- pragma translate_off assert (now < 20 ns) report "logic vector contains U, X, Z or W" severity error; -- pragma translate_on end if; . . . Example 2 . . . case (expr_1) is when value_1 => -- pragma translate_off . . . -- pragma translate_on when value_2 => . . . when . . . . . . end case; >8Q>VHDL-2060 Message %1 Description Only use the translate_on and translate_off pragmas on complete constructs, not on parts of constructs. For example, do not use these pragmas to comment out one of more branches of a "case" statement or the "if" construct as shown in the following examples. Example 1 . . . -- pragma translate_off if (Is_X(svec)) then assert (now < 20 ns) report "logic vector contains U, X, Z or W" severity error; else -- pragma translate_on if ( t > 20) then -- synthesize this RTL . . . -- pragma translate_off end if; -- pragma translate_on . . . Example 2 . . . case (expr_1) is -- pragma translate_off when value_1 => -- incomplete case statement missing this branch . . . -- pragma translate_on when value_2 => . . . when . . . . . . end case; What Next Modify the placement of translate_on and translate_off pragmas. When you use the translate_on and translate_off pragmas, use them around the entire "if"/"case" statement. >nVHDL-2092 Message %1 Description Simple configurations are currently supported for synthesis, the configuration you have used is too complex. What Next Use the following synopsys pragmas --synopsys synthesis_off --synopsys synthesis_on to control the text that is synthesized. All code between the two pragmas will be parsed for syntax, but not synthesized. >8>VHDL-2099 Message %1 Description The VHDL "assert" and "report" statements have no meaning for synthesis. These statements are ignored by HDL Compiler. >HDL is port ( a, b : in std_logic; r : inout std_logic); end M_VHDL; architecture test of M_VHDL is begin process ( a) begin r <= a; end process; process ( b) begin r <= b; end process; end test; Example where warning is correct. "BIT" is not a resolved type. This will cause problems in simulation. entity M_VHDL is port ( a, b : in bit; r : inout bit); end M_VHDL; architecture test of M_VHDL is begin process ( a) begin r <= a; end process; process ( b) begin r <= b; end process; end test; Example Message Warning: There are inout ports of type 'std_logic' that are multiply driven. The type 'std_logic' must be a resolved type or the vhdl will not simulate. (VHDL-20) >8>VHDL-20 Message %1 Description VHDLout cannot determine whether the port is of a resolved type. This warning is issued whenever a multiply driven inout port is found. What Next Check that the type reported in the message is a resolved type. If it is, ignore this warning. If the type is not resolved, two remedies exist. Modify the setting of vhdlout_single_bit or vhdlout_preserve_hierarchical_types as appropriate. Change the variable setting to "BIT" or "VECTOR." When necessary, VHDLout creates a resolved type. For more information on the use of these variables, see the appropriate man pages. Alternately modify your VHDL source to use a resolved type for the inout ports, recreate the design, and write again. Note that the warning is issued only once for each type. In a hierarchical design, multiple entities with the same problem may exist. Examples Example of warning that is safe to ignore. "std_logic" is a resolved type. library IEEE; use IEEE.std_logic_1164.all; entity M_V?iVHDL-2103 Message %1 Description Slang functions cannot have a return data-type that is unconstrained. The return-type cannot be a record or multi-dimensional array. The legal data types allowed are: Scalar types: enumeration, integer, physical, floating-point Composite types: single dimensional array only Access Types File Types Slang procedures and functions cannot have parameters whose data-type is a record or multi-dimensional array. The legal data types allowed are: Scalar types: enumeration, integer, physical, floating-point Composite types: single dimensional array only Access Types File Types >8?Tield.count <= input_count; myrec_positional <= (input_vecpart, input_count); ?VHDL-2111 Message %1 Description The fields of a record were assigned using named aggregate assignment, which is not supported for synthesis. The following is an example of this style of assignment: type myrec_type is record vecpart : bit_vector(0 to 4); count : integer range 0 to 4; end record; signal myrec : myrec_type; ... myrec <= (vecpart => input_vecpart, count => input_count); In the above example, "vecpart" and "count" are fields of a record. For records, aggregate assignment using named notation is not supported. What Next Assign each field of the record individually, or use positional notation. The following example shows both positional notation and assignment of each field individually. type myrec_type is record vecpart : bit_vector(0 to 4); count : integer range 0 to 4; end record; signal myrec_positional : myrec_type; signal myrec_eachfield : myrec_type; ... myrec_eachfield.vecpart <= input_vecpart; myrec_eachf>8B?VHDL-2112 Message %1 Description File names in the file declaration should be constants, generics or constant string literals. Use of expression or argument of the subprogram parameter is not supported by Cyclone. Q?VHDL-2131 Message %1 Description The following usage is not supported in VHDL Compiler. LABEL: configuration library_name.configuration_name generic map (...) port map (...); >8d?VHDL-2132 Message %1 Description The following usage is not correct in VHDL Compiler. LABEL: library_name.entity_name(architecture_name) generic map (...) port map (...); VHDL Compiler reads the architecture to be used from the .mra file. Therefore, only the most recently analyzed one is meaningful to synthesis. What Next Remove the architecture specification from the statement and analyze the architecture you want to use first. z?VHDL-2142 Message %1 Description Multiple-dimensional array is not supported for synthesis. So `RANGE(i) or `REVERSE_RANGE(i) is meaningless for synthesis. O|8 ?VHDL-2156 Message %1 Description The VHDL predefined type "REAL" is an example of a floating point type. What Next Remove any floating point types from the VHDL source.  ?VHDL-2157 Message %1 Description This error occurs if a type is used but not declared. It is likely to happen if the type declaration is enclosed in translate_off or synthesis_off comments. What Next Declare the type before you use it. >8 ?VHDL-2158 Message %1 Description Record types are not support in generics, only in ports, signals variables, and constants. What Next Use multiple smaller generics.  ?TVHDL-2159 Message %1 Description A string with no characters or spaces is not supported by VHDL Compiler. For example, the following is not supported: entity test is generic(str : string := ""); -- This is not supported port(data_in : in std_logic; data2_in : in std_logic; data_out : out std_logic); end test; architecture one of test is constant c1 : string := ""; -- This is not supported begin end test; What Next Use a blank string (i.e. " ") instead of an empty string (i.e. ""). The above code should be modified to: entity test is generic(str : string := " "); -- Add a space. This is allowed. port(data_in : in std_logic; data2_in : in std_logic; data_out : out std_logic); end test; architecture one of test is constant c1 : string := " "; -- Add a space. This is allowed. begin end test; >8 ?VHDL-2160 Message %1 Description An example of the use of the 'event attribute is: if (clk'event and clk = '1') then ... or wait until clk'event and clk = '1'; An example for the use of the 'stable attribute is: if (not clk'stable and clk = '1') then ... or wait until not clk'stable and clk = '1'; This error will occur in cases such as the following: if(clock'event and clock = '1' and enable = '1') then ... or wait until clk'stable and clk = '1'; What Next Modify the statement containing the 'stable or 'event attribute so that it is in conformance with the suggested style.  @VHDL-2161 Message %1 Description This is a Boolean attribute. To have any effect, it must be set to "TRUE." What Next Check that the attribute specification assigns the value "TRUE." Case doesn't matter. >8@yVHDL-2162 Message %1 Description VHDL Compiler doesn't allow parameters or variables declared in parent subprogram to be used in nested child subprograms. For Example, the following usage of "j" and "v" are prone to bad logic: library ieee ; use ieee.std_logic_1164.all ; entity my_test is port( d : in std_logic ; q : out std_logic ); end my_test ; architecture synthesize of my_test is begin process(d) procedure outer_procedure(signal j : out std_logic) is variable v : std_logic; procedure inner_procedure is begin j <= v; end ; begin v := '1'; inner_procedure(j); end ; begin outer_procedure(q); end process; end synthesize ; What Next Change the usage of parameters or variables in your VHDL code. G@VHDL-21 Message %1 Description STD.TEXTIO package is not supported for synthesis. What Next Remove the use of this package from the use clause >8X@. X@e not been inserted properly, so the procedure is not synthesized. To make the code usable for both synthesis and simulation, this procedure declaration should be: procedure my_proc (variable data_in: in std_logic; variable clk: in std_logic; variable data_out: out std_logic -- synopsys synthesis_off ; variable delay: in time -- synopsys synthesis_on ); What Next To get around this problem, if you have more than one package of the same name (even if they are in different libraries), rename one of the packages. If you do not have more than one package of the same name, analyze the package and the design that uses the package in separate sessions of dc_shell or design_analyzer. If the problem has to do with the synthesis_off/on or translate_off/on directives, modify the code to use the directives appropriately. Please see the DESCRIPTION section above for additional information on this>8X@VHDL-2204 Message %1 Description This error occurs because the synthesis tool searches for packages in memory before it searches the libraries. A package exists in memory if it has been analyzed in the current session of the tool. The error can also occur if two or more libraries have packages of the same name and if the packages are used in the same design. If the object contains synopsys synthesis_off/on or translate_off/on directives around it, the object is not synthesized. As a result, the object cannot be found when it is referenced in the design. The problem can also occur if the directives are placed incorrectly around part of the object. For example, consider the following procedure declaration: procedure my_proc (variable data_in: in std_logic; variable clk: in std_logic; variable data_out: out std_logic; -- synopsys synthesis_off variable delay: in time); -- synopsys synthesis_on In this case, the directives hav}@RVHDL-2205 Message %1 Description This warning occurs if the same package is multiply declared in same HDL source file. It also occurs if multiple HDL source files are read by the same read or analyze command and if the same package is defined in more than one of the files. What Next Be sure to read or analyze a package only once. O|8@VHDL-2206 Message %1 Description You are using two (or more) architectures with the same name, belonging to the same entity. What Next Rename the architecture(s) so that they have unique names. @VHDL-2207 Message %1 Description VHDL-compiler does not allow component declaration inside a for generate loop. What Next Move the component declaration outside the for loop. >8@ VHDL-2230 Message %1 Description This error occurs if two or more instances in the same scope are labelled with the same name using the "label" pragma. What Next Change the names of one instances to make them distinct. You can do this by changing the label pragma for each instance. @VHDL-2234 Message %1 Description An object was referenced but not declared. This can happen if a pragma synthesis_off hides the declaration. What Next Change the HDL description so that the declaration is visible for the HDL Compiler. ?8@QVHDL-2237 Message %1 Description This error is given when the user has a comment of the form -- pragma <pragma_name> And the pragma_name is not one of the pragmas that is supported. What Next This is just a warning, so no action is required. However, the user may want to check the pragma_name to see if it has been mis-typed. @VHDL-2243 Message %1 Description The attribute value does not match the name of an object of the class of port, signal, or variable. What Next Change the attribute value. ?8@VHDL-2244 Message %1 Description The attribute value does not match name of a process label. What Next Change the attribute value. AVHDL-2245 Message %1 Description The process label has more than one Synopsys set_reset attribute, which is illegal. What Next Change source code to put only one set_reset attribute on the process. ?8AVHDL-2246 Message %1 Description A process label can have only one master_process_is/slave_process_is attribute. What Next Change source code to put only one attribute on the process. *AVHDL-2247 Message %1 Description Inside an expression, the VHDL Analyzer cannot deal with pragma translate_off or translate_on. What Next In the case of an after-clause, like the example below, take out the pragmas. After-clauses are ignored for synthesis. A warning is issued in that case. To suppress warnings, refer to the man page for the suppress_errors variable. Example The following example will cause error VHDL-2247: entity pragma is port ( iput : in bit; oput : out bit); end pragma; architecture test of pragma is begin oput <= iput -- synopsys translate_off AFTER 7 ns -- synopsys translate_on ; end test; P|8LAVHDL-2248 Message %1 Description The package declaration must be analyzed before the corresponding package body. There was probably a problem with the declaration part related to the synthesis subset, causing the analysis of the declaration to terminate. Since the analysis of the package declaration was terminated, the body cannot be analyzed. What Next Correct the problem in the package declaration, and this error will go away. Example This example will cause error VHDL-2248: package P is constant C : bit; -- deferred constant, not supported by synthesis. end P; package body P is constant C : bit := '0'; end P;  jAVHDL-2250 Message %1 Description When the value of the right-hand side is outside the range of the left-hand side, a run-time error occurs in simulation. However, no logic is built by the VHDL Compiler to detect this kind of run-time error. What Next Declare a proper range for the left-hand side. Or type-convert the right-hand side to ensure that the range of the left-hand side covers that of the right-hand side. ?8!{AVVHDL-2251 Message %1 Description This error occurs with statements of the form: if(clk'event and clock = '1' and enable = '1') then .. Such expressions are only permitted in: wait until clk'event and clock = '1' and enable = '1' ... at present What Next Modify the if statement with the enabling condition to conform to suggested style. "A#^ report "One-cold violation" severity Error; end process -- synopsys synthesis_on ?8#A"VHDL-2252 Message %1 Description Attribute 'one_hot' indicates at most one object in its group can have a Logic1 value at any instance of time, all other objects must have a Logic0 value. Attribute 'one_cold' indicates at most one object in its group can have a Logic0 value at any instance of time, all other objects must have a Logic1 value. What Next For "attribute one_hot of c1, c2, c3 : signal is "true", add a process in the design like the following exmaple. -- synopsys synthesis_off process (c1, c2, c3) begin assert not ((c1='1' and c2='1') or (c1='1' and c3='1') or (c2='1' and c3='1')) report "One-hot violation" severity Error; end process -- synopsys synthesis_on For "attribute one_cold of c1, c2, c3 : signal is "true", add a process in the design like the following exmaple. -- synopsys synthesis_off process (c1, c2, c3) begin assert not ((c1='0' and c2='0') or (c1='0' and c3='0') or (c2='0' and c3='0'))$AVHDL-2253 Message %1 Description Synthesis VHDL subset does not include this type of a value in a attribute specification. Value could be of concatenation type. What Next Rewrite the attribute specification using the VHDL synthesis subset. ?8%AVHDL-2254 Message %1 Description Synthesis VHDL subset does not include the VHDL type TIME. Your HDL should not depend on simulation-specific delays for its proper behavior. What Next You can prevent synthesis from using simulation-specific HDL by enclosing it within the synthesis_off / synthesis_on pragmas. Example The following is a sample usage of the TIME type used in a declaration: GENERIC( DelayAmount : TIME ); To prevent the TIME type from going through synthesis, change the above HDL to: GENERIC( --synopsys synthesis_off DelayAmount : TIME --synopsys synthesis_on ); This will ensure the HDL is present for simulation, but is ignored during synthesis. &AVHDL-2255 Message %1 Description Synthesis VHDL subset does not include generics of type string. What Next Rewrite the attribute specification using the VHDL synthesis subset. ?8'A!VHDL-2256 Message %1 Description Ranges of enumerated types using the TO construct are not supported in VHDL Compiler. The following CASE statement using the TO construct is not supported. type STATE_TYPE is (STATE0, STATE1, STATE2, STATE3); signal STATE, NEXT_STATE : STATE_TYPE; process begin case STATE is when STATE0 => DOUT <= '0'; when STATE1 to STATE3 => DOUT <= '1'; end case; end process; What Next The workaround is to use the "|" construct which performs an OR operation. type STATE_TYPE is (STATE0, STATE1, STATE2, STATE3); signal STATE, NEXT_STATE : STATE_TYPE; process begin case STATE is when STATE0 => DOUT <= '0'; when STATE1 | STATE2 | STATE3 => DOUT <= '1'; end case; end process; (BrVHDL-2257 Message %1 Description Some remote functions can not be called. What Next Move to a local package. ?8),BVHDL-2260 Message %1 Description Bit slices in the generic map of a component instantiation are not supported. For example: U1: GATE1 generic map ( INIT(0) => '0', INIT(1 to 7 ) => init_val) port map ( DINPUT(0) => d0, DINPUT(1) => d1, DOUTPUT => dout ); What Next Concatenate the values assigned to slices in the generic map or port map. Assign this concatenation to an intermediate signal or variable, and use this signal or variable in the component instantiation. For example: aggr1 <= ('0' & init_val); U1: GATE1 generic map ( INIT => aggr1 ) port map ( DINPUT(0) => d0, DINPUT(1) => d1, DOUTPUT => dout ); *EBVHDL-2262 Message %1 Description Enumeration values may not be used to define the bounds of a for or for-generate loop in Synopsys' synthesizable subset of VHDL. These bounds must be integer values that can be computed at compile time. ?8+TBVHDL-2263 Message %1 Description The number of enumeration encoding values defined via the ENUM_ENCODING attribute must match the number of enumeration values for the type. What Next Modify the number of enumeration or enumeration attribute values. ,eB@VHDL-2264 Message %1 Description What Next event and 'stable attributes are allowed to be used only when inferring a clock edge . For example (clock'event and clock = '1') and ((not clock'stable) and clock = '1') following are not allowed ((not clock'event and clock = '1') and (clock'stable and clock = '1') ?8-|BVHDL-2270 Message %1 Description HDL Compiler supports aliases to signals, variables and constants only. HDL Compiler does not support aliases that refer to existing aliases. What Next Either remove the alias to an alias and replace references to the first alias with references to the second, or replace the second alias with an alias to the original object. For example, given: signal B : std_logic_vector(0 to 31); alias MSB : std_logic_vector(0 to 7) of B(24 to 31); alias MSN : std_logic_vector(0 to 3) of MSB(4 to 7); ... MSN <= "0000"; You could remove the definition of MSN and replace its use with: MSB(4 to 7) <= "0000"; Or, you could transform the declaration of MSN and leave its use intact: alias MSN : std_logic_vector(o to 3) of B(28 to 31); ... MSN <= "0000"; .BQVHDL-2271 Message %1 Description HDL Compiler does not support the use of predefined attributes (such as 'LEFT, 'HIGH, 'RANGE, and so on) with aliases when the alias range is not locally static. What Next Replace the predefined attribute with the corresponding components of the alias's range. For example, given procedure foo(B : inout std_logic_vector) is begin constant b_left : integer := B'length-1; alias b_alias : std_logic_vector(b_left downto 0) of B; ... for I in b_alias'RANGE loop ... end loop; ... end foo; replace the loop with for I in 0 to b_left loop ... end loop; ۸8/B0VHDL-2280 Message %1 Description HDL Compiler supports the 'IMAGE attribute only as part of an attribute specification of the following type: attribute RELATIVE_LOCATION of <object> : label is <string_literal> & INTEGER'IMAGE(<indexvar>) & <string_literal> Where <indexvar> is the index variable of a for-generate loop. What Next The following is an example of the situation in which 'IMAGE might be used. G : FOR d IN 0 TO 7 GENERATE B : BLOCK ATTRIBUTE RELATIVE_LOCATION OF flop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; BEGIN flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); END BLOCK; END GENERATE G; In this case, you're instantiating a set of eight DFFs that will be used to latch the value of an eight-bit bus. Note that 'IMAGE can be used only + Within a block within a for-generate loop. + As part of an attribute statement, where the attribute name is "RELATIVE_LOCATION" and the value is a concatination of three strings: a prefix, the 'IMAGE expression0B/K, and a suffix. In the previous example, "R" is the prefix and "C0" is the suffix. The prefix and suffix must be literals. + With the index variable for the for-generate loop. Note that choices for the following are left to you: + The label for the for-generate loop and the block. + The number and contents of the instantiation statements within the block. You can also specify more than one entity name in the attribute statement. For example, you can use ATTRIBUTE RELATIVE_LOCATION OF flop,rflop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; if you were instantiating two series of entities: flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); rflop : dff PORT MAP (D => INP(d), Q=>R_OUTP(8-d), CK=>CLK); You can also have more than one such attribute statement if you want to specify a different prefix or suffix. ۸81B2yof three strings: a prefix, the 'IMAGE expression, and a suffix. In the above example, "R" is the prefix and "C0" is the suffix. The prefix and suffix must be literals. + With the index variable for the for-generate loop. Note that choices for the following are left to you: + The label for the for-generate loop and the block. + The number and contents of the instantiation statements within the block. You may also specify more than one entity name in the attribute statement. For example, you could use ATTRIBUTE RELATIVE_LOCATION OF flop,rflop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; if you were instantiating two series of entities: flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); rflop : dff PORT MAP (D => INP(d), Q=>R_OUTP(8-d), CK=>CLK); You may also have more than one such attribute statement, if you want to specify a different prefix and/or suffix. 2B1VHDL-2281 Message %1 Description HDL Compiler supports the use of the RELATIVE_LOCATION attribute only with a very specific value. The attribute statement must be of the form: attribute RELATIVE_LOCATION of <object> : label is <string_literal> & INTEGER'IMAGE(<indexvar>) & <string_literal> Where <indexvar> is the index variable of a for-generate loop. What Next The following is an example of the situation in which you may use the attribute RELATIVE_LOCATION: G : FOR d IN 0 TO 7 GENERATE B : BLOCK ATTRIBUTE RELATIVE_LOCATION OF flop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; BEGIN flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); END BLOCK; END GENERATE G; In this case, we're instantiating a set of eight DFFs that will be used to latch the value of an eight-bit bus. Note that 'IMAGE can be used only: + Within a block within a for-generate loop. + As part of an attribute statement, where the attribute name is "RELATIVE_LOCATION" and the value is a concatination ۸83B4M, and a suffix. In the previous example, "R" is the prefix and "C0" is the suffix. The prefix and suffix must be literals. + With the index variable for the for-generate loop. Note that choices for the following are left to you: + The label for the for-generate loop and the block. + The number and contents of the instantiation statements within the block. You can also specify more than one entity name in the attribute statement. For example, you can use ATTRIBUTE RELATIVE_LOCATION OF flop,rflop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; if you were instantiating two series of entities: flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); rflop : dff PORT MAP (D => INP(d), Q=>R_OUTP(8-d), CK=>CLK); You can also have more than one such attribute statement if you want to specify a different prefix or suffix. 4B3VHDL-2282 Message %1 Description HDL Compiler supports the 'IMAGE attribute only as part of an attribute specification of the following type: attribute RELATIVE_LOCATION of <object> : label is <string_literal> & INTEGER'IMAGE(<indexvar>) & <string_literal> Where <indexvar> is the index variable of a for-generate loop. What Next The following is an example of the situation in which 'IMAGE might be used. G : FOR d IN 0 TO 7 GENERATE B : BLOCK ATTRIBUTE RELATIVE_LOCATION OF flop : LABEL IS "R" & INTEGER'IMAGE(d) & "C0"; BEGIN flop : dff PORT MAP (D => INP(d), Q=>OUTP(d), CK=>CLK); END BLOCK; END GENERATE G; In this case, you're instantiating a set of eight DFFs that will be used to latch the value of an eight-bit bus. Note that 'IMAGE can be used only + Within a block within a for-generate loop. + As part of an attribute statement, where the attribute name is "RELATIVE_LOCATION" and the value is a concatination of three strings: a prefix, the 'IMAGE expression:?85CVHDL-2283 Message %1 Description Presently 'IMAGE attribute has a limited support in HDL compiler. Only Integer may appear as a prefix to it What Next Please rewrite the use of 'image attribute so that it has integer as its prefix 60C7--- :?870C6VHDL-2284 Message %1 Description This version of VHDL Compiler doesn't support declarative regions of generate statements. What Next Use block statement inside the generate statement. Example: You replace the following VHDL codes ---------------------------------------------------------------------- build_blks: FOR i IN 1 TO 4 GENERATE SIGNAL int_connect: unsigned(3 DOWNTO 0); BEGIN blk1: blk_in PORT MAP(a_in(i - 1), int_connect(i - 1)); blk2: blk_out PORT MAP(int_connect(i - 1), b_out(i - 1)); END GENERATE build_blks; ---------------------------------------------------------------------- by ---------------------------------------------------------------------- build_blks: FOR i IN 1 TO 4 GENERATE THE_BLOCK : block SIGNAL int_connect: unsigned(3 DOWNTO 0); BEGIN blk1: blk_in PORT MAP(a_in(i - 1), int_connect(i - 1)); blk2: blk_out PORT MAP(int_connect(i - 1), b_out(i - 1)); end block; END GENERATE build_blks; -------------------------------------------------------------------8ICVHDL-22 Message %1 Description Somehow the db file contains incomplete type information. Please find out which command caused this problem and report it to the Support Center or CAE. What Next Please regenerate the db file. Q|89ZCVHDL-232 Message %1 Description The entity for the current architecture could not be found in the library. What Next Provide the entity for the architecture. :kCVHDL-265 Message %1 Description This error occurs when vhdlout_preserve_hierarchical_types is set to a higher value than vhdlout_single_bit. The variables vhdlout_single_bit and vhdlout_preserve_hierarchical_types control how VHDLout handles types on ports and pins. See the manual pages on these variables for information on possible settings. What Next Change the value of vhdlout_single_bit and/or vhdlout_preserve_hierarchical_types and retry the write command. Example Message Error: The value 'ENUM' of vhdlout_preserve_hierarchical_types is greater than that of vhdlout_single_bit. vhdlout_preserve_hierarchical_types is changed to be equal to vhdlout_single_bit. ;?8;C VHDL-266 Message %1 Description This error occurs when vhdlout_single_bit or vhdlout_preserve_hierarchical_types is set to an invalid value. The variables vhdlout_single_bit and vhdlout_preserve_hierarchical_types control how VHDLout handles types on ports and pins. See the manual pages on these variables for information on possible settings. What Next Correct the setting of the variable and retry the write command. Example Message Error: 'vhdlout_preserve_hierarchical_types' contains the invalid string 'RNUM'. <CzVHDL-267 Message %1 Description VHDLout infers the name of the type-conversion package (if it is needed) from the variable vhdlout_package_naming_style. The setting of this variable must result in a legal VHDL identifier. See the manual page for vhdlout_package_naming_style for more details. This error occurs when vhdlout_package_naming_style is set to a value that results in an illegal name for the type conversion package. What Next Correct the setting of the variable and retry the write command. Example Message Error: The current setting, '%s', of vhdlout_package_naming_style does not produce a valid VHDL identifier. A?8=CVHDL-268 Message %1 Description VHDLout infers the name of the type-conversion package (if it is needed) from the variable vhdlout_package_naming_style. The setting of this variable must result in a legal VHDL identifier. See the manual page for vhdlout_package_naming_style for more details. This error occurs when vhdlout_package_naming_style is set to a string that cannot be understood by VHDLout. The string (or substring) begins with a '%' followed by an unexpected character. What Next Correct the setting of the variable and retry the write command. Example Message Error: '%' is not valid for vhdlout_package_naming_style. >CZVHDL-269 Message %1 Description This use of dc_scripts is discouraged because it does not have the same scope as library and use clauses. What Next To apply a dc_script to a single design unit, the script must be declared in the declarative region of that design unit. You can suppress this message by setting the suppress_errors variable. B?8?CVHDL-270 Message %1 Description Configurations between the test bench and your top-level design are written out only when the variable vhdlout_single_bit is set to type vector. The purpose of the configuration is to map between the original and new types. If vhdlout_single_bit is set to user, the original types are used, and a configuration is unnecessary. If vhdlout_single_bit is set to bit, the new ports do not map well to the original types. In this case, a configuration is impractical. What Next If you are using the original types (vhdlout_single_bit is set to user), you can ignore this message, or, to disable the writing of configurations, you can set vhdlout_write_top_configuration to "FALSE." If you want to write out a configuration with your design, set vhdlout_single_bit to vector, and rewrite the design. NOTE: Setting vhdlout_single_bit to vector does not affect the acceleration of your design. @CSVHDL-271 Message %1 Description The 'vhdlout_bit_type' must be a one-bit wide type for VHDLout to be able to produce a legal description. What Next Check your type definition and ensure it is one bit wide. If the type definition is an enumerated type with more than two possible values, it may be missing the ENUM_ENCODING attribute. H?8AC`VHDL-272 Message %1 Description Vhdlout found a possible clash between two connected objects. An object A, that may drive a three-state value. An object B, being driven by object A and that is of a type not including a three-state value. For example: a signal of type 'bit' may drive a port in mode 'inout'. This is legal and works as long as that port is never driven by the outside world. This may also happen if the source description language was less rigorous on types than VHDL. Note that such a clash is cought by simulation during run-time. What Next The alternatives are: A - locate the clash and correct the HDL description, re-analyze, re-synthesize and re-write vhdl. In the example above, one can either use a resolved type for the signal or change the port's mode to 'out'. B - leave as is and simulate to find out if this was a true error. BDVHDL-273 Message %1 Description This will be fixed in a future release. What Next Work around, compile design before writing out VHDL. K?8CDXVHDL-274 Message %1 Description Driver type may be specified for three-state cell pins in Synopsys' Library format, which is used to describe technology libraries. This warning is issued when VHDLout is writing a behavioral description and don't recognize the driver type at hand. The resulting description may have problems simulating weak signal values properly. Please inform Synopsys when this happens. What Next This warning is issued only when vhdlout_equations = TRUE. The warning can be avoided by setting the variable to FALSE in which case a structural description is written. For such a description, the driver type isn't relevant to VHDLout. An alternate approach is to use the dont_use attribute on the library cell in question, prior to compiling the design. Please refer to man-page for the dc_shell command set_dont_use for details. D+DVHDL-275 Message %1 Description Driver type may be specified for three-state cell pins in Synopsys' Library format, which is used to describe technology libraries. This warning is issued when VHDLout is writing a behavioral description and encounters different pin driver types on the same library cell. VHDLout is not capable of handling more than one driver type per cell. The resulting description may have problems simulating weak signal values properly. Please inform Synopsys when this happens. What Next This warning is issued only when vhdlout_equations = TRUE. The warning can be avoided by setting the variable to FALSE in which case a structural description is written. For such a description, the driver type isn't relevant to VHDLout. An alternate approach is to use the dont_use attribute on the library cell in question, prior to compiling the design. Please refer to man-page for the dc_shell command set_dont_use for details. Y?8E?DFxer to the ZyCad XP manuals.) If you receive this warning message, your design might require type conversions and/or might contain user-defined types. What Next If your design contains user-defined types or requires type conversions, check the setting of the variable vhdlout_single_bit and, if it is set to USER, change it to VECTOR or BIT. Then re-execute write -f vhdl. F?DEVHDL-276 Message %1 Description The XP accelerator accepts as input only a limited subset of VHDL constructs. A design that cannot be described using this subset is not acceleratable by the XP accelerator. By setting the variable vhdlout_target_simulator to XP, you requested a VHDL output that is targeted at the XP accelerator. If vhdlout_target_simulator is set to XP, write -f vhdl attempts to describe the design using the XP-supported VHDL subset. If this is successful, then write -f vhdl adds the BACKPLANE attribute to the output VHDL file, indicating that the design is to be simulated using the XP Accelerator. If, however, vhdlout_target_simulator is set to XP and the design cannot be described using the XP-supported VHDL subset, then write -f vhdl does not add the BACKPLANE attribute to the generated VHDL description, and issues this warning message. The XP-supported VHDL subset cannot describe type conversions or user-defined types. (For more information on allowed types, refR|8GSDVHDL-277 Message %1 Description The process statement contains an attributed object in its scope and, as a result, must be labelled. What Next Label the process statement. HdD"VHDL-278 Message %1 Description The VHDL writer does not know the port direction, so it cannot write it out. This is probably caused by some modules that are missing when reading Verilog files. What Next Read in the complete design that has specified the port direction and try again. J8IuDVHDL-279 Message %1 Description STD.TEXTIO package is not supported for synthesis. What Next Remove the use of this package from the use clause JDVHDL-2 Message %1 Description There was a name clash between these two objects. Please refer to the IEEE Standard VHDL Language Reference Manual (normally referred to as the VHDL LRM) for details on scoping rules for identifiers. There is a limitation in the intelligence of VHDLout when issuing this warning. If there is a port with a name that clashes with a type-name, where the type is used as a sub-type of another type in a design being written out, and this sub-type is defined in STD.STANDARD (a predefined package that is part of the language definition), then this warning is issued even though no type declaration for the sub-type is written out. In other words this warning may be issued for a type name that is actually not written out. With the current version of the VHDL LRM, IEEE Std 1076-1987, this will only happen for the following example: entity e is port ( bit: out bit_vector(1 downto 0)); end e; architecture a of e is begin ... end a; `?8KDVHDL-3 Message %1 Description This error is generated when vhdlout_single_bit is not set to BIT, and type information is not supported. What Next Change the types to the supported types. one of the following: Bit,Array,Enumeration and Record LDMqr : out std_logic); end TRI_VHDL; architecture test of TRI_VHDL is begin process ( cond, a) begin if( cond) then r <= a; else r <= 'Z'; end if; end process; end test; Example Message Error: You must change 'vhdlout_bit_type' to a bit type that includes a three-state value when writing out generic three-state devices. (VHDL-7) f?8MDLVHDL-7 Message %1 Description vhdlout_bit_type determines what VHDL type to use when writing out ports, single-bit-wide ports, or ports that were buses in the original source but are written out bit-blasted. This error can occur if, for instance, a generic three-state device is written out and vhdlout_bit_type is set to type "BIT," which does not contain a three-state value. Such a description cannnot simulate the high-impedance value, so VHDLout issues this error. Note that VHDLout, apart from the type "BIT," does not recognize possible values of a type. So, if you use a type other than "BIT," but it does not contain a three-state value, this error will go undetected. What Next Set vhdlout_bit_type to a type that contains a three-state value. For example std_logic. Example This example will cause the error if read in and then written out with vhdlout_bit_type = BIT. library IEEE; use IEEE.std_logic_1164.all; entity TRI_VHDL is port ( cond : in boolean; a : in std_logic; NDUVSS-0 Message %1 Description This error was generated because of a Simulator software error. This error can arise if the code generated by the Analyzer is different from that expected by the Simulator, or a corruption of data structures inside the Simulator occurs. What Next This error indicates a software problem for which no workaround exists. Please contact Synopsys Hotline. The error string will give some indication as to what might be happening. Examples No example available. Example Message **Error: vhdlsim,0: Internal Error - Please report Strange mtree node in pass1 J8ODP*ess begin s <= not s; wait for 10 ns; end process; end; configuration C of E is for A end for; end C; Example Message % vhdlan -nc code.vhd signal s: bit = '0'; -- missing ':' before '=' **Error: vhdlan,1081 code.vhd(5): Syntax error. -- Note: This is the real problem configuration C of E is **Error: vhdlan,1015 code.vhd(14): The intermediate file for the entity-architecture pair E(A) is not in the library bound to WORK. "code.vhd": errors: 2; warnings: 0. PDQOsfully analyzed. This error could also be generated if the configuration statement is in a source file separate from the corresponding entity-architecture declarations, and that file is analyzed before the entity-architecture declarations. What Next Most of the time, this error goes away once the errors in the entity-architecture declarations are eliminated and the entity-architecture statements are analyzed successfully without any errors. So, check the output of the vhdlan to see the errors it generated during the compilation of the entity-architecture declarations. If the configuration statement is in a different source file from the corresponding entity-architecture statements, make sure that the file containing the entity-architecture is compiled successfully before attempting to analyze the file containing the configuration statement. Example % cat code.vhd entity E is end; architecture A of E is signal s: bit = '0'; -- missing ':' before '=' begin P: proc?8QDPVSS-1015 Message %1 Description This error was generated because the intermediate files corresponding to an entity-architecture is not in the directory corresponding to the logical library WORK. This error was generated by the Synopsys VHDL System Analyzer (vhdlan) while parsing a configuration declaration. A configuration declaration statement is defined as: configuration identifier of entity_name is configuration_declarative_part block_configuration end [ configuration_simple_name ] ; Here, the entity name identifies the name of the entity declaration that defines the design entity at the root of the design hierarchy. The entity and the corresponding architecture declarations must be successfully analyzed before the configuration declaration can be analyzed. So, the above error will be generated during the analysis of the configuration statement, if the corresponding entity-architecture was not succesR/ESvhd % vhdlsim -nc TEST STRUCT **Error: vhdlsim,101: Top level entity/architecture must be configured before it can be simulated. % vhdlan -nc vss-101-d.vhd % vhdlsim -nc CHEAP # q % ?8S/ETR.mypkg.all; architecture struct of test is component filter port( news : IN int256; tog : IN bit; avg: OUT int256); end component; signal newsig, avgsig : int256 :=0; signal togsig : bit := '0'; -- One can defer the bindings of component instance by using -- Configuration declaration. -- for u2: filter use entity work.filter(A); begin p : process begin for j in 1 to 10 loop togsig <= not(togsig); newsig <= j; wait for 1 ns; end loop; end process; u2 : filter port map ( newsig, togsig, avgsig); end struct; -- File: vss-101-d.vhd ---------------------------------- Configuration cheap of test is for struct -- Architecture "struct" has one instance "u2" for -- Entity "filter". "A" is one way of designing "filter". for u2: filter use entity work.filter(A); end for; end for; end cheap; Example Message % vhdlan -nc vss-101-a.vhd vss-101-b.vhd vss-101-c.T/EUS What Next If you have configured the top level entity/architecture but haven't analyzed the file containing the configuration, analyze that file before elaboration/simulation. If you haven't configured the top level entity/architecture, configure it, analyze, and start the simulation. Example -- File: vss-101-a.vhd --------------------------------- package mypkg is subtype int256 is integer range 0 to 256; end mypkg; -- File: vss-101-b.vhd ---------------------------------- -- Contains entity and architecture for the design of a filter. use work.mypkg.all; entity filter is port( news : IN int256 := 0; tog : IN bit; avg: OUT int256:=0); end filter; architecture A of filter is begin p : process variable oldavg :int256 := 0; begin wait on tog; oldavg := ( 7*oldavg + news) / 8 ; avg <= oldavg; end process; end A; -- File: vss-101-c.vhd -------------------------- entity test is end test; use std.textio.all; use work?8U/ETVSS-101 Message %1 Description This error was generated because the top level entity/architecture contains component instances that need to be configured. A configuration describes how component instances in a given block are bound to design entities, in order to describe how design entities are put together to form a complete design. The binding of component instances to design entities is performed by a configuration specification. You can associate binding information by using a configuration specification in the declarative part of the block in which the corresponding component instances are created. You can defer this binding by providing a separate configuration declaration. (See example below.) For the configuration of a given design entity, both the configuration declaration and the corresponding entity declaration must reside in the same library. A configuration declaration achieves it effect entirely through elaboration. For more information see LRM Sections 1, 1.3, 5.2.VEWWORK.P2.SHORT). However, this is legal VHDL and illustrates one of the problems that subtypes were intended to solve. See Also For more explanation about types, type declarations and assignment statements, refer to the following sections of the IEEE Standard VHDL Language Reference Manual (LRM). 4.1 Type Declarations 8.4 Variable Assignment Statement 9.5 Concurrent Signal Assignment Statement 3. Types ?8WEXVGE DEFAULT.P1, Source data type: SHORT declared in PACKAGE DEFAULT.P2). **Error: vhdlan,1023 test.vhd(23): Type mismatch over assignment operation (Target data type: SHORT declared in PACKAGE DEFAULT.P1, Source data type: SHORT declared in PACKAGE DEFAULT.P2). If you intend to have these two types interact, a better solution might be to define them as subtypes of type INTEGER. In the next example, the previous example has been modified to use subtypes. package P1 is subtype SHORT is INTEGER range 0 to 4095; end P1; package P2 is subtype SHORT is INTEGER range 0 to 4095; end P2; entity E is end; use WORK.all; architecture A of E is signal S1 : P1.SHORT := 0; signal S2 : P2.SHORT := 0; begin process variable V1 : P1.SHORT := 0; variable V2 : P2.SHORT := 0; begin V1 := V2; S1 <= S2; wait; end process; end; Here the type is the same (INTEGER, a.k.a. STD.STANDARD.INTEGER), but the subtypes differ (WORK.P1.SHORT and XEYW these problems might apply to your situation. Incorrect use of types and subtypes is probably the most common problem. Example In the following example, there are two types named 'SHORT', which are exactly the same in every respect, except that one is defined in package P1 and the other is defined in package P2. In VHDL, these two types are completely different and assignments cannot be made directly between them. package P1 is type SHORT is range 0 to 4095; end P1; package P2 is type SHORT is range 0 to 4095; end P2; entity E is end; use WORK.all; architecture A of E is signal S1 : P1.SHORT := 0; signal S2 : P2.SHORT := 0; begin process variable V1 : P1.SHORT := 0; variable V2 : P2.SHORT := 0; begin V1 := V2; -- Error, line 22 S1 <= S2; -- Error, line 23 wait; end process; end; produces the errors: **Error: vhdlan,1023 test.vhd(22): Type mismatch over assignment operation (Target data type: SHORT declared in PACKA?8YEXVSS-1023 Message %1 Description This error was generated because the type of the left-hand side of an assignment operation is different from the type on the right-hand side. (The "left-hand side" is the target of the assignment, the object to the left of the assignment operator.) The right-hand side is a general expression. The error message specifies exactly the types of each side of the assignment operator and where each type is defined. These types must match exactly. What Next Depending on the nature of your design, the problem(s) may be among these: Simple typo The 'fix' here should be fairly straightforward, once found. Confusion or incorrect use of types and subtypes This is a more difficult problem. See the Examples section below for an example problem and possible solution. Too many packages defining types You might need to centralize your types packages to prevent overlap of definitions and to avoid homographs.  You should examine your code to determine which ofZE[ E is begin process type st1 is ('a', 'b', 'c'); type t1 is array(natural range <>) of st1; subtype t2 is t1(1 to 2); subtype t3 is t1(1 to 2); variable V1,V2 : STRING (1 to 4) := "ABDC"; variable V3 : t2; variable V4 : STRING(1 to 2); begin /* assign complex expression to a variable V4 := V1(1) & V2(4); case V4 is when others => null; end case; -- use of type conversion t3 case t3(V3) is when others => null; end case; -- use of qualified expression t3 case t3'(V3) is when others => null; end case; end process; end A; Example Message % vhdlan -nc code.vhd ?8[E\Z when others => null; end case; -- type conversion t2 is an unconstrained array type case t2(V3) is when others => null; end case; end process; end A; Example Message % vhdlan -nc code.vhd case V1(1) & V2(4) is ^ **Error: vhdlan,1029 code.vhd(13): Expression must be the name of an object whose subtype is locally static, or it must be a qualified expression or type conversion whose type mark denotes a locally static subtype. case t2(V3) is ^ **Error: vhdlan,1029 code.vhd(16): Expression must be the name of an object whose subtype is locally static, or it must be a qualified expression or type conversion whose type mark denotes a locally static subtype. "code.vhd": errors: 2; warnings: 0. An example to show how to modify your code to make it work entity E is end; architecture A of\E][plicitly state the type. - If there is a type conversion in the expression, make sure that the type mark of the type conversion is locally static. This means that the type must not be an unconstrained array type. If the type mark is a constrained array, the index constraints and the subelement subtypes must be locally static. What Next Either change your code to declare a constrained array type or use qualified expressions or type conversions and re-analyze. See the examples section for an example problem and possible solution. Examples entity E is end; architecture A of E is begin process type st1 is ('a', 'b', 'c'); type t1 is array(natural range <>) of st1; type t2 is array(natural range <>) of st1; variable V1,V2 : STRING (1 to 4) := "ABDC"; variable V3 : t1 (1 to 4) := "abcc"; begin -- expression without an explicit type case V1(1) & V2(4) is ?8]E\VSS-1029 Message %1 Description This error was generated because the selector expression of a case statement does not conform to the rules of the LRM section 8.7: If the expression is of a one-dimensional character array type, then the expression must be the name of an object whose subtype is locally static, or it must be a qualified expression or type conversion whose type mark denotes a locally static subtype. To fix this error, make sure that the expression whose type is a one dimensional character array satisfies one of the following conditions: - The subtype of the expression is locally static. This means that indices of the array type are locally static expressions. A locally static expression is an expression that can be evaluated during the analysis of the design unit. See the LRM section 7.4 for a more detailed definition. - If the expression is complex, its type must be known and unambiguous. Use qualified expression where you ex^aFXVSS-1032 Message %1 Description The VHDL language requires all possible choices are specified when a case statement is declared. What Next Often the "when others" statement can be used to cover any possibilities that are not specified. If the type of the signal or variable used in the case statement is std_ulogic, remember std_logic has 9 states. Examples signal test : std_logic_vector(3 downto 0); signal output : std_logic_vector(2 downto 0); case test is when "0000" => output <= "11"; when "0001" => output <= "11" when others => output <= "00"; end case; entity e is end e; ?8_F`h overloaded -- to use, since it is not allowed to 'look' -- for help in the context. s1 <= (s1-100) when "11111111", (s1+3) when others; end; Example Message %vhdlan -nc err1033.vhd with (To_X01(s2)) select ^ **Error: vhdlan,1033 err1033.vhd(12): Selector expression is ambiguous. "err1033.vhd": errors: 1; warnings: 0. % `F_VSS-1033 Message %1 Description This error was generated because the analyzer could not tell the type of a selector expression in a selected signal assignment or in a case statement. This situation is unique, since the analyzer cannot tell in advance what is the expected type of the expression (unlike an assignment, for example). What Next The expression is (in whole or part) overloaded. You should use type qualification to help the analyzer disambiguate the type. For more information on the selector expression type and how it is determined, see the LRM section 8.8. Examples entity e is end e; library IEEE; use ieee.std_logic_1164.all; architecture a of e is signal s1 : integer := 0; signal s2 : bit_vector(7 downto 0) := "11111111"; begin with (To_X01(s2)) select -- To_X01 is an overloaded function which may -- return a vector of different types. -- The analyzer cannot tell whicJ8aFb!st one architecture body has been analyzed corresponding to the entity that will be bound by default (the most recently analyzed architecture is the one that will be associated). For more information on these issues, see the VHDL Language Reference Manual, sections 1.3.3, 5.2.1.1, 5.2.2, and 12.4.3. Examples entity partBound is end; architecture partBound of partBound is begin end; entity E is end; architecture A of E is component partBound end component; for all: partBound use entity Work.partBound; -- The entity aspect above does not specify the architecture begin L: partBound; end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E Warning: vhdlsim,104: /E/L/COMPONENT was not instanced because it is bound to an entity with no architecture. # quit bFaVSS-104 Message %1 Description This warning was generated by the Simulator because the elaboration of a component instantiation statement has no effect when the component instance is only partially bound to a design entity. This occurs when the entity aspect for the instance implies a design entity that has an entity declaration visible but no associated architecture body, and is possible when: An entity aspect specifies an entity name but omits the architecture identifier. The LRM does not define which architecture body is to be selected. The default binding indication results in the association with an entity that has an entity declaration visible but no architecture bodies in the library.  What Next The message is a merely a warning that the component instantiation statement being referred to will have no effect. If this is not your intention, for the first situation above, specify the architecture identifier in the entity aspect. In the second situation, ensure that at lea?8cFd use entity work.E1(A); -- end for; end for; end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc cfg Warning: vhdlsim,105: /E/L/COMPONENT was not instanced because it is unbound. dFecarchitecture declarative part or inside the configuration declaration, or use the default configuration where the name of the entity and the corresponding component is the same; then re-analyze the design. Example entity E1 is port (I: in bit; O: out bit); end E1; architecture A1 of E1 is begin end A1; use WORK.all; entity E is end E; architecture A of E is -- naming component C1 as E1 will fix the problem component C1 port (I :in BIT; O: out BIT); end component; -- adding the following configuration specification to the -- architecture declarative part will fix the problem -- for L: C1 -- use entity E1(A1); signal SI, SO: bit; begin L: C1 port map (SI, SO); end A; configuration cfg of E is for A -- adding the following configuration specification to the -- configuration declaration will fix the problem too -- for all: C1 -- ?8eFdVSS-105 Message %1 Description This error was generated during the elaboration of a component instantiation statement. The error can be caused three ways: a configuration specification is missing from your VHDL code, the names of a design entity and its corresponding component are not the same, the entity is hidden due to the existence of a homograph. (see (1987) VHDL LRM sections 10.3 and 10.5)  A configuration specification tells how the component instances in a given block are bound to design entities, thus describing how design entities are put together to form a complete design. Configuration specifications are defined in the VHDL LRM section 5.2 as follows: for component_specification use binding_indication The component_specification defines either a list of instantiation labels, or the reserved words others or all. The binding_indication associates component instances with a particular design entity. What Next Either add a configuration specification inside the f-GVSS-1065 Message %1 Description This error was generated because a library logical name is not mapped to a host directory. What Next Map the library logical name to to a host directory. See also the VHDL System Simulator Core Programs Manual chapter on system configuration and the chapter on customizing your environment. Examples -- file name: .synopsys_vss.setup -- WORK > WHERE -- fix is adding "WHERE : <host_path>" -- file name: e1065.vhd library WHERE; entity E is end E; architecture A of E is begin end A; Example Message % vhdlan e1065.vhd **Error: vhdlan,1065: Library logical name WORK is not mapped to a host directory. % J8gYGhmfg_std : grade_t := PASS; -- Correct constant yield : real := .912; -- Incorrectly formed numeric literal -- constant yield : real := 0.912; -- Correct constant count : real := 8#13.2e+4; -- Missing delimiter -- constant count : real := 8#13.2#e+4; -- Correct constant qkey : character := "q"; -- Character literal -- constant qkey : character := 'q'; function negate (val : Integer) return Integer; end; package body bad_literals is function negate (variable val : Integer) -- Variable class not allowed -- function negate (val : Integer) -- Constant object class implicit return integer is variable neg_val : Integer; begin neg_val := val * -1; -- Violation of precedence rules -- neg_val := val * (-1); -- Correct return neg_val; end; end; See Also IEEE Standard VHDL Language Reference Manual, Appendix A. hYGignes before it. Correct the error and re-analyze the source file. Example entity buffer is -- Reserved word used as identifier generic (tHold : time := 1 ns); port (X, en: in Bit; Z: out : Bit); -- Extra colon begin assert (tHold > Z'last_event) severity WARNING report "Hold time violation"; -- Statement misordered end buffer; architetcure buffer_body of buffer is -- Characters transposed begin A: process begin if (en = '1') -- Missing "then" Z <= X; else if (en = '0') -- Correction "elsif" null; -- Missing "end if;" end process; end; Example Message % vhdlan -nc example entity buffer is ^ **Error: vhdlan,1081 example(1): Syntax error. "example.vhd": errors: 1; warnings: 0. Example package bad_literals is type grade_t (FAIL, PASS, PREMIUM); -- Missing reserved word -- type grade_t is (FAIL, PASS, PREMIUM); -- Correct constant mfg_std : grade_t := 'PASS'; -- Syntax error -- constant ?8iYGhVSS-1081 Message %1 Description This error message was issued because the VHDL analyzer encountered a symbol or sequence of symbols in the VHDL source file that is illegal for the context in which it appears. The syntax of VHDL is a set of rules defining the expected order of characters, words, and constructs in a source file. If your VHDL source file does not conform to these rules, the analyzer will generate this message along with an indication of where in the source file the error was first detected. What Next Some common mistakes that cause syntax errors are: + Typos, misspellings, transposed characters, missing character(s) + Missing semicolon + Missing reserved word + Badly formed literal (i.e. "c" vs. 'c') + Wrong operator for context (i.e. A = B vs. A := B) + Using reserved word as identifier + Statement misordered + Character mistakenly added/deleted Check for a misspelled word, missing semicolon, etc. on the line shown in the error message and on the lijGka syntax error and was -- therefore not written to the library WORK. architecture A of E is begin end A; Example Message % vhdlan -nc E1084 port (X : in Bit , Y : in Bit ; Z : out Bit); ^ **Error: vhdlan,1081 E1084.vhd(2): Syntax error. architecture A of E is ^ **Error: vhdlan,1084 E1084.vhd(5): The intermediate file for entity E is not in the library bound to WORK. "E1084.vhd": errors: 2; warnings: 0. ?8kGjVSS-1084 Message %1 Description This error was generated because your design referenced an entity not present in the working design library. A design library is a storage facility for previously analyzed design units. The Synopsys VHDL System Simulator implements design libraries via the host file system. Each library is mapped to a single directory. When a source file is analyzed, each design unit is stored as an entry in a design library. This error indicates that the analyzer cannot find the named entity in the working library, which is by default the current directory. What Next Check to make sure the entity was analyzed without errors prior to the analysis of the secondary unit that references it. After you correct the error, re-analyze the entity named in the error message and then re-analyze all source files that reference it. Example entity E is port (X : in Bit , Y : in Bit ; Z : out Bit); -- Syntax error. Comma should be semicolon. end E; -- Entity E contains lGmary WORK. package body P is end P; Example Message % vhdlan -nc P1085 type BV4 is ('0'; '1', 'Z', 'X'); ^ **Error: vhdlan,1081 P1085.vhd(2): Syntax error. package body P is ^ **Error: vhdlan,1085 P1085.vhd(5): The intermediate file for package specification P is not in the library bound to WORK. "P1085.vhd": errors: 2; warnings: 0. ?8mGlVSS-1085 Message %1 Description This error was generated because your design referenced a package not present in the working design library. A design library is a storage facility for previously analyzed design units. The Synopsys VHDL System Simulator implements design libraries via the host file system. Each library is mapped to a single directory. When a source file is analyzed, each design unit is stored as an entry in a design library. This error indicates that the analyzer cannot find the named package in the working library, which is by default the current directory. What Next Check to make sure the package was analyzed without errors prior to the analysis of the secondary unit that references it. After you correct the error, re-analyze the package named in the error message and then re-analyze all source files that use it. Example package P is type BV4 is ('0'; '1', 'Z', 'X'); end P; -- Package P contains a syntax error and was -- therefore not written to the librn Ho]e a of e is begin process subtype byte is bit_vector (7 downto 0); type bytep is access byte; variable v: bytep; variable w: byte; begin w := v.all; wait; end process; end; architecture a of e is begin process subtype byte is bit_vector (7 downto 0); type bytep is access byte; variable v: bytep; variable w: byte; begin w := v.all; wait; end process; end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc e # run **Error: vhdlsim,10: Null access value dereferenced. code.vhd(11): w := v.all; ?8o HnVSS-10 Message %1 Description Error message 10 will be emitted when an object of an access type, initialized to null, is dereferenced. An example follows: architecture a of e is begin process subtype byte is bit_vector (7 downto 0); type bytep is access byte; variable v: bytep; variable w: byte; begin w := v.all; wait; end process; end; In the above example, variable v is initialized to null by default (according to LRM section 3.3). LRM section 6.1 states that when evaluating the prefix of a name and the prefix is of an access type, it is an error if the value of the prefix is a null access value. Thus the variable assignment statement given in the above example is erroneous. What Next Modify the source so that the variable v is set to a non-null access value before dereferencing it. This can be done by using an initializer in the variable declaration for v: variable v: bytep := new byte; Example % cat code.vhd architecturpSHqgin U1: bus_master_1 port map (Data_Bus, Req(1), Ack(1)); U2: bus_master_2 port map (Data_Bus, Req(2), Ack(2)); end system_body; Example Message % vhdlsim -nc system (vhdlsim): Assertion error or keyboard interrupt during signal initialization: the resolution function RESOLVE_DRIVERS which resolves /SYSTEM/DATA_BUS. Assertion ERROR at 0 NS in design unit BUS_TYPES from process /_KERNEL: "Bus Collision Detected" # ?8qSHrpdriven to 0 Req : out tristate; Ack : in tristate); end bus_master_1; architecture bus_master_1_body of bus_master_1 is begin end; use WORK.bus_types.all; entity bus_master_2 is port (Data_Bus : inout rv_tristate := '1'; -- Initially driven to 1 Req : out tristate; Ack : in tristate); end bus_master_2; architecture bus_master_2_body of bus_master_2 is begin end; use WORK.bus_types.all; entity system is end system; architecture system_body of system is component bus_master_1 port (Data_Bus : inout rv_tristate; Req : out tristate; Ack : in tristate); end component; component bus_master_2 port (Data_Bus : inout rv_tristate; Req : out tristate; Ack : in tristate); end component; for U1: bus_master_1 use entity WORK.bus_master_1(bus_master_1_body); for U2: bus_master_2 use entity WORK.bus_master_2(bus_master_2_body); signal Data_Bus : rv_tristate := 'Z'; signal Ack, Req : tristate_array(1 to 2); berSHsqtate_array is array (Natural range <>) of tristate; function resolve_drivers (driver_values : tristate_array) return tristate; subtype rv_tristate is resolve_drivers tristate; end bus_types; package body bus_types is function resolve_drivers (driver_values: tristate_array) return tristate is variable number_drivers : Integer := 0; variable result : tristate := 'Z'; begin Detect_Collision: for i in driver_values'Range loop if (driver_values(i) /= 'Z') then number_drivers := number_drivers + 1; if (number_drivers > 1 and driver_values(i) /= result) then assert false report "Bus Collision Detected"; end if; result := driver_values(i); end if; end loop; return result; end resolve_drivers; end bus_types; use WORK.bus_types.all; entity bus_master_1 is port (Data_Bus : inout rv_tristate := '0'; -- Initially @8sSHrVSS-110 Message %1 Description This error message was issued because an assertion violation occurred or because you pressed interrupt (^C) while the simulator was assigning initial values to the signals of a design. The initial values of drivers and signals are computed during the elaboration phase, just prior to the start of simulation. Computing the initial value of a signal may require the execution of VHDL statements (for example, calling a resolution or type conversion function). These statements are executed during signal initialization. Assert statements are therefore evaluated and potentially violated during signal initialization. This message is also generated if you press interrupt (^C) before the initial simulator prompt is issued (that is, before static elaboration is complete). What Next Check to see which assertion failed and why. Correct the code. Re-compile the design and re-simulate. Example package bus_types is type tristate is ('0', '1', 'Z'); type tristHu-ckage body p is function my_func(j:bit) return integer is variable m:my_type; begin return m; end; end; library work; use work.p.all; -- dependency on package p will create -- a cyclical dependency. In order to -- break this cycle move declaration of -- p_type to package q declarative region. package body q is function q_func(j: bit) return integer is variable m : p_type; begin return m; end ; end; library work; use work.p.all; -- dependency on package p entity vss117 is end vss117; architecture a_vss117 of vss117 is begin end ; Example Message % vhdlan -nc vss117.vhd % vhdlsim -nc -t ms vss80 **Error: vhdlsim,117: Design unit dependency loop found. @8uHtVSS-117 Message %1 Description This error was generated because a cyclical dependency between the design units exists. A design unit D1 depends on design unit D2 if: a) D1 refers to the name D2. For example, architecture D1 refers to the entity D2 by name. b) D2 appears in the context clause of design unit D1. This happens when design unit D1 needs to import declaration from D2. What Next Check the design units constituting the model, and their dependencies on each other. If loops exist, find out why these design units depend on each other. This may be because of the reasons listed above. To break this cycle, move the declarations around so that the design unit dependency cycle is broken. Example package p is function my_func(j: bit) return integer ; subtype p_type is integer range 40 to 50; end; package q is subtype my_type is integer range 10 to 20; function q_func(j: bit) return integer ; end; library work; use work.q.all; -- dependency on package q pavHZVSS-118 Message %1 Description This error was generated because two logical library names are mapped to the same physical directory. The mapping of logical libraries to physical directories is specified in the .synopsys_vss.setup file. What Next Check your .synopsys_vss.setup file. Look for the mapping of the two logical library names mentioned in the error message. Change the mapping to two different directories. Example Following is an example of an invalid file mapping in the .synopsys_vss.setup file: LIB1 : /tmp/lib LIB2 : /tmp/lib Changing this mapping to the one following will solve the problem: LIB1 > LIB LIB2 > LIB LIB: /tmp/lib Example Message % vhdlan -nc vss118.vhd % vhdlsim -t ns vss118 **Error: vhdlsim,118: Design library names LIB1 and LIB2 map to the same host directory. @8wI VSS-119 Message %1 Description This error was generated because you tried to define the reserved design library name STD or WORK. What Next Do not define the reserved design library STD or WORK. For more information, see the VHDL System Simulator Core Programs Manual chapter on system configuration and the chapter on customizing your environment. Examples Following is an example of invalid mapping of design library names in the .synopsys_vss.setup file. WORK: ./work STD : ./std MY_WORK > WORK MY_STD > STD Example Message % vhdlan -nc e119.vhd **Error: vhdlan,119: Design library name WORK is reserved, and can not be defined by the user. **Error: vhdlan,119: Design library name STD is reserved, and can not be defined by the user. *** Error code 2 % xEIVSS-120 Message %1 Description This error was generated because you tried to map the reserved logical library name STD or SYNOPSYS. What Next Do not map the reserved logical library name STD or SYNOPSYS. For more information, see the VHDL System Simulator Core Programs Manual chapter on system configuration and the chapter on customizing your environment. Examples -- file name: .synopsys_vss.setup -- MY_STD : ./my_std MY_SYN : ./my_syn STD > MY_STD SYNOPSYS > MY_SYN Example Message % vhdlan e120.vhd % vhdlsim E **Error: vhdlsim,120: Logical library name STD is reserved, and can not be mapped by the user. **Error: vhdlsim,120: Logical library name SYNOPSYS is reserved, and can not be mapped by the user. % *@8ylIztall/sim/environ.csh For further information refer to the System Installation and Configuration Guide. Example No example. Example Message No example message. zlIyVSS-1210 Message %1 Description This error was generated because the environment variable SYNOPSYS is not set; therefore, the VHDL System Simulator is not set up properly. The environment variable SYNOPSYS is used by Synopsys VHDL System Simulator application programs to get the full pathname to the Synopsys Standard Packages. What Next Set the SYNOPSYS variable to the directory where the Synopsys VHDL System Simulator is installed. Consult your system administrator to get the full pathname to Synopsys tools. The pathname to Synopsys Standard Packages is obtained by expanding "$SYNOPSYS/$SIM_ARCH/packages/synopsys/lib". If you use csh, execute the following commands; you can add these commands to the ".cshrc" file in your home directory. If you are using a different shell, you can find similar files "environ.csh", "environ.aeg" for setting your environment in the directory "$SYNOPSYS/admin/install/sim". setenv SYNOPSYS <full-path-name-of-Synopsys-tools> source $SYNOPSYS/admin/ins2@8{IVSS-123 Message %1 Description This error was generated because you tried to map the logical library name WORK to a reserved design library name such as STD or SYNOPSYS. What Next Do not map the logical library name WORK to a reserved design library name such as STD or SYNOPSYS. For more information, see the VHDL System Simulator Core Programs Manual chapter on system configuration and the chapter on customizing your environment. Examples Following is an example of invalid library mapping in the .synopsys_vss.setup file. -- filename: .synopsys_vss.setup -- WORK > SYNOPSYS Example Message % vhdlan e123.vhd **Error: vhdlsim,123: Logical library name WORK can not be mapped to SYNOPSYS, which is reserved. % |I}W = ~who_is/$ARCH/sim/bin/window.X11 -- **Error: vhdlan,1290: -- Error in VSS SETUP File: can't find environment variable: HOME. IEEE : ~/$SYNOPSYS/$ARCH/packages/IEEE/lib 2@8}I|VSS-1290 Message %1 Description This error was generated because the analyzer could not find an environment variable or user name. What Next Define the environment variable and make sure the user name is correct. For more information, see the VHDL System Simulator Core Programs Manual chapter on system configuration and the chapter on customizing your environment. Examples -- file name: .synopsys_vss.setup -- -- error if environment variable HELP is not defined HELPDIR = $HELP/doc/sim/help/ -- error if can't find user name who_is WINDOW = ~who_is/$ARCH/sim/bin/window.X11 -- error if can't find environment variable HOME IEEE : ~/$SYNOPSYS/$ARCH/packages/IEEE/lib Example Message % vhdlan -nc e1290.vhd -- **Error: vhdlan,1290: -- Error in VSS SETUP File: can't find environment variable: HELP. HELPDIR = $HELP/doc/sim/help/ -- **Error: vhdlan,1290: -- Error in VSS SETUP File: can't find user name: who_is. WINDO~IExample Message % vhdlan -nc e12.vhd % vhdlsim E # run **Error: vhdlsim,12: Integer arithmetic overflow. e12.vhd(17): i3 := i1 + i2; # quit e@8I~VSS-12 Message %1 Description This error was generated because an overflow occurred while performing an integer arithmetic operation. The range of type integer is implementation defined. For a 32-bit platform, the type integer has the range -217483647 to 2147483647. What Next Avoid calculations that produce n integer value that is less than -217483647 or greater than 2147483647. Examples -- file name: e12.vhd entity E is end E; architecture A of E is begin P: process variable i1, i2, i3: integer; begin i1 := 1; i2 := 2147483647; -- the following statement will cause -- integer arithmetic overflow error i3 := i1 + i2; i1 := -2; i2 := -217483647; -- the following statement will cause -- integer arithmetic overflow error i3 := i1 + i2; wait; end process P; end A; J{ at thorin, started on Monday 1/4 at 15:27 **Error: vhdlsim,1300: No license for feature VSS-Simulator, version 3.0. e@8Jd contact Synopsys for a license. The license for this particular feature has expired. Check the key file and contact Synopsys to get an extension, if needed. Communication with the license server might have failed. Contact your System Administrator to shutdown and restart the license manager daemon lmgrd.  Example Following is an example of the contents of license key file: SERVER sauron 4001799 1700 DAEMON synopsysd /usr/synopsys/sparc/license/bin/synopsysd /usr/synopsys/admin/license/nls.options FEATURE VSS-Debugger synopsysd 3.0 1-jan-92 1 4BE6EC6F13E90C82FC6B "" FEATURE VSS-Simulator synopsysd 3.0 1-jan-92 1 5B16AC6FCCF1BF224ED7 "" Example Message % vhdlan -nc code.vhd **Error: SEC-51: This site is not licensed for 'VSS-Analyzer'. **Error: vhdlan,1300: No license for feature VSS-Analyzer, version 3.0. % vhdlsim -nc E **Error: SEC-50: All 'VSS-Simulator' licenses are in use. The current users of this feature are: kennedyJVSS-1300 Message %1 Description This error was generated because a license could not be checked out for a VSS tool, such as vhdlan, vhdlsim, etc. All Synopsys VSS tools (or features) need a license verification before they can be run. Each Synopsys tool is limited to a certain number of simultaneous invocations and can only be invoked up to (and including) an expiration date. The license information is contained in the license key file: $SYNOPSYS/admin/license/key This file contains information regarding the number of licenses available for each feature as well as the expiration date for each feature. What Next License for a feature can not be checked out for any of the following reasons: All the licenses available for this feature are in use. Check the license key file to see how many licenses are available for this feature. A list of all the users currently using this feature is also displayed. This particular feature is not licensed at this site. Check the key file anJ8AJ39 of vss139 is begin end ; Example Message % vhdlan -nc pack.vhd % vhdlan -nc vss139.vhd % vi pack.vhd # Modify text in pack.vhd % vhdlan -nc pack.vhd % vhdlsim -nc -t ns -its vss139 Warning: vhdlsim,139: Out of date intermediate file(s) found, and ignored. Errors including Core dumps may occur! Rerun tool without the -its flag to identify the out of date design units. #quit AJ not affect your design. Refer to the VHDL Language Reference Manual, Section 11.4, for more information. What Next If you encounter a problem after using the -its flag (core dump, unexpected results, system hang, etc), reanalyze the design and simulate without the -its flag. If you are not sure about the dependency, you should run the tool again without the -its option. This will tell you the name of the intermediate file which is out of date. If you are sure that no changes were made to this design unit, you can ignore this message. Otherwise, re-analyze all the design units that depend on the recently analyzed design unit. Example package p is -- store package p and its body in file pack.vhd function my_func(j: bit) return integer ; end; package body p is function my_func(j:bit) return integer is variable m:integer; begin return m; end; end; library work; use work.p.all; -- dependency on package p entity vss139 is end vss139; architecture a_vss1J@8AJVSS-139 Message %1 Description VHDL allows designs and packages to depend on other designs and packages. For example, if an entity is declared with a port of type std_logic, that entity is dependent on the package in which the type is declared (IEEE.std_logic_1164). Normally, when you analyze or simulate a design, a check is performed to make sure that these dependencies have been observed. A further check is made to verify that the designs and packages on which your design depends have not changed since you last analyzed files that depend on them (for example, to make sure that the std_logic type has not been removed). If these checks fail, the tool generates an error and exits. If you use the -its flag when invoking the Simulator or Analyzer, the tool will issue the warning and continue. Be aware that since the referenced design or package has changed, the tool is likely to exit abnormally. Use this flag only if you know for certain that the changes made to the referenced unit dozJ{ -- the simulation time of 4 us to fit into a 32-bit integer. wait; end process; end structural; Example Message % vhdlan -nc vss13.vhd % vhdlsim -nc vss13 # run **Error: vhdlsim,13: Simulation time overflow. vss13.vhd(12): out_signal <= '0' after 2 us; # quit Running vhdlsim as follows does not result in an error: % vhdlsim -nc -t ns vss13 J@8zJou can override the default resolution of femtoseconds by adding the option -t ps in the vhdlsim command line to allow for greater simulation times. If you still need a greater dynamic range of simulation times, use 64-bit simulation time by setting the USELONGTIME variable in the .synopsys_vss.setup file to TRUE. If you change the time base, you need to reexecute only vhdlsim. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss13 is port (out_signal: out MVL7); end vss13; architecture structural of vss13 is begin P: process begin wait for 2 us; out_signal <= '0' after 2 us; -- The line above tries to schedule a value for out_signal at time -- 4 micro-seconds (the original 2 us wait plus the 2 us delay) -- However, 4 micro-seconds can not be represented in the default -- time base of femto-seconds (4,000,000,000 fs). Running with the -- option "-t ns" sets the time base to nano-seconds and allows zJVSS-13 Message %1 Description This error was generated because the value of simulation time overflowed. Simulation time is represented as an integer value and a time base to scale by. Depending on the options you have chosen, the time value is represented by either a 32-bit integer or 64-bit integer. The time value is then scaled by the specified time base (which defaults to femtoseconds) to determine the absolute simulation time. For example, with a default base of femto-seconds, 1 nano-second would be represented as 1,000,000 femto-seconds. If the simulation time is too large to be represented by a 32-bit (or 64-bit) integer, an overflow occurs. What Next You can fix this problem either by increasing the time base (resolution limit), or by using 64-bit simulation time. You can increase the time base either with the TIMEBASE variable in the .synopsys_vss.setup file, or via the command line with the -t option. For example, if the smallest propagation delay in your design is 100ps, ys@8J; end component; begin U1 : BOTTOM Port Map (Y=>Y_SIG); -- Y_SIG driver 1 U2 : BOTTOM Port Map (Y=>Y_SIG); -- Y_SIG driver 2 end SCHEMATIC; configuration E of TOP is for SCHEMATIC for U1: BOTTOM use configuration WORK.CFG_BOTTOM; end for; end for; end E; This code analyzes without errors. The error is produced by the Simulator at simulation time. % vhdlan message140.vhd % vhdlsim -t ns E **Error: vhdlsim,140: Actual (/TOP/Y_SIG) connected to buffer port has more than one source : Connected to port /TOP/U2/Y Connected to port /TOP/U1/Y See Also For more information on the use of ports with mode buffer, refer to the following sections of the IEEE Standard VHDL Reference Manual (LRM). 1.1.1.2 Ports 4.3.1.2 Signal Declarations 4.3.3 Interface Declarations 3.2.1.1 Index Constraints and Discrete Ranges 12.6.1 Propagation of Signal Values JVSS-140 Message %1 Description There are five different modes of a port: in, out, inout, buffer, and linkage. A buffer port is similar to an out port, with some restrictions. One of these restrictions is that a buffer port may not have more than one source. Also, any actual associated with a formal buffer port may have at most one source. What Next Make sure that buffer ports contain no more than one driver, or change the mode from buffer to out. Example In the following example, Y_SIG (the actual) is driven by two buffer ports, /TOP/U1/Y and /TOP/U2/Y. library IEEE; use IEEE.STD_LOGIC_1164.all; entity BOTTOM is Port (Y : buffer STD_LOGIC); end BOTTOM; architecture BEHAVIORAL of BOTTOM is begin end BEHAVIORAL; configuration CFG_BOTTOM of BOTTOM is for BEHAVIORAL end for; end CFG_BOTTOM; library IEEE; use IEEE.STD_LOGIC_1164.all; entity TOP is end TOP; architecture SCHEMATIC of TOP is signal Y_SIG : STD_LOGIC; component BOTTOM port (Y : buffer STD_LOGIC)x@8JP consult your C compiler documentation if you are unsure. Next, check for file systems that are full. If the file system used for storing temporary files is full, redirect these files to another location by passing the -temp option to the C compiler. Example % vhdlan -nc code.vhd /: write failed, file system is full compiler(iropt) error: write_irfile: Error 0 Warning: vhdlan,1500 vld.bug(980): Error compiling file : ./E.c Reverting to Interpreted code for design unit : E. "vld.bug": errors: 0; warnings: 1. % vhdlan -nc -ccflags "-temp=/remote/sim3/tempfiles" code.vhd JVSS-1500 Message %1 Description This message results from a failure to generate the object file for the design unit under analysis. This situation is only applicable when analyzing a design unit for compiled simulation. If the analyzer is unable to produce the necessary object file, this message is issued and the analyzer reverts to generating the intermediate files necessary for an interpretive simulation. When vhdlan is invoked to generate a design unit suitable for compiled simulation, it calls upon the standard C compiler to produce an object file. If for some reason the C compiler is unable to produce this object file, the above error message is reported. The most likely cause of this error is a failure to write either the object file or the temporary files the C compiler produces. What Next Make sure you have write permissions in both the current directory and the directory used for storage of temporary files. Temporary files are usually stored on the /tmp disk, but you should@8KC exist, are mounted, and that you have read permission to. If a setup variable is incorrectly set, change its value in the .synopsys_vss.setup file and re-execute the tool that issued the error. Example -- Cannot read/write in directory % vhdlsim -nc E # coverage E157.vhd # run 200 200 FS # quit (vhdlsim): Unable to open file t.cov. % chmod +w ../examples Example -- Setup variable incorrect % vhdlsim -nc E # help mon (vhdlsim): Unable to open file vhdlsim.hlp. # quit % vi .synopsys_vss.setup See Also chmod(1V), chown(8), ls(1V), mount(8), show_vss_setup(Synopsys) KVSS-157 Message %1 Description This error message was issued because the analyzer or simulator was unable to open the named file. Synopsys software may fail to open a file for any of the following reasons: + The file does not exist. + You do not have read/write permission for this file. + You do not have read/write permission for the directory containing this file. + You do not own the file and have no read/write permission. + The software is searching for the file in the wrong directory. + The file system containing the file is not mounted. In this case, contact your system adminstrator. What Next Make sure you have permission to read/write the file and that the file system is mounted. If the Synopsys software is searching in the wrong directory for the file, check the settings of the Synopsys setup variables with the show_vss_setup command. The SYNOPSYS setup variable, HELPDIR setup variable, etc., should specify paths thatָ8CK return 42; end if; -- when 'if' is false function returns no value end; signal z: integer; begin z <= bad_funct(0); end; configuration cfg of vss16 is for vss16 end for; end; Example Message % vhdlsim -nc cfg # run **Error: vhdlsim,16: Function returned without expression. vss16.vhd(11): end if; CKVSS-16 Message %1 Description This error occured because execution reached the end of the body of a function without executing a return statement. This can occur when a function contains multiple return statements that are inside conditional statements (such as if statements or case statements), and none of the conditional statements are executed. What Next Re-check the function that ends on the line number specifed by the error message. Look for possible control paths that do not contain a return statement. Try adding a dummy statement at the end of the function and placing a breakpoint on that statement. When the simulation reaches a breakpoint, print out the local variables and parameters passed to the function. If all else fails, place a breakpoint on the function and single step thru the function. Example entity vss16 is end; Architecture a_vss16 of vss16 is function bad_funct(arg1: integer) return integer is begin if (arg1 = 1) then U|8uKVSS-18 Message %1 Description This error was generated during the elaboration of a declaration where a signal name is referenced in an expression. Section 12.3 of the VHDL LRM states: The name of a signal declared within a block cannot be referenced in expressions appearing in declarative items within a block, because the value of a signal is not defined until after the design hierarchy is elaborated. This error is a consequence of violating this rule. The VHDL analyzer, vhdlan, also issues a message that you cannot read a signal during static elaboration, as a warning of possible problems. What Next Avoid using signals in expressions within declarations. Examples entity E is end E; architecture A of E is signal SI: bit := '1'; signal SO: bit := SI; -- SI value is not defined at this level. begin end A; Example Message % vhdlan -nc code.vhd signal SO: bit := SI; Warning: vhdlan,826 code.vhd(6): Can not read signal duuKring static elaboration. "code.vhd": errors: 0; warnings: 1. %vhdlsim -nc E (vhdlsim): The following error was encountered while elaborating /E: **Error: vhdlsim,18: Attempted to read signal during elaboration or signal evaluation. @8KE with -togfile. This feature is not supported by VSS-Pro. Consider using VSS-Expert. Ignoring. # vhdlsim -nc -pro -gsvf violations m385_cfg Warning: vhdlsim,1904: Warning: Bus violation reporting requested with -gsvf. This feature is not supported by VSS-Pro. Consider using VSS-Expert. Ignoring. .fi KVSS-1904 Message %1 Description This error was generated because the feature in question is not supported by VSS-Pro. VSS-Pro does not include the support for the following features: Toggle counting Power statictics generation Bus violation reporting These features can be specified on the command line and/or in the setup file. What Next This is a warning message. The requested feature will not be supported by VSS-Pro. If you want to use these features, switch to VSS-Expert, by either specifying -expert option on the simulator command line or setting setup file variable VSS_PRODUCT = EXPERT, in your .synopsys_vss.setup file. If these features are not important for you, just ignore this error message; rest of the simulation run will not be affected. You may want to remove them from your command line or setup file or both later. Example Message # vhdlsim -nc -pro -togfile adder_toggles top_level Warning: vhdlsim,1904: Warning: Toggle counting requestedS8Kers of this feature are: sheela at jose, started on Monday 12/4 at 1:02 **Error: vhdlsim,1905: No license for feature VSS-Simulator, version 3.0. Kions FEATURE VSS-Analyzer synopsysd 3.0 1-jan-92 1 4BE6EC6F13E90C82FC6B "" FEATURE VSS-Debugger synopsysd 3.0 1-jan-92 1 4BE6EC6F13E90C82FC6B "" FEATURE VSS-Simulator synopsysd 3.0 1-jan-92 1 5B16AC6FCCF1BF224ED7 "" FEATURE VSS-CompiledSim synopsysd 3.0 1-jan-92 1 5B16AC6FCCF1BF224ED7 "" Example Message % vhdlsim -nc -expert cfg **Error: SEC-51: This site is not licensed for 'VSS-CLI'. **Error: vhdlan,1905: No license for feature VSS-CLI, version 3.0. **Error: Could not acquire all the licenses for Expert. Quitting Note:the following cfg is a file which requires interface options % vhdlsim -nc -pro cfg **Error: SEC-51: This site is not licensed for 'VSS-CLI'. **Error: vhdlsim,1905: No license for feature VSS-CLI, version 3.0. **Error: Could not acquire all the licenses for Pro. Quitting % vhdlsim -nc -pro cfg **Error: SEC-50: All 'VSS-Simulator' licenses are in use. The current usS8Kformation regarding the number of licenses available for each feature as well as the expiration date for each feature. What Next License for a feature can not be checked out for any of the following reasons: All the licenses available for this feature are in use. Check the license key file to see how many licenses are available for this feature. A list of all the users currently using this feature is also displayed. This particular feature is not licensed at this site. Check the key file and contact Synopsys for a license. The license for this particular feature has expired. Check the key file and contact Synopsys to get an extension, if needed. Communication with the license server might have failed. Contact your System Administrator to shutdown and restart the license manager daemon lmgrd.  Example Following is an example of the contents of license key file: SERVER jose 4001799 1700 DAEMON synopsysd /usr/synopsys/sparc/license/bin/synopsysd /usr/synopsys/admin/license/nls.optKVSS-1905 Message %1 Description For VSS-Expert and VSS-Pro, the error occurs when one of the required licenses could not be checked out. VSS-Expert requires having a license for each of the following: VSS-Simulator VSS-CompiledSim VSS-GateSim Interface Options : CLI and SWIFT VSS-Wave-Display (not always, only on demand)  VSS-Pro requires having a license for each of the following: VSS-Simulator VSS-CompiledSim VSS-Wave-Display (not always, only on demand)  The interface options are optional for Pro. When the user attempts to use any one of the interface options, the licenses for all interface options need to be checked out. All Synopsys VSS tools (or features) need a license verification before they can be run. Each Synopsys tool is limited to a certain number of simultaneous invocations and can only be invoked up to (and including) an expiration date. The license information is contained in the license key file: $SYNOPSYS/admin/license/key This file contains in@8 LVSS-1906 Message %1 Description This error was generated because one of the interface options was being used with VSS-Pro and no interface options license was available. Interface options license consist of the following licenses: SWIFT Interface C-Languaue Interface So each time an interface option is used with VSS-Pro, all the interface options licenses are checked out. If any of these licenses is not present, this error will be issued. This error would typically show up in a scenario where a VSS-Pro invocation tries to use an interface option and the site either does not have the interface options license or all the interface options licenses are checked out by other users. What Next Wait for other users to finish up, and then try again. Interface options while optional with VSS-Pro, are standard with VSS-Expert. Contact your Synopsys sales representative for more information. "LuVSS-1907 Message %1 Description This error was generated because VSS-Expert was being used and no interface options license was available. Interface options license consist of the following licenses: SWIFT Interface C-Languaue Interface Interface Options bundle comes standard with VSS-Expert and is optional with VSS-Pro. So each time you use VSS-Expert, you need to have the interface options license available. Interface options license can be shared between VSS-Pro and VSS-Expert. For VSS-Pro the checkout of this license is demand driven, whereas VSS-Expert needs this license to be able to run. What Next If you have VSS-Expert licenses at your site, and you can not bring up a VSS-Expert due to this error, this means that the Interface Options license is being used by another VSS-Pro on the site. Wait for other users to finish up and then try again. @87L quit 7L function bv2str(p:bit_vector) return string is variable v: string(p'left to p'right); -- The above variable declaration will cause an error if either -- bound of the parameter P falls outside the index subtype -- of STRING (1 to INTEGER'HIGH). begin -- ... return(v); end bv2str; signal s: bit_vector(0 to 7); begin P: process begin assert bv2str(s) = "00000000"; -- The above function call will cause an error at the point of -- the variable declaration in bv2str() because the left bound -- of the signal S is 0. wait; end process; end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E # run **Error: vhdlsim,19: Discrete range is not consistent with corresponding index subtype. code.vhd(5): function bv2str(p:bit_vector) return string is #@87LVSS-19 Message %1 Description This error was generated because you used a range to constrain an unconstrained array type, and the range fell outside the index subtype of the array. An unconstrained array is defined as: array(index_subtype_definition {, index_subtype_definition}) of element_subtype_indication The index_subtype_definition defines the minimum LOW bound and maximum HIGH bound. It is an error if you declare an array with a range outside of these bounds. What Next Either change the bounds of the object declaration so that they are both within the range specified by the index subtype of the array type, or change the index subtype to include the bounds used in the object declaration. If you change the array type declaration, re-analyze each design unit that depends on the array type. If you change the object declaration, re-analyze the design file that declared the object. Example entity E is end; architecture A of E is tLwnto 0); clk: in STD_LOGIC; cbus: out STD_LOGIC_VECTOR(3 downto 0)); end vss1; architecture structural of vss1 is signal x0: STD_LOGIC; signal v1: integer; begin P: process(clk) begin v1 <= 4; x0 <= abus(v1); -- The above assignment will cause an error because abus -- is only defined for indices of 3 downto 0. Thus, -- an index of 4 does not exist. -- Note: the statement x0 <= abus(4) would be caught by -- the VHDL analyzer, vhdlan, at compile time. end process; end structural; Example Message % vhdlan -nc vss1.vhd % vhdlsim -nc vss1 # run **Error: vhdlsim,1: Array subscript out of bounds. vss1.vhd(17): x0 <= abus(v1); # quit @8tLVSS-1 Message %1 Description This error was generated because an array has an index value that falls outside the declared index range of the array. A constrained array is defined in Section 4.2.1 of the VHDL LRM, as: array(discrete_range {, discrete_range}) of element_subtype_indication The discrete_range defines the minimum LOW bound and maximum HIGH bound. It is an error if you try to access an array element with an index outside these bounds. What Next Either change the bounds of the array declaration so that all sub-elements that are accessed fall within the discrete_range, or correct any errors in the code that computes the index. If you change the array type declaration, then reanalyze each design unit that depends on it. If you change the object declaration, then re-analyze the design file where the object is declared. Example library IEEE; use IEEE.std_logic_1164.all; entity vss1 is port ( abus: in STD_LOGIC_VECTOR(3 doLy architectures for -- that entity Example Message % vhdlan -nc vss204.vhd % vhdlsim -nc vss204 **Error: vhdlsim,204: No architecture is available for the specified entity. @8LVSS-204 Message %1 Description This error was generated because you specified an entity for simulation, for which no architecture exists. In VHDL, you can define several architectures for an entity. For example, an entity `adder' can have architectures for the behavioral, RTL, and gate levels. You indicate which architecture to simulate with a configuration statement, or on the command line in an entity-architecture pair. What Next Either indicate a configuration or a specific architecture for the entity you want to simulate. If no architecture exists for the entity, you must create one. If you add or change an architecture, re-analyze the files that depend on the changed file. If you want to simulate a configuration that is already defined, you do not need to re-analyze. Just run vhdlsim on the configuration. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss204 is port (out_signal: out MVL7); end vss204; -- This file defines an entity but does not define anL*is port( news : IN int256 := 0; tog : IN bit; avg: OUT int256:=0); end filter; architecture fir8 of filter is begin p : process variable oldavg :int256 := 0; begin wait on tog; oldavg := ( 7*oldavg + news) / 8 ; avg <= oldavg; end process; end fir8; Example Message % ls vss-206-a.vhd vss-206-b.vhd % vhdlan -nc vss-206-a.vhd % ls MYPKG.sim vss-206-a.vhd vss-206-b.vhd % vhdlan -nc vss-206-b.vhd % ls FILTER.mra MYPKG.sim FILTER.sim vss-206-a.vhd FILTER__FIR8.sim vss-206-b.vhd % vhdlsim -nc FILTR **Error: vhdlsim,206: Can not find specified design unit to simulate. % vhdlsim -nc FILTER # ls FILTER STANDARD MYPKG _KERNEL # q % @8LVSS-206 Message %1 Description This error was generated because the simulator or debugger could not find the specified design unit for simulation. Some possible reasons are: - You are in a wrong directory. - You have misspelled the design unit. - You have not yet analyzed the design unit. What Next If you have not analyzed your VHDL files, use vhdlan to analyze the files. The VHDL Analyzer puts the analyzed files in the VHDL design library. These files correspond to VHDL design units and provide the description used for the simulation. Invoke the Simulator with the name of the design unit. For further information, refer to the online manual pages or the VHDL System Simulator Core Programs Manual. Example -- File vss-206-a.vhd --------------------------------- package mypkg is subtype int256 is integer range 0 to 256; end mypkg; -- File vss-206-b.vhd --------------------------------- -- Contains entity and architecture for the filter. use work.mypkg.all; entity filter MLtagnum = 7) T5 CE EVENT /E/DATA(0 to 3) -- TRACE (file = E.ow, tagnum = 6) T4 CE EVENT /E/ENABLE -- TRACE (file = E.ow, tagnum = 5) T3 CE EVENT /E/DATA -- TRACE (file = E.ow, tagnum = 4) T2 CE EVENT /E/CLK3 -- TRACE (file = E.ow, tagnum = 3) T1 CE EVENT /E/CLK2 -- TRACE (file = E.ow, tagnum = 2) T CE EVENT /E/CLK1 -- TRACE (file = E.ow, tagnum = 1) # delete T6 -- delete trace corresponding to data(4) # trace data(4) -- allowed since this object is not currently being traced # quit @8M T3 CE EVENT /E/DATA -- TRACE (file = E.ow, tagnum = 4) T2 CE EVENT /E/CLK3 -- TRACE (file = E.ow, tagnum = 3) T1 CE EVENT /E/CLK2 -- TRACE (file = E.ow, tagnum = 2) T CE EVENT /E/CLK1 -- TRACE (file = E.ow, tagnum = 1) # # trace data (vhdlsim): "data" is already being traced, trace command ignored. # trace data(0 to 15) -- whole bus already being traced (vhdlsim): "data(0 to 15)" is already being traced, trace command ignored. # trace data(0 to 3) -- allowed since the slice specification is unique # trace data(4) -- allowed since the slice specification is unique # trace data(0 to 7) -- allowed since the slice specification is unique # trace data(4) -- already being traced (vhdlsim): "data(4)" is already being traced, trace command ignored. # list -l -- list all the traces T7 CE EVENT /E/DATA(0 to 7) -- TRACE (file = E.ow, tagnum = 8) T6 CE EVENT /E/DATA(4) -- TRACE (file = E.ow, Mo a single vector object. Occasionally, you may want to display part of a vector object as a separate waveform. The VHDL System Simulator can separately trace a slice of the vector object even if it is already tracing the whole range of the vector object. Example % cat code.vhd entity e is end e; architecture A of E is signal clk1 : bit; signal data : bit_vector(0 to 15); signal enable : bit := '0'; signal clk2 : bit; signal clk3 : bit; .... .... begin .... .... end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E # cd e # trace clk*'signal -- trace all the clk signals first # trace *'signal -- trace the remaining signals (vhdlsim): "CLK1" is already being traced, trace command ignored. (vhdlsim): "CLK2" is already being traced, trace command ignored. (vhdlsim): "CLK3" is already being traced, trace command ignored. # list -l T4 CE EVENT /E/ENABLE -- TRACE (file = E.ow, tagnum = 5) A8MVSS-235 Message %1 Description This error was generated because a trace command was issued for a VHDL object, that the Simulator was already tracing. VSS allows only one trace monitor to be present at any given time for a given object. A scalar object can have only one trace monitor. Similarly, there can be only one trace associated with each slice of a vector object. Thus, it is an error to trace a vector object twice if the range indicated for the vector object in the trace command exactly matches the range indicated during the previous invocation of the trace command. See the example below for details. What Next Typically, there is no need to trace the same object twice. If you are viewing the traced objects in a waveform viewer window, then use the Edit->Duplicate pulldown menu in the waveform viewer window to display a duplicate of the waveform. Other commands are available from the waveform viewer's menubar for expanding a vector and for combining multiple trace objects intdMyt collapsed ); end component; signal k : res_sig; begin c1 : sub_comp port map (j => k); end; configuration cfg of vss244 is for a_vss244 end for; end; Example Message % vhdlan -nc vss244.vhd % vhdlsim -nc -t ns vss80 # cd vss244/c1 # monitor event j (vhdlsim): Signal (/VSS244/C1/J) is collapsed. # quit A8dMg is resolve_drivers bit; end p; package body p is function resolve_drivers(q: bit_vector) return bit is begin for i in q'range loop if q(i) = '1' then return '0'; elsif q(i) = '0' then return '1'; end if; end loop; end; end p; library work; use work.p.all; entity sub_comp is port ( j : out res_sig ); end sub_comp; architecture a_sub_comp of sub_comp is begin P1: process begin j <= '1'; wait for 20 ns; j <= '0'; wait for 20 ns; end process; end; library work; use work.p.all; entity vss244 is end vss244; architecture a_vss244 of vss244 is component sub_comp port ( j : out res_sig -- port of mode OUT will -- gedMVSS-244 Message %1 Description The VHDL System Simulator has certain optimization built into its kernel to improve the performance of the simulator. When this optimization is enabled, a port of mode OUT of resolved type is collapsed (removed from the signal network) if it is not a top-level port. This error message was generated because the name of a collapsed port was passed to a Simulator command that takes a signal object as an argumentN. These commands are "ls","monitor","trace","eval","assign", and "hold". If you need to use one or more of these commands for a collapsed port, you can disable the optimization by setting the RESFUNC_OPT variable in your .synopsys_vss.setup file to NO_OPT. What Next If you want to use one of the commands listed above on the collapsed port, set the RESFUNC_OPT setup variable to NO_OPT in the .synopsys_vss.setup file. Re-invoke the simulator. Example package p is function resolve_drivers(q : bit_vector) return bit; subtype res_siA8M_D_CK = -4 + 4 -1 = -1 ns ---- bad result thold_D_CK = 3 - 4 + 1 = 0 ns What Next Check to make sure that the sum of SETUP and HOLD delays in the same CLOCK and DATA pins is equal or greater than zero.  See Also vss-298 MVSS-297 Message %1 Description This is a warning message from NCC (Negative Constraint Calculation), besides giving a warning message, NCC also sets the offending value to zero. When the sum of SETUP and HOLD times is less than zero, NCC cannot generate a valid SETUP or HOLD result after calculation. The following NCC algorithm is used to determine clock and signal delays as well as the adjusted SETUP/HOLD delays for negative constraints: /* internal clock and signal delays for negative constraints*/ ticd_CK = ABS (MIN (0, MIN(tsetup_*_CK, trecovery_*_CK, ...))) tisd_D_CK = ABS (MIN (0, (MIN(thold_D_CK, tremoval_D_CK, ...)- ticd_CK))) /* adjustment of SETUP and HOLD time */ tsetup_D_CK = tsetup_D_CK + ticd_CK - tisd_D_CK thold_D_CK = thold_D_CK - ticd_CK + tisd_D_CK /* NOTE: above generics' name are using VITAL generic rules */ Example of bad data: tsetup_D_CK = -4 ns, thold_C_CK = 3 ns, Result from NCC: ticd_CK = ABS(-4) = 4 ns, tisd_D_CK = ABS(MIN (0, (3-4))) = 1 ns, tsetup%A8Mom NCC: ticd_CK = ABS(-3) = 3 ns, tisd_D_CK = ABS(MIN (0, (5-3))) = 0 ns, tpd_CK_Q = 1 - 3 = -2 ns ---- bad result What Next Check to make sure that the IOPATH delay is not less than its corresponding ticd (or tisd) delay.  See Also vss-297 MVSS-298 Message %1 Description This is a warning message from NCC (Negative Constraint Calculation), besides giving a warnning message, NCC also sets the negative value to zero. When the IOPATH delay is less than its corresponding internal clock (or signal) delay, the new IOPATH delay is negative and invalid. The following NCC algorithm is used to determine internal clock and signal delays as well as the adjusted IOPATH delay: /* internal clock and signal delays for negative constraints*/ ticd_CK = ABS (MIN (0, MIN(tsetup_*_CK, trecovery_*_CK, ...))) tisd_D_CK = ABS (MIN (0, (MIN(thold_D_CK, tremoval_D_CK, ...)- ticd_CK))) /* adjustment of IOPATH delay */ tpd_CK_Q = tpd_CK_Q - ticd_CK tpd_D_Q = tpd_D_Q - tisd_D_CK /* adjustment of SETUP and HOLD time */ tsetup_D_CK = tsetu_D_CK + ticd_CK - tisd_D_CK thold_D_CK = thold_D_CK - ticd_CK + tisd_D_CK /* NOTE: above generics' name use VITAL generic rules */ Example: tsetup_D_CK = -3 ns, thold_C_CK = 5 ns, tpd_CK_Q = 1 ns, Result fr@8MT of a floating -- point type. end process; end structural2; Example Message vhdlsim vss2 structural1 # run **Error: vhdlsim,2: Constraint error. vss2.vhd(15): aint <= v1; # quit vhdlsim vss2 structural2 # run **Error: vhdlsim,2: Constraint error. vss2.vhd(25): v3 <= 3 ** v2; # quit Mnalyze each design unit that depends on the type declaration. If you change the object declaration, re-analyze the design file that contains the declaration. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss2 is port ( aint: out integer range 0 to 10; -- The above line will only allow values between 0 and 10 inclusive to be -- assigned to the signal aint. clk: in MVL7); end vss2; architecture structural1 of vss2 is signal v1: integer; begin P: process(clk) begin v1 <= 11; aint <= v1; -- The above line will generate an error since 11 does not fall within -- the declared range constraint of the signal aint (0 to 10). end process; end structural1; architecture structural2 of vss2 is signal v1, v2: integer; begin P: process(clk) begin v1 <= -2; v2 <= 3 ** v1; -- The above will generate a constraint error since exponentiation with -- negative exponents is only allowed for the left operand1A8MVSS-2 Message %1 Description This error was generated because you assigned a value to an object, and that value does not fall within the declared range of the object. A subtype indication with range constraints is defined as: subtype_indication ::= [resolution_function_name] type_mark [constraint] constraint ::= range_constraint | index_constraint range_constraint ::= range range range ::= range_attribute_name | simple_expression direction simple_expression If a simple range constraint, such as `0 to 10', is specified for a signal, then that constraint defines the minimum LOW bound and maximum HIGH bound of values for the constrained object. It is an error to assign the object a value outside of these bounds. What Next Either change the bounds of the object declaration so that the values you assign to it fall within the specified range, or change any errors in the code that cause incorrect values to be assigned to the object. If you change a type declaration, re-aIN port map ( CONV(A) => CONV(TA), Z => TZ ); end test_a; configuration test_cfg of test_e is for test_a for U1 : e use configuration WORK.cfg; end for; end for; end test_cfg; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E **Error: vhdlsim,33: Error: Can not use type conversion functions in port association lists when the actual is of a resolved type Error occurred on Signal /TEST_E/U1/A. 6A8INVSS-33 Message %1 Description This error is generated when a type conversion function is used in a port association when the actual is of a resolved type. This will be fixed in the next release. What Next There are two ways around this: - Eliminate the type conversion in the port association by doing the type conversion locally inside the entity and pass the converted signal through the port association. Instead of associating port map( a => tcf(b)); Do b_local <= tcf(b); port map( a => b_local ) - If the signal is not actually resolved (i.e., it has only one driver), you can use an equivalent unresolved type. For example, if the signal in question is of the type std_logic, you can use std_ulogic. Example entity test_e is end test_e; Architecture test_a of test_e is signal TA : MYTYPE_VECTOR (1 to 2); signal TZ : MVL7; component e port ( A : inout MVL7_VECTOR (1 to 2); Z : out MVL7 ); end component; begin U1 : e Nror when using the result of a type converted INOUT port in another port association. Please call the hotline. Error occurred on Signal /TEST_E/U1/Z connected to /TEST_E/U1/U1/Z2. 6A8N WORK.pkg.all; entity e is port ( Z : inout std_logic ); end e; architecture a of e is component e2 port ( Z2 : in std_logic ); end component; begin U1 : e2 port map ( Z2 => Z ); P1: process begin Z <= '1'; wait; end process; end a; configuration cfg of e is for a end for; end cfg; library IEEE; use IEEE.std_logic_1164.all; use WORK.pkg.all; entity test_e is end test_e; Architecture test_a of test_e is signal TZ : std_logic_vector(2 downto 1); component e port ( Z : inout std_logic ); end component; begin U1 : e port map ( CONV(Z) => CONV(TZ)); P1: process begin TZ <= "ZZ"; wait; end process; end test_a; configuration c of test_e is for test_a for U1 : e use configuration WORK.cfg; end for; end for; end c; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E vhdlsim,34: Error: There is an implementation erNVSS-34 Message %1 Description This error is generated when an actual to formal (or 'down') type conversion function is used and the result of that function is passed down to another component through a port association of mode IN or INOUT. This will be fixed in the next release. What Next There are two ways around this problem, both of which introduce delta-cycle delays. - Copy the result of the TCF locally in the entity and use that signal in the lower port map. - Eliminate the type conversion in the port association by doing the type conversion locally inside the entity and pass the converted signal through the port association. Instead of associating port map( a => tcf(b)); Do b_local <= tcf(b); port map( a => b_local ) Example library IEEE; use IEEE.std_logic_1164.all; use WORK.pkg.all; entity e2 is port ( Z2 : in std_logic ); end e2; architecture a of e2 is signal Z3 : std_logic; begin Z3 <= Z2; end a; library IEEE; use IEEE.std_logic_1164.all; use fprint "%s" s2 > end # run 10 FS s2 ^ (vhdlsim): Expression is of the wrong type. # q % dA8TOVSS-46 Message %1 Description This error was generated by the Simulator because an expression did not match an expected type. If you were using the Simulator's 'fprint' command, a format conversion character did not match the actual value in the command. What Next Look at all the {argument} expressions that follow the format_string in the 'fprint' command, and make sure each (vhdl) expression type matches the (implied) type of the format conversion character. Examples entity e is end e; architecture a of e is function f2 (p : integer) return bit_vector is variable st : bit_vector(p downto 1); begin for i in st'range loop st(i) := '0'; end loop; return st; end f2; signal s1 : integer := 0; signal s2 : bit := '1'; signal s3 : bit_vector(8 downto 1); begin with s2 select O8 vss49 # cd vss49 # ls P X0 # ls b_func(0) ^ (vhdlsim) : Not a valid name. # ls p'blah ^ (vhdlsim) : Not a valid name. # status p'blah ^ (vhdlsim) : Not a valid name. # where p'blah ^ (vhdlsim) : Not a valid name. (vhdlsim) : Not Running. # quit jA8OVSS-49 Message %1 Description This error was generated because you used an invalid name as an argument to an interactive command in the Simulator Control Language that takes a vhdl_object_name. The commands that take vhdl_object_name are "ls","cd","status",and "where". What Next Find the object_names that are visible in the current working region by using "ls" command. The object names in this list are the only valid arguments to the interactive commands listed above. Example package my_pack is function b_func(val : integer) return bit; end my_pack; package body my_pack is function b_func(val : integer) return bit is begin return ('1'); end; end; library WORK; use WORK.my_pack.all; entity vss49 is end vss49; architecture structural of vss49 is signal x0: bit; begin P: process begin wait for 10 ns; end process; end structural; Example Message % vhdlan -nc vss49.vhd % vhdlsim -nc -t nsO -- Boolean type. However, two versions of the function -- 'To_X01' are applicable here: one which returns -- 'std_logic_vector' and the other which returns -- 'std_ulogic_vector'. The choice of conversion -- function determines which of the overloaded `=' -- operators to use. But since the Analyzer cannot -- tell which conversion function to use, it cannot -- tell which equality operator to use, either. s1 <= 1; end if; wait for 10 ns; end process; end; Example Message % vhdlan -nc err501.vhd if (To_X01(s3) = To_X01(s2)) then ^ **Error: vhdlan,501 err501.vhd(15): Expression is ambiguous. "err501.vhd": errors: 1; warnings: 0. % jA8OVSS-501 Message %1 Description This error was generated because the analyzer could not determine the type and expected type of an expression (or part of an expression). The analyzer checks that the type of an expression matches the expected type for this expression. In some cases (specifically, if you use overloaded functions as part of the expression), the Analyzer cannot determine which function you mean. What Next You can help the Analyzer by type qualifing expressions (or sub-expressions). Always qualify overloaded functions or literals. Examples entity e is end e; library IEEE; use ieee.std_logic_1164.all; architecture a of e is signal s1 : integer := 0; signal s2 : bit_vector(7 downto 0); signal s3 : bit_vector(7 downto 0); begin process begin if (To_X01(s3) = To_X01(s2)) then -- This expression is ambiguous. The Analyzer -- expects the 'if' expression to be of Ps A V # q % iA8Pttribute: name'declared(i), where `name' is the name of the overloaded item and `i' is the number of the declaration you want to access in a region, counting the declarations from the top of the region. This attribute is NOT a VHDL attribute and it is valid only as part of a hierarchy name in the Simulator. Examples entity e is end e; architecture a of e is function foo (a : in integer) return integer is variable v : integer; begin v := a -1; return(v); end foo; function foo (a : in bit) return integer is variable v : integer; begin v := 0; if (a = '1') then v := 1; end if; return(v); end foo; begin end; Example Message % vhdlan -nc err50.vhd % vhdlsim -nc e # ls E STANDARD _KERNEL # cd e/foo e/foo ^ (vhdlsim): Name is ambiguous. # cd e/foo'declared(2) # lPVSS-50 Message %1 Description This error was generated by the Simulator because it could not determine the meaning of a name. You specified a hierarchical path name to an object as part of a command, in a CLI model, or in back-annotation, that the Simulator could not resolve with the runtime environment. The ambiguous name is an overloaded name. Overloaded names are function, procedure, enumeration literal, or operator symbol names that are the same sequence of character literals. The analyzer uses the parameter result profile of the function to find the correct match for that name. For more information on parameter result profiles, see the VHDL Language Reference Manual, Section 2.3. You can use an overloaded name as part of a runtime command without giving all the information required to construct the parameter result profile. The name is then ambiguous to the Simulator. What Next To prevent this situation, indicate the particular declared name you want to access. Use a special a{A8PPc i1 := r1 + i2; -- mixing types REAL and INTEGER b1 := i2 > t1; -- mixing types INTEGER and TIME b1 := r1 <= i2; -- mixing types REAL and INTEGER wait; end process; end; NOTE: When converting from REAL to INTEGER, ensure that you do not violate the range constraints inherent in type INTEGER. See Also The following LRM sections describe binary operators, operator overloading, type conversions, and expressions in general: 2.3.1 Operator Overloading 7. Expressions 7.2 Operators 7.2.1 Logical Operators 7.2.2 Relational Operators 7.2.3 Adding Operators 7.2.4 Multiplying Operators 7.2.5 Miscellaneous Operators 7.3.5 Type Conversions 7.4 Static Expressions 7.5 Universal Expressions 10.5 The Context of Overload Resolution 14.2 Package STANDARD PPteger) return integer is variable result : integer; begin if a > REAL(INTEGER'HIGH) then assert FALSE report "INTEGER overflow" severity WARNING; result := integer'high; elsif a < REAL(INTEGER'LOW) then assert FALSE report "INTEGER overflow" severity WARNING; result := integer'low; else result := INTEGER(a) + b; end if; return result; end; function ">"(a : integer; b : time) return boolean is constant time_base_unit : TIME := TIME'VAL(1); begin return a > (b / time_base_unit); end; function "<="(a : real; b : integer) return boolean is begin return a <= REAL(b); end; end p; use WORK.P.all; entity e is end; architecture a of e is begin process variable i1 : integer; variable i2 : positive; variable r1 : real; variable t1 : TIME := 0 ns; variable b1 : boolean; begin {A8PPrror: vhdlan,523 test523.vhd(nn): Type mismatch on left and/or right operand of binary operator. Modifying your code One solution is to modify your code as follows: entity e is end; architecture a of e is begin process variable i1 : integer; variable i2 : positive; variable r1 : real; variable t1 : TIME := 0 ns; variable b1 : boolean; begin i1 := INTEGER(r1) + i2; -- mixing types REAL and INTEGER b1 := i2 > (t1/1 ns); -- mixing types INTEGER and TIME b1 := r1 <= REAL(i2); -- mixing types REAL and INTEGER end process; end; Creating Operator Overload Functions Another solution is to create a new function or a set of functions to allow operand type mixing. One possible solution follows. package p is function "+"(a : real; b : integer) return integer; function ">"(a : integer; b : time) return boolean; function "<="(a : real; b : integer) return boolean; end p; package body p is function "+"(a : real; b : inPPultiplying operators * and /, with a few differences. If the type of one operand is REAL, and the type of the other operand is INTEGER, an implicit type conversion occurs, and the resulting type is REAL. What Next There are two solutions to this problem. Either you can modify your code to use consistent (related) types in all operations, or you can overload the predefined operators with new functions to allow operands of the types you want to use. Example The following code does not analyze: entity e is end; architecture a of e is begin process variable i1 : integer; variable i2 : positive; variable r1 : real; variable t1 : TIME := 0 ns; variable b1 : boolean; begin i1 := r1 + i2; -- line 13; mixing types REAL and INTEGER b1 := i2 > t1; -- line 14; mixing types INTEGER and TIME b1 := r1 <= i2; -- line 15; mixing types REAL and INTEGER end process; end; Lines 13, 14, and 15 each produce the following error message: **E{A8PPor, nand, nor, and xor are defined for predefined types BIT and BOOLEAN, but not for any other types. Relational Operators The predefined binary relational operators include tests for equality (=), inequality (/=), and ordering of operands (<, <=, >, >=). Both operands of each relational operator must be of the same type. The resulting type of each relational operator is BOOLEAN. Adding Operators The predefined binary adding operators (+ and -) are defined for any numeric type and have the conventional (arithmetic) meaning. Both operands of each adding operator must be of the same numeric type, though subtypes can be different. The result is the same numeric type. For integer types and subtypes (INTEGER, POSITIVE, NATURAL, and user-defined INTEGER subtypes), the result type is INTEGER. For type REAL and user-defined REAL subtypes, the resulting type is REAL. Multiplying Operators The restrictions specified under 'Adding Operators' above are also applicable to the predefined binary mPPVSS-523 Message %1 Description The VHDL language is generally more restrictive than other languages when using operands of different types on either side of a predefined binary operator. An example of a predefined binary operator is the '+' sign in the following equation: v1 := 1 + 4; In VHDL, the classes of binary operators are logical, relational, adding (includes subtraction), multiplying (includes division), and miscellaneous. The predefined set of operations allowed with each operator is well defined. These sets of operations are outlined here. For complete information, refer to the IEEE Standard VHDL Language Reference Manual (LRM). Relevant sections are listed in the See Also section of this manual page. Additionally, only information on binary operations involving scalar types is included here. For information on binary operations involving non-scalar types (for example, arrays or records), refer to the LRM. Logical Operators The predefined binary logical operators and, A8P e is end; architecture a of e is begin process variable b1 : bit; variable i1 : integer; begin b1 := not b1; i1 := -i1; wait; end process; end; The behavior here is different from that in the first solution. An overload function for the logical negation operator not has been defined to support INTEGER. See Also The following LRM sections describe binary operators, operator overloading, type conversions, and expressions in general. 2.3.1 Operator Overloading 7. Expressions 7.2 Operators 7.2.1 Logical Operators 7.2.3 Adding Operators 7.2.5 Miscellaneous Operators 10.5 The Context of Overload Resolution 14.2 Package STANDARD P Type mismatch on operand of unary operator. Modifying your code One solution is to modify your code as follows: entity e is end; architecture a of e is begin process variable b1 : bit; variable i1 : integer; begin b1 := not b1; i1 := -i1; wait; end process; end; This example uses a compatible type/operator pair; however, the resulting behavior of the component may not be what you intended. Creating Operator Overload Functions Another solution is to create a new function or a set of functions to define the unary operation you want. One possible solution follows. package p is function "-"(a : bit) return bit; function "not"(a : integer) return integer; end p; package body p is function "-"(a : bit) return bit is begin return not a; end; function "not"(a : integer) return integer is begin if a = 0 then return 1; else return 0; end if; end; end p; use WORK.P.all; entityA8P negation: Unary - The predefined operations support types INTEGER, REAL, TIME, POSITIVE, and NATURAL. Logical negation: not The predefined operations support only types BIT, and BOOLEAN. Arithmetic absolute value: abs The predefined operations support types INTEGER, REAL, TIME, POSITIVE, and NATURAL. What Next There are two solutions to this problem. Either you can modify your code to use consistent (related) types in all operations, or you can overload the predefined operators with new functions to allow operands of the types you want to use. Example The following code is not correct: entity e is end; architecture a of e is begin process variable b1 : bit; variable i1 : integer; begin b1 := -b1; -- line 10; unsupported unary operation for type BIT i1 := not i1; -- line 11; unsupported unary operator for type INTEGER wait; end process; end; Lines 10 and 11 each produce the following error message: **Error: vhdlan,524 test524.vhd(nn): PVSS-524 Message %1 Description This error message was generated because you used a type/operator pair that was not defined. In VHDL, the small set of unary operator includes unary +; unary - (arithmetic negation); not (logical negation); and abs (arithmetic absolute value). Not all types of operands are supported by each of the unary operators. An example of a predefined unary operator is 'abs', used in the following equation: v1 := abs(-4); The predefined set of operations allowed with each operator is well-defined. These sets of operations are outlined here. For complete information, refer to the IEEE Standard VHDL Language Reference Manual (LRM). Relevant sections of the LRM are listed in the See Also section of this manual page. In the following sections, if a type is not listed as supported, then there is no predefined operation for this combination of type and operator. Unary + The predefined operations support types INTEGER, REAL, TIME, POSITIVE, and NATURAL. ArithmeticA8hQ8n,542 /remote/dtg310/shankha/STARS/24949/24949.vhd(10): Element association associates the same formal more than once. L2:c port map (c => s, d => t, c => s); ^ **Error: vhdlan,542 /remote/dtg310/shankha/STARS/24949/24949.vhd(11): Element association associates the same formal more than once. L3:c port map (c => s, d => t, c(1) => s(1)); ^ **Error: vhdlan,542 /remote/dtg310/shankha/STARS/24949/24949.vhd(12): Element association associates the same formal more than once. hQ2); begin L1:c port map (c(1) => s(1), d(1) => t(1), c(2) => s(2), d(2) => t(2)); end a; In the above example, all subelement associations of c and d do not appear in a contiguous sequence. The corrected association list would appear as: L1:c port map (c(1) => s(1), c(2) => s(2), d(1) => t(1), d(2) => t(2)); Example % cat code.vhd architecture a of e is component c port (c: bit_vector (1 to 2); d: bit_vector (1 to 2)); end component; signal s, t: bit_vector (1 to 2); begin L1:c port map (c(1) => s(1), d(1) => t(1), c(2) => s(2), d(2) => t(2)); L2:c port map (c => s, d => t, c => s); L3:c port map (c => s, d => t, c(1) => s(1)); end a; Example Message % vhdlan -nc code.vhd c(2) => s(2), d(2) => t(2)); ^ **Error: vhdlaA8hQVSS-542 Message %1 Description Error message 542 will be emitted in one of two cases: If any subelement of a formal is associated more than once, and If subelement association of the formal does not appear in a contiguous sequence in the association list.  An example of case 1 follows: architecture a of e is component c port (c: bit_vector (1 to 2); d: bit_vector (1 to 2)); end component; signal s, t: bit_vector (1 to 2); begin L1:c port map (c => s, d => t, c(1) => s(1)); end a; In the above example, subelement c(1) is being associated more than once in the association list. The correct association list would associate subelement c(1) only once. An example of case 2 follows: architecture a of e is component c port (c: bit_vector (1 to 2); d: bit_vector (1 to 2)); end component; signal s, t: bit_vector (1 to Q for A for all : C use entity work.E(A); end for; end for; end; Example Message % vhdlan -nc code.vhd generic map(N => VAL) -- Formal (N) is of type thousand; **Error: vhdlan,543 code.vhd(37): Actual designator not of the correct type - THOUSAND expected. port map (A => B); -- Formal (A) is of type mybit_vector1; **Error: vhdlan,543 code.vhd(40): Actual designator not of the correct type - MYBIT_VECTOR1 expected. A8Q type million is range 0 to 1000000; -- create two different types that differ only in their names type mybit_vector1 is array (integer range <> ) of bit; type mybit_vector2 is array (integer range <> ) of bit; end p; -- use work.p.all; entity e is generic ( N : thousand := 999); port ( A : mybit_vector1(0 to 7)); end e; architecture A of E is begin end; -- use work.p.all; entity e2 is end; architecture A of e2 is component C generic ( N : thousand); port ( A : mybit_vector1(0 to 7)); end component; signal VAL : million := 999; signal B : mybit_vector2(0 to 7); begin UUT : C generic map(N => VAL) -- Formal (N) is of type thousand; -- Actual (VAL) is of type million; port map (A => B); -- Formal (A) is of type mybit_vector1; -- Actual (B) is of type mybit_vector2; end; configuration C of E2 is Qle s : integer := 1; variable p : integer; begin p := addten(s); -- s is an actual variable end process; end; This error was generated because an actual designator was of a different type than that of the associated formal. Since VHDL is a strongly typed language, it requires that both the actual and formal belong to the exact same type, unless you specify a type conversion function. It is also an error to connect two objects belonging to two different types, whose type declarations differ only in their names. See `Example' below for such usage. What Next Correct the source so that both the formal and the actual belong to the exact same type, or you may need to use a type conversion function, to convert between the two types. In either case, after the source file is changed, reanalyze all the designs that depend on the design unit where the change was made. Example % cat code.vhd package p is type thousand is range 0 to 1000; A8QVSS-543 Message %1 Description In VHDL, a formal is defined to be either a formal port or formal generic of a design entity, or a formal parameter of a subprogram. An example of a formal follows: package body P is function addten (val:integer) return integer is -- val is a formal parameter of the subprogram addten begin return (val+10); end; end P; entity e is generic ( gen : TIME := 5 ns); -- gen is a formal generic port ( prt : bit ); -- prt is a formal port end; An actual is either an expression, a port, a signal, or a variable associated with a formal port, formal parameter, or formal generic. The following example illustrates the concept of an actual: architecture A of Example is signal act_prt : bit := '0'; begin UUT : E generic map( gen => 10 NS) -- 10 NS is an actual expression port map ( prt => act_prt); -- act_prt is an actual signal P : process variab*Rs2(c1); ^ **Error: vhdlan,565 /remote/dtg310/shankha/j.vhd(5): Type conversion operand and result type must have matching elements in each dimension. "code.vhd": errors: 1; warnings: 0. A8*RVSS-565 Message %1 Description This error message is generated when the number of elements in the operand to a type conversion function is not the same as the target to which the result is being assigned. What Next The user needs to modify the number of elements in either the target or the operand so that the numbers match. Examples The following example illustrates the error: package p is subtype s1 is bit_vector(1 to 2); subtype s2 is bit_vector(1 to 4); constant c1: s1 := (others=>'1'); constant c2: s2 := s2(c1); end; The initializer of constant c2 contains a type conversion function which provides for a conversion of a constant of type s1 into a constant of type s2. However, since the operand, c1, has two elements (as specified by its type) and the type s2 requires four elements, the initializer is erroneous. The solution would be to make the number of elements of s1 and s2 match. Example Message % vhdlan -nc code.vhd constant c2: s2 := SRVSS-567 Message %1 Description This error was generated because you tried to take a slice of an object that is not a one-dimensional array. A slice name is defined as: prefix ( discrete_range ) What Next Change the prefix of the slice name so that it is a one-dimensional array object. Examples The following example shows an invalid and a valid prefix: entity E is signal b: bit; signal bv: bit_vector(1 to 7); begin assert b(1 to 1) = b; -- The prefix of the slice is not a one-dimensional array assert bv(1 to 1) = "1"; end; Example Message % vhdlan -nc code.vhd assert b(1 to 1) = b; ^ **Error: vhdlan,567 code.vhd(5): Prefix is not appropriate for slice name. "code.vhd": errors: 1; warnings: 0. A8~Rss; P1: process variable bar, sign : bit; begin sign := bar(7); -- Because of visibility, bar above refers to the variable and not to -- the signal bar that was intended. wait; end process; end; Example Message % vhdlan -nc vss-568a.vhd sign := foo(7); ^ **Error: vhdlan,568 vss-568a.vhd(16): Prefix of name can not be interpreted as a subprogram or array. sign := bar(7); ^ **Error: vhdlan,568 vss-568a.vhd(24): Prefix of name can not be interpreted as a subprogram or array. "vss-568a.vhd": errors: 2; warnings: 0. % ~RVSS-568 Message %1 Description This error was generated by the Analyzer when it tried to interpret a VHDL fragment of the form "prefix ( optional_association_list )". In that context, the prefix should be a subprogram or an array. But the Analyzer was unable to find a valid interpretation for that name as a subprogram or an array. What Next Check that the prefix indicated by the error message is either an array name or a subprogram name, correct the VHDL code, and re-analyze the file(s). Example -- File: vss-568a.vhd entity E is end; architecture A of E is type byte is array (Integer range 7 downto 0) of BIT; function foo return byte is variable v : byte := X"13"; begin return (v); end; signal bar : byte; begin P0: process variable foo, sign : bit; begin sign := foo(7); -- Because of visibility, foo above refers to the variable and not to -- the function call that was intended. wait; end proce۸8Ration on the use of selected names, refer to the following sections of the IEEE Standard VHDL Language Reference Manual (LRM). 06.3 Selected Names 10.3 Visibility Rules Rn the following example. package P is constant C1 : integer := 1; end P; package body P is constant C2 : integer := 2; end P; use WORK.all; entity e is constant C3 : integer := P.C1; -- ok; C1 visible constant C4 : integer := P.C2; -- Error, line 13 -- C2 declared in package body end e; Analyzing the above code produces the error: **Error: vhdlan,573 test573.vhd(13): No selected element named C2 is defined for this prefix. Example - Incorrect use of a record element This situation occurs when you refer to an element of a record that is a type and not an object, as shown in the following example. package P is type RT is record EL_A : BIT; EL_B : BIT; end record; constant C1: BIT := RT.EL_B; -- Error, line 7 -- RT.EL_B has no value end P; Analyzing the above code produces this error: **Error: vhdlan,573 test573.vhd(7): No selected element named EL_B is defined for this prefix See Also For more inform۸8R2.C1; -- Error, line 9 (typo) -- There is no constant C1 declared in P2; -- P2 is not fully declared end P2; Analyzing the above code produces the following error: **Error: vhdlan,573 test573.vhd(9): No selected element named C1 is defined for this prefix. Example - Missing or incomplete use clause Check to make sure that your package name exists in the associated library. The following example uses a package name that does not exist in the associated library. use WORK.PACKAGE_NAME.all; -- Error, line 1 -- There is no package PACKAGE_NAME in library WORK. entity e is end e; In this case, the library is visible, but there is no such package in the library. The example above produces the following error: **Error: vhdlan,573 test573.vhd(1): No selected element named PACKAGE_NAME is defined for this prefix. Example - Object declared in a package body Objects declared in package bodies are not visible outside the package body where they are declared, as shown iRVSS-573 Message %1 Description This error was generated because a selected name is in an invalid format. A selected name is a name with the format prefix.suffix. You can use a selected name to denote an element of a record, an object designated by an access value, or an entity whose declaration is contained within another named entity, particularly within a library or a package. You can also use a selected name to denote all entities whose declarations are contained in a library or a package. What Next Modify the format of the selected name, which was invalid because of a missing or incorrectly formed use clause; a typo; or incorrect use of a record element. Example - Typographical error in name Check each portion of the selected name to ensure that no misspellings have occurred; the following example contains a misspelling. package P1 is constant C1 : integer := 0; end P1; use WORK.all; package P2 is constant C2 : integer := P1.C1; -- ok constant C3 : integer := PJ8#Sext Eliminate the homographs by renaming one of them or by explicitly specifying which definition you want. For example: z := work.q.foo(x); Examples package p is function foo (x: bit) return bit; end; package q is type foo_t is array(bit) of bit; constant foo : foo_t; end; entity e is end; use work.p.all; use work.q.all; Architecture A of e is begin p0: process variable x,z: bit; begin x := '1'; z := foo(x); end process; end; Example Message %vhdlan vss-574.vhd z := foo(x); ^ **Error: vhdlan,574 vss-574.vhd(19): Identifier is not visible because it is ambiguous (homographs were introduced by USE clauses). #SVSS-574 Message %1 Description This error occured because multiple definitions of a name are visible at a given point, and the definitions are homographs of each other. The VHDL Language Reference Manual, Section 10.3, states: "Two declarations are said to be homograph of the other if both declarations have the same identifier and overloading is allowed for at most one of the two. If overloading is allowed for both declarations, then each of the two is a homograph of the other if they have the same identifier, operator symbol, or character literal, as well as the same parameter and the result profile." The example below should make this clear. In this example, the name foo is defined in both packages p and q. They are homographs because the definition of foo in package p is overloadable (it is a function) whereas the definition foo in package q is not overloadable. In the process p0 when a reference is made to foo, the analyzer is unable to determine which definition to use. What NA8ZSVSS-576 Message %1 Description This error occurred because the type of the operand in a qualified expression did not have the same type as the base type of the type mark in the qualified expression. Refer to the VHDL Language Reference Manual, Section 7.3.4, for more information. What Next Check the line number specifed by the error message. Find the qualified expression and change either the type mark or the expression operand so that the type mark and expression operand both have the same base type. Example entity vss576 is end; Architecture a_vss576 of vss576 is signal i: integer := integer'('1'); begin end; Example Message % vhdlan -nc vss576.vhd signal i: integer := integer'('1'); ^ **Error: vhdlan,576 er576.vhd(7): Qualified expression argument can not be interpreted as the given type. "vss576.vhd": errors: 1; warnings: 0. ~S7 assert s = now/ 10 s; -- unit name s collides with the signal name assert b = 5 a; -- unit name a collides with the variable name wait for 10 ii; -- name ii does not denote a unit name end process; end; Example Message % vhdlan -nc code.vhd assert s = now/ 10 s; -- unit name s collides with the signal name **Error: vhdlan,577 code.vhd(20): Name must denote a unit of some physical type. assert b = 5 a; -- unit name a collides with the variable name **Error: vhdlan,577 code.vhd(21): Name must denote a unit of some physical type. wait for 10 ii; -- name ii does not denote a unit name **Error: vhdlan,575 code.vhd(22): Name must denote a unit of some physical type. "code.vhd": errors: 3; warnings: 0. A8~SVSS-577 Message %1 Description This error was generated because the Analyzer could not uniquely identify a name (identifier) as a unit of a physical type (in other words, a physical literal). This error is generated, for example, if you use the same name both for an object and as a physical literal. What Next Either change the name of the object declaration, or change the physical literal to make it unique. If you change the physical literal, then re-analyze each design unit that uses it. If you change the name of the object, then re-analyze the design file that it was declared in. Example % cat code.vhd entity E is type alpha is range 0 to 1000 units a; b = 5 a; c = 5 a; d = 25 a; end units; end e; architecture A of E is signal s : integer := 0; signal ii : integer; begin P : process variable a,b,c : integer; begin S process variable v1: integer; begin P1 (F1(1) => v1); -- Failure_here end process; end; Example Message % vhdlan -nc vss580.vhd P1 (F1(1) => v1); -- Failure_here ^ **Error: vhdlan,580 vss580.vhd(17): Bad formal part - formal is not declared or is not in the correct form. "vss580.vhd": errors: 1; warnings: 0. A8SVSS-580 Message %1 Description This error occured because the formal part in an association list was incorrectly specified. Association lists map formals to actuals in a generic map, port map, or subprogram call. The formal part occurs before the => token. The formal part can consist of either a single formal parameter name, or a function call that is passed one of the formal parameter names. Refer to the VHDL Language Reference Manual, section 4.3.3.2, for more information. What Next Check the line number specifed by the error message. Correct the missing or bad formal part in the association list. Example entity vss580 is end; architecture vss580 of vss580 is procedure P1 (a: in integer) is begin end; File written entity vss580 is end; architecture vss580 of vss580 is procedure P1 (a: in integer) is begin end; function F1 (I1: integer) return integer is begin return 0; end; begin SVSS-701 Message %1 Description This error was generated because multiple choices are used in an element association, and one of them is an others choice. What Next Remove all choices except the others choice from the offending element association. Examples entity E is signal b: BIT_VECTOR (1 to 5) := (1 => '0', 2 | others => '1'); begin end; Example Message % vhdlan -nc code.vhd (1 => '0', 2 | others => '1'); ^ **Error: vhdlan,701 code.vhd(4): OTHERS must be the only choice in an element association. "code.vhd": errors: 1; warnings: 0. X|8TrVSS-702 Message %1 Description This error was generated because an aggregate contains one or more element associations following an 'others' association. What Next Make the 'others' choice the last one in the aggregate. Examples entity E is signal b: BIT_VECTOR (1 to 5) := (1 => '0', others => '1', 2 => '0'); begin end; Example Message % vhdlan -nc code.vhd (1 => '0', others => '1', 2 => '0'); ^ **Error: vhdlan,702 code.vhd(4): OTHERS choice must be in the final element association. "code.vhd": errors: 1; warnings: 0. 6TVSS-703 Message %1 Description This error was generated because you used an 'others' choice in an element association of an array aggregate, and the subtype of the aggregate cannot be determined from the context. What Next Ensure that the 'others' choice used within an array aggregate appears only in a valid context as defined in Section 7.3.2.2 of the VHDL Language Reference Manual. Examples entity E is constant b: BIT_VECTOR := ('0', others => '1'); begin end; Example Message % vhdlan -nc code.vhd constant b: BIT_VECTOR := ('0', others => '1'); ^ **Error: vhdlan,703 code.vhd(3): OTHERS is not legal in this context. "code.vhd": errors: 1; warnings: 0. A8WTVSS-704 Message %1 Description This error was generated because a positional element association follows a named association in an aggregate. What Next Ensure that all positional associations precede named associations in the aggregate. Examples entity E is signal b: BIT_VECTOR (1 to 5) := (1 => '0', '1', others => '0'); begin end; Example Message % vhdlan -nc code.vhd signal b: BIT_VECTOR (1 to 5) := (1 => '0', '1', others => '0'); ^ **Error: vhdlan,704 code.vhd(3): Illegal mixing of named and positional element associations. "code.vhd": errors: 1; warnings: 0. xT(g: for i in 1 to 20 generate P: process type memory is array(integer range <>, integer range <>) of bit; variable v: memory(1 to 32, 1 to 600000); begin wait; end process; end generate; end; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E **Error: vhdlsim,71: System virtual memory limit exceeded (tried to allocate 2400016 bytes) - more virtual memory must be made available. A8xTre declared. - The design does not have a structural recursion. If the design does contain these constructs, find another method to model this piece of the design. If you need more memory: - Re-run the Simulator on a machine with more memory. - Increase the virtual and/or physical memory on the system. (See your systems administrator.) - Kill/quit other process that are consuming systems memory (such as other Simulator sessions). - Break the design into smaller pieces and simulate each piece separately. Finally, this error may also be generated if you have a corrupt intermediate file. If you suspect you have a corrupt intermediate file, re-analyze your design and restart the Simulator. What Next Either reduce the size of the design or obtain more memory, and then re-run the VHDL System Simulator. Example entity E is end; architecture A of E is -- This design has 20 instances each of which declares a variable -- with 1.8 million elements. begin xTVSS-71 Message %1 Description This error was generated when a tool was unable to obtain enough memory from the operating system. This may be because the design is too large for the virtual memory of the system, or because another tool or set of tools is consuming a large portion of the available system memory. Check to see if the VHDL System Simulator is consuming excessive memory, by using operating system commands such as ps -v and pstat -s. If a different tool is consuming the memory, then either kill that process or move to a different machine that has more memory available. If the VHDL System Simulator is using the memory, it is usually because the design is too large to fit into memory. You must either obtain more memory or reduce the size of the design. When reducing the size of the design, make sure that: - There are no very large objects, such as buses that are a million bits wide. - There are no generate statements with huge generate ranges. - No large RAM objects aA8Tr environment to verify you have installed the system. See Chapter 2 "System Configuration" of the VHDL System Simulator Core Programs Manual for more details. 2 Re-analyze all your source files with one set of tools. If the error is the size of a VHDL source file name, reduce the length of the name. If the error is the size of the generated intermediate file, reduce the lengths of the entity name, architecture name, package name and/or the design library names. Examples original .synopsys_vss.setup test > lib1 lib1 : work modified .synopsys_vss.setup test > lib2 lib2 : work example of vhdl source file code.vhd entity E is end E; architecture A of E is begin end A; Example Message % vhdlan -nc -w lib1 code.vhd after modifying lib1 to lib2 in the .synopsys_vss.setup file %vhdlsim -nc lib2.E **Error: vhdlsim,74: Corrupt intermediate file - LIB2.E.sim (library aliasing detected). Te file. * The NFS network caused the corruption. POSSIBLE ENVIRONMENT PROBLEMS The following are possible problems with your environment. - Check to see if your path includes more than one SYNOPSYS VHDL simulator release directory by typing the shell command echo $path. If it does, set your path and the $SYNOPSYS variable only once in either the .login or .cshrc files or in your startup files. - Check to see if your local directory or any directory preceding the SYNOPSYS release directories in $path has symbolic links to vhdlan, vhdlsim or vhdldbx from different releases or platforms. If there are, remove the links or rename the symbolic names. - Check your aliases list to see if you have vhdlan, vhdlsim or vhdldbx as aliases (type the shell command alias). If you find any, discard the alias name by using the shell command unalias [vhdlan | vhdlsim | vhdldbx]. What Next If the error is because of version or machine incompatibility, or library aliasing detection: 1 Check youA8Tng detected": This error was generated because you changed the library mapping in the setup file .synopsys_vss.setup after analyzing files and before simulation. You can change the mapping of any library and any variables in the setup file; however, improper setup of this file can cause the tools to fail. See example for more details. - "source file name too long": "dependent file name too long": "logically dependent file name too long": "file comment too long": You are not likely to get the above error messages. But if you do, check whether any of your VHDL source file names or any entity name, architecture name, or design library name used in the .synopsys_vss.setup file are longer than 1024 characters. - Various other errors may be generated when the intermediate file has not been written properly. These errors may be generated because: * Your machine or server went down in the middle of writing the intermediate files. * You ran out of memory while writing the intermediatTVSS-74 Message %1 Description VHDL analyzer generates intermediate files to store the results of the analysis. This error was generated because vhdlan, vhdlsim, or vhdldbx did not read these files successfully. The corruption of theses files may happen for several reasons. These are: - "written using an old version of the analyzer": You tried to simulate a design using vhdlsim or vhdldbx which has been analyzed by a incompatible version of vhdlan. For example, you used v2.2 of vhdlan and v3.0 of vhdlsim. Similarly, you may have tried to analyze a design and its logically dependent units using different versions of vhdlan. - "written by a different machine": You analyzed your design on one machine and tried to analyze its logically dependent design files on an incompatible machine. Similarly, you analyzed your design on one machine and tried to simulate it or debug it on an incompatible machine. Check the documentation for information on machine compatibility. - "library aliasiJ8 Us -- entity aspect begin C1 : comp generic map(N=>1); end ; Example Message % vhdlan -nc vss770.vhd generic map(N=>1); ^ **Error: vhdlan,770 check.vhd(10): Generic or port map is illegal after an OPEN entity aspect. "vss770.vhd": errors: 1; warnings: 0.  UVSS-770 Message %1 Description This error was generated because you tried to associate generics or ports with the formal ports of the component for which the entity aspect is specified as OPEN. The entity aspect is specified at the time of binding a component with an entity. An OPEN entity aspect is used to defer the identification of the design entity. Refer to Section 5.2.2.1 of the VHDL Language Reference Manual for more information. What Next Check the line number specifed by the error message. Delete the generic or port map aspects specifed in the binding indication after an OPEN entity aspect specification. Example entity vss770 is end vss770; architecture a_vss770 of vss770 is component comp generic ( N : integer); end component; for C1 : comp use open generic map(N=>1); -- this generic aspect is -- illegal after an OPEN X|86UVSS-773 Message %1 Description The VHDL LRM contains a number of rules about how port and generic maps may be written. This error is generated if one of these rules is violated. In particular, section 5.2.1.2 states: Each local port or generic of the component instances to which the enclosing configuration specification applies must be associated as an actual with at least one formal. This means that if you include port or generic declarations in your component declaration, any configuration specification that applies to an instance of that component must use these component ports and generics (also known locals). See below for an example showing each of these VHDL constructs. This rule ensures that all values specified in the generic/port maps of the component instance are passed down to the entity. If you want to specify explicit values in the configuration specification, do not include the generics and/or ports in the component declaration. Put them only in the entity declarati6Uon. What Next Either change the component declaration to remove the local(s), or change the configuration specification to add the local(s); then re-analyze the design. Example entity ANDGATE is generic (tLH: Time := 0 ns; tHL: Time := 0 ns); port (Input: in BIT_VECTOR (1 to 2); Output: out BIT); end; architecture A of ANDGATE is begin -- Not defined. end; entity E is end; architecture A of E is -- This component has 4 locals: tLH, tLH, Input, and Output. -- If an instance of this component is configured using -- a configuration specification, then you must use each -- of these locals as actuals. component ANDGATE generic (tLH: Time := 5 ns; tHL: Time := 5 ns); port (Input: in BIT_VECTOR (1 to 2); Output: out BIT); end component; component ANDGATE_no_generics port (Input: in BIT_VECTOR (1 to 2); Output: out BIT); endX|86U component; signal i1_1, i2_1, o_1: bit; signal i1_2, i2_2, o_2: bit; begin -- Component Instances U1: ANDGATE generic map(10 ns, 20 ns) port map(Input(1) => i1_1, Input(2) => i2_1, Output => o_1); U2: ANDGATE_no_generics port map(Input(1) => i1_2, Input(2) => i2_2, Output => o_2); end; -- Configuration Specification configuration C of E is for A for U1: ANDGATE use entity WORK.ANDGATE(A) generic map (0 ns, 0 ns); -- The above generic map is illegal because the -- actuals (0 ns) do not include the locals (tLH -- and tLH) declared in the component declaration. end for; for U2: ANDGATE_no_generics use entity WORK.ANDGATE(A) generic map (0 ns, 0 ns); -- The above gene6Ujric map is legal because the -- the component does not include a generic -- clause. end for; end for; end C; Example Message % vhdlan -nc code.vhd generic map (0 ns, 0 ns); **Error: vhdlan,773 code.vhd(43): Component local TLH must be associated as an actual with at least one entity formal. generic map (0 ns, 0 ns); **Error: vhdlan,773 code.vhd(43): Component local THL must be associated as an actual with at least one entity formal. "code.vhd": errors: 2; warnings: 0. X|8UVSS-782 Message %1 Description This warning was generated because a component configuration specification was applied to a component that was never instanced in the applicable context (block or architecture). This situation is not an Error (it is legal VHDL), but it is flaged since it may be an inadvertent mismatch. For more information on configuration specification see the LRM section 5.2. What Next Check that the name of the component is the component you want to configure. Check that the configuration specification is in the right context (i.e. in the inner block or architecture in which the instancing is done). Examples entity e is end e; architecture a of e is component c end component; for all : c use open; -- Componenet 'c' is not instanced in the architecture 'a'; -- only in the block b. begin b: block -- the component configuration really belongs in the block, -- sinceU] this is the only place in which 'c' is instanced. begin i : c; end block; end; Example Message % vhdlan -nc err782.vhd for all : c use open; ^ Warning: vhdlan,782 err782.vhd(9): Component is never instanced in the corresponding set of statements. "err782.vhd": errors: 0; warnings: 1. % X|8UVSS-793 Message %1 Description This error was generated when an interface element (Port) of mode OUT or LINKAGE was used to read a value. Typically, an element is read if used on the right-hand side of an assignment or used in port association as an actual for formal port of mode IN/INOUT. If the interface object is of mode OUT, the value of the interface object can be updated. You can read attributes of the interface object, unless the attributes are predefined, but no other reading is allowed. If the interface object is of mode LINKAGE, the value of the interface object can be read or updated, but only by appearing as an actual corresponding to an interface object of mode LINKAGE. No other reading or updating is permitted. (See the LRM Section 4.3.3 for details) What Next Use the interface element as described above. Example -- File: vss-793.vhd entity ctof is port (c : IN integer; x : LINKAGE integer; g : OUT integer); end ctof; architecture firstUu of ctof is begin a: process variable temp1, temp2 : integer; begin wait on c; g <= 2*c + 30; temp1 := g; -- Port of mode OUT can`t be read temp2 := 3*x ; -- Port of mode LINKAGE cannot be read in this way. end process; end first; Example Message % vhdlan -nc vss-793.vhd temp1 := g; ^ **Error: vhdlan,793 vss-793.vhd(14): Ports of mode OUT or LINKAGE can not be read. temp2 := 3*x ; ^ **Error: vhdlan,793 vss-793.vhd(15): Ports of mode OUT or LINKAGE can not be read. "vss-793.vhd": errors: 2; warnings: 0. % Y|8UVSS-805 Message %1 Description VHDL has two assignment operators. The operator ":=" assigns a value to a variable. The operator "<=" assigns a value to a signal. If you use the variable assignment operator to assign a value to a signal, this error message is generated. What Next Verify that the target on the left side of the assignment is correct. If it is, change the operator to the signal assignment operator "<=". Finally, re-analyze the design. Example entity E is end; architecture A of E is signal s: bit; begin P: process begin -- Note: Signal on the left-hand side of the variable assignment s := '1'; wait; end process; end; Example Message % vhdlan -nc code.vhd s := '1'; ^ **Error: vhdlan,805 code.vhd(9): Target must be a variable name or designate an access object. "code.vhd": errors: 1; warnings: 0. !VVSS-806 Message %1 Description This error is generated when a port map in a component instantiation statement associates an actual that is not a signal or a port name with a formal (that is a port name). What Next Double check th component instantiation port map in question. Replace the actual with a name of a signal or a port. The name can be an indexed name or slice name. Example entity e is port (a: out bit); end; architecture a of e is begin end; entity top is end; architecture a of top is component c port (a: out bit); end component; for all:c use entity work.e(a); constant foo: bit := '1'; begin L:c port map(foo); end; Example Message % vhdlan -nc vss-806.vhd L:c port map(foo); ^ **Error: vhdlan,806 error-806.vhd(19): Signal or port name expected as actual in association element. "error-806.vhd": errors: 1; warnings: 0. Y|8PVVSS-807 Message %1 Description This error was generated because the actual in the port association did not match the restriction implicated by the direction of the formal port. IEEE Std 1076-1987 VHDL LRM Section 1.1.1.2 specifies that: For a formal port of mode out, the associated actual may only be a port of mode out or inout. For more information on restrictions upon the actual that is a port, see LRM Section 1.1.1.2. What Next Check that the mode of the actual that is a port complies with the restrictions specified in the LRM, modify your code, and then re-analyze your VHDL file(s). Example -- File: vss-807a.vhd entity E is port (port1 : BUFFER bit); end; architecture A of E is component C port (c_port1 : OUT Bit); end component; begin U1: C port map (c_port1 => port1); end; Example Message % vhdlan -nc vss-807a.vhd port map (c_port1 => port1); ^ **Error: vhdlan,807 vss-807a.vhd(11): Actual signal PVUis not appropriate for port of mode OUT. "vss-807a.vhd": errors: 1; warnings: 0. % Y|8|VVSS-808 Message %1 Description This error was generated because the actual in the port association did not match the restriction implicated by the direction of the formal port. IEEE Std 1076-1987 VHDL LRM Section 1.1.1.2 specifies that: For a formal port of mode inout, the associated actual may only be a port of mode inout. For more information on restrictions upon the actual that is itself a port, see LRM Section 1.1.1.2. What Next Check that the mode of the actual that is a port complies with the restrictions specified in the LRM, modify your code, and then re-analyze your VHDL file(s). Example -- File: vss-808a.vhd entity E is port (port1 : BUFFER bit); end; architecture A of E is component C port (c_port1 : INOUT Bit); end component; begin U1: C port map (c_port1 => port1); end; Example Message % vhdlan -nc vss-808a.vhd port map (c_port1 => port1); ^ **Error: vhdlan,808 vss-808a.vhd(11): Actual sig|V[nal is not appropriate for port of mode INOUT. "vss-808a.vhd": errors: 1; warnings: 0. % Y|8VVSS-809 Message %1 Description This error was generated because the actual in the port association did not match the restriction implicated by the direction of the formal port. IEEE Std 1076-1987 VHDL LRM Section 1.1.1.2 specifies that: For a formal port of mode buffer, the associated actual may only be a port of mode buffer. For more information on restrictions upon the actual that is itself a port, see LRM Section 1.1.1.2 What Next Check that the mode of the actual that is a port complies with the restrictions specified in the LRM, modify your code, and then re-analyze your VHDL file(s). Example -- File: vss-809a.vhd entity E is port (port1 : INOUT bit); end; architecture A of E is component C port (c_port1 : BUFFER Bit); end component; begin U1: C port map (c_port1 => port1); end; Example Message % vhdlan -nc vss-809a.vhd port map (c_port1 => port1); ^ **Error: vhdlan,809 vss-809a.vhd(11): Actual siV]gnal is not appropriate for port of mode BUFFER. "vss-809a.vhd": errors: 1; warnings: 0. % Y|8VVSS-80 Message %1 Description This error was generated because a time unit specified in the VHDL file for the design is smaller than the time unit used for running the model. Time units are associated with the objects of type TIME. You specify the time base for the execution of the model using the TIMEBASE variable in .synopsys_vss.setup file or by the -t command line option to vhdlsim or vhdldbx. It is an error if a unit of type TIME appears anywhere in the design and a larger unit is used to execute the model. See Section 3.1.3.1 of the VHDL Language Reference Manual for more information. What Next There are two ways to eliminate this problem: a) Check the hierarchy of the design files defining the model for any reference to the unit of time. Check the unit of time you have specified for running the model. If the unit of time specified in the design files is smaller than this time base, change it to a smaller time unit. Re-analyze all the files which depend on it. b)V Choose a time base for running this model that is smaller than (or equal to) the smallest time base specified in the design file. Example library IEEE; use IEEE.std_logic_1164.all; entity vss80 is end vss80; architecture structural of vss80 is signal x0: std_logic; begin x0 <= '1' after 10 ns; -- time base used here is ns. -- any time base greater than ns used for simulation -- of this architecture (ex - ms) will result in this -- error end structural; Example Message % vhdlan -nc vss80.vhd % vhdlsim -nc -t ms vss80 **Error: vhdlsim,80: Time literal unit smaller than resolution limit in DEFAULT.VSS80__STRUCTURAL.sim: 10 NS. Y|8WVSS-811 Message %1 Description VHDL has a number of rules regarding the class of parameters to subprograms. In particular, section 2.1.1 of the LRM states: In a subprogram call, the actual designator associated with a formal parameter of class signal must be a signal. The actual designator associated with a formal of class variable must be a variable. The actual designator associated with a formal of class constant must be an expression. If a non-variable is passed as an actual to a variable parameter, the above error is generated. What Next Verify that the actual passed to the subprogram is correct. If it is, change the class of the parameter to the same class as the actual and re-analyze the design. Example entity E is end; architecture A of E is signal s: bit; begin P: process procedure PR(variable p: bit) is begin -- No body. end PR; begin PR(s); end procWess; end; Example Message % vhdlan -nc code.vhd PR(s); ^ **Error: vhdlan,811 code.vhd(11): Actual must be a variable or designate an access object. "code.vhd": errors: 1; warnings: 0. Y|84WVSS-815 Message %1 Description This error was generated because a function attempts to modify an object (signal or a variable) that was not declared in its declarative region. According to Section 2.2 of the VHDL Language Reference Manual, "If a function subprogram contains a reference to a signal or variable object, then that object must be declared within the declarative region associated with the function." What Next Remove the offending statements and recode the function. Examples -- -- vss-815.vhd -- entity e is end; Architecture A of e is signal s : bit; function foo return bit is begin return s; -- Illegal reference end; begin p1: process variable v: bit; function bar return bit is begin return v; -- Illegal reference end; begin end process; end; In this example, function foo refers to signal s, and function bar refers to variable v, neither o4Wf which is declared in the declarative region of the functions. Example Message %vhdlan vss-815.vhd return s; ^ **Error: vhdlan,815 vss-815.vhd(9): Illegal reference to signal or variable object in a function. return v; ^ **Error: vhdlan,815 vss-815.vhd(16): Illegal reference to signal or variable object in a function. Y|8 lW VSS-81 Message %1 Description This error was generated at elaboration time because the value of an integer time literal could not be represented in the time base used by the simulation. Simulation time is represented as an integer value and a time base for scaling. Depending on the options set, the time value is represented by either a 32-bit integer or 64-bit integer. The time value is scaled by the specified time base, which defaults to femto-seconds, to give the absolute simulation time. If the simulation time is too large to be represented by either 32 or 64 bits, an overflow occurs. For example, with a default base of femto-seconds, 1 nano-second would be represented as 1,000,000 femto-seconds. What Next You can fix this problem by either increasing the time base (resolution unit) or using 64-bit simulation time. You can increase the time base either with the TIMEBASE variable in the .synopsys_vss.setup file, or via the command line `-t' option. For example, if the smallest prop lW  agation delay in your design is 100ps, you can override the default resolution of femto-seconds by adding the option `-t ps' in the vhdlsim command line to allow for greater absolute simulation times. If you still need a greater dynamic range of simulation times, use 64-bit simulation time by setting the USE_LONGTIME variable in the .synopsys_vss.setup file to TRUE. If you change the time base, you need to re-run only vhdlsim. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss81 is port (out_signal: out MVL7); end vss81; architecture structural of vss81 is begin P: process begin out_signal <= '0' after 8 us; -- The above line tries to schedule a value for out_signal at time -- 8 micro-seconds. However, 8 micro-seconds can not be represented -- in the default time base of femto-seconds (8,000,000,000 fs). -- Running with the option "-t ns" will set the time base to -- nano-seconds and allow the simulation time Y|8 lW of 8 us to fit into -- a 32-bit integer. wait; end process; end structural; Example Message % vhdlan -nc vss81.vhd % vhdlsim -nc vss81 **Error: vhdlsim,81: Integer time literal overflow in DEFAULT.VSS81__STRUCTURAL.sim: can not represent 8 US. Running with the "-t ns" option eliminates the error. % vhdlsim -nc -t ns vss81 # run (vhdlsim): Simulation complete, time is 8000 NS. # quit  W VSS-82 Message %1 Description This error was generated at elaboration time because the value of an integer time literal was smaller than the time base used by the simulation. For example, a time literal of 1 pico-second can not be represented if the time base is nano-seconds, since 1 ps is less than 1 ns. What Next Decrease the time base with the TIMEBASE variable in .synopsys_vss.setup or via the command line with the `-t' option. The default time base is femto-seconds. If you change the time base, you need to re-run vhdlsim. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss82 is port (out_signal: out MVL7); end vss82; architecture structural of vss82 is begin P: process begin out_signal <= '0' after 5.1 ps; -- The line above tries to schedule a value for out_signal at time -- 5.1 pico-seconds. However, if you are using a time base of -- nano-seconds, 5.1 ps cannot be represented and this line will -- result in Y|8 W an error. Running with the option "-t fs" will -- set the time base to femto-seconds and allow the simulation -- time of 5.1 ps to be represented. wait; end process; end structural; Example Message % vhdlan -nc vss82.vhd % vhdlsim -nc -t ns vss82 **Error: vhdlsim,82: Time literal unit smaller than resolution limit in DEFAULT.VSS82__STRUCTURAL.sim: 5.1 PS. Running with the "-t fs" option eliminates the error. % vhdlsim -nc -t fs vss82 # run (vhdlsim): Simulation complete, time is 5100 FS. # quit WVSS-86 Message %1 Description In the case of a signal with multiple sources, a resolution function is executed to compute a single value for the signal from the values of its sources. This error was generated because a scalar signal had more than one source providing values, and no function was defined to compute the signal's single value. This error may also be generated for a non-resolved signal of composite type whose sub-elements have more than one source. The subelements could be scalar or part of an interval range. Section 4.3.1.2 of the VHDL LRM states: It is an error if, after the elaboration of a description, a signal has multiples sources and it is not a resolved signal. A resolved signal is a signal that has the name of a resolution function appearing either in its declaration, or in the declaration of the subtype used to declare the signal. The VHDL LRM section 4.3.1.2 defines the syntax of a resolved signal declaration. A source is either a driver (hoY|8Wlder of the signal transactions), or an out, inout, buffer, or linkage port of a component instance with which the signal is associated. What Next Either associate a resolution function with the scalar signal or the subelements of the composite signal, or remove the extra source(s). Examples entity E is end E; architecture A of E is signal S1, S2, S3: bit; signal V1: bit_vector(0 to 4); begin L0: S1 <= S2; L1: V1(0) <= S1; L2: V1(0 to 1) <= S1 & S2; P0: process begin S1 <= S3; wait; end process; end A; Example Message % vhdlan -nc code.vhd % vhdlsim -nc E **Error: vhdlsim,86: Signal (/E/V1(0)) is not a resolved signal and has more than 1 source: Driver from process /E/L2 Driver from process /E/L1 **Error: vhdlsim,86: Signal (/E/S1) is not a resolved signal and has more than 1 source: Driver from process /E/P0 Driver from process /WE/L0 Y|8 XVSS-871 Message %1 Description This error occured because for or while generate statements were nested more than 127 levels deep. What Next Check the line number specifed by the error message. Try to simplify the design so that it does not require such deeply nested generate statements. Example entity vss871 is port(clk: bit); end; Architecture vss871 of vss871 is component foo port(p1: bit); end component; begin L000: for i000 in 1 to 1 generate L001: for i001 in 1 to 1 generate L002: for i002 in 1 to 1 generate L003: for i003 in 1 to 1 generate L004: for i004 in 1 to 1 generate ... L127: for i127 in 1 to 1 generate L0: foo port map(clk); end generate; end generate; end generate; end generate; end generate; ... end generate; end; Example Message % vhdlan -nc vss871.vhd L127: X for i127 in 1 to 1 generate ^ **Error: vhdlan,871 vss871.vhd(139): Analyzer limit exceeded: 127 levels of for-generate statement nesting. "vss871.vhd": errors: 1; warnings: 0. Y|8EXVSS-876 Message %1 Description This error was generated because there is a process that contains no wait statements or sensitivity lists. Once this process starts to run, it will never end and no other processes will have a chance to run. What Next Add either a wait statement or a sensitivity list to the process. If the process is meant as an initialization routine only, it may be missing a `wait;' statement at the end of the process. The VHDL Language Reference Manual, section 9.2, states: The execution of a process statement consists of the repetitive execution of its sequence of statements. After the last statement in the sequence of statements of a process statement is executed, execution will immediately continue with the first statement in the sequence of statements. Thus, it is possible to write infinite loops without really being aware of it. This error message was created to prevent these situations. Example library SYNOPSYS; use SYNOPSYS.types.all; entity vss876 is EX port (out_signal: out MVL7); end vss876; architecture structural of vss876 is begin P: process begin out_signal <= '0' after 8 us; -- Adding a 'wait;' statement will remove the error in this case. end process; end structural; Example Message % vhdlan -nc vss876.vhd P: process begin Warning: vhdlan,876 vss876.vhd(10): This process statement will never execute a wait statement (no other processes will ever get a chance to run). "vss876.vhd": errors: 0; warnings: 1. Y|8pXVSS-87 Message %1 Description This error was generated because a process drove part, but not all, of a resolved composite type signal. The following rule stated in the VHDL LRM section 4.3.1.2 has been violated: If a subelement of a resolved signal of composite type has a driver in a given process, then every scalar subelement of that signal must have a driver in the same process, and the collection of all of those drivers taken together constitute one source of the signal. What Next Either associate drivers to all sub-elements of a resolved signal of composite type, or change the subtype of the signal to cover only the driven sub-elements. Examples entity E is end; architecture A of E is subtype st1 is bit_vector(1 to 5); type t1 is array(natural range <>) of st1; function bv_res(bvv: t1) return st1 is begin return b"00000"; end; signal S: bv_res st1; begin -- subepXXlements 3 to 5 do not have drivers in L0 L0: S(1 to 2) <= "11"; P0: process begin -- subelement 5 does not have a driver in process P0 S(1 to 4) <= "1111"; wait; end process; end; Example Message % vhdlan -nc code.vhd %vhdlsim -nc E **Error: vhdlsim,87: The (piece of the) signal /E/S which is resolved by function BV_RES is not completely driven by process /E/L0. **Error: vhdlsim,87: The (piece of the) signal /E/S which is resolved by function BV_RES is not completely driven by process /E/P0. Y|8XVSS-89 Message %1 Description This error occurred because of a reference to a design unit that has changed more recently that the referencing design unit. Before analyzing a design unit, you must first analyze all design units it references. For example, you have two design units, A and B, and design unit B depends on design unit A. If you analyze A, then B, then modify and reanalyze A, B is now out-of-date with respect to A. This error is generated if you now reference B, either in a subsequent analysis of a third design unit or during simulation. What Next Make sure that all design units that are dependent on the changed design unit named in the error message are reanalyzed. Example -- File : vss-89a.vhd package P is type byte is array (7 downto 0) of bit; end; -- File : vss-89b.vhd use work.P.all; entity E is end; architecture A of E is begin P: process variable v : byte := X"10"; begin wait; end process; end; Example Message % vhdlan -nc vsXs-89a.vhd vss-89b.vhd % vi vss-89a.vhd # Modify contents of vss-89a.vhd % vhdlan -nc vss-89a.vhd % vhdlsim -nc e **Error: vhdlsim,89: Intermediate file "DEFAULT.P.sim" has changed. Re-analyze files that depend on this file. % Y|8XVSS-964 Message %1 Description This error was generated because an unexpected character was discovered in the VHDL source file. VHDL specifies that various items, such as literals, consist of a series of specific characters. If, while reading one of these items, a character that does not fall into this set is encountered, this error message is generated. This error is generated if the source contains any non-printing characters such as control characters or if it contains a malformed literal. In particular (See LRM Section 13.1 for details): String Literals are formed by a sequence of graphic characters enclosed between two quotation characters. A graphic character is an upper or lower case letter, a digit, or a "special" character. For example, "Hello World", or "Embedded Single Quote "" <- Here". Bit String Literals are formed by a base specifier followed by a sequence of digits and underscores enclosed between two quotation characters. The base specifier is either a B, O or X.X For example, X"FFF", O"777", or B"0000_1111". Based Literals are formed by a base, a sharp (#), a based_integer, an optional period followed by a based_integer, and an optional sharp followed by an exponent. For example, 16#FF.F#E+2, or 2#1110_0000#. Decimal Literals are formed by an integer, followed by an optional period and integer, followed by an optional exponent. For example: 3.14159_26, 123_456, or 1.23E-12. Exponents are formed by an E, an optional sign [+ or -] and an integer. What Next Examine the line/literal indicated by the error message. Remove any non-printing characters, or change the form of the literals to correspond to the above guidelines. Re-analyze the design. Examples -- Example 1: entity E is end; architecture A of E is begin P: process begin ^Xwait; -- Note: Invalid control character (^X) end process; end; -- Example 2: entity E is end; architecture A of E is signal s: bit_veY|8Xctor(0 to 7); begin P: process begin assert s = x"F?"; -- Note: Invalid ? in bit string literal end process; end; Example Message % vhdlan -nc 964a.vhd wait; -- Note: Invalid control character (^X) ^ Note: The character may not be visible in the error message **Error: vhdlan,964 964a.vhd(10): Invalid character in input stream. "964a.vhd": errors: 1; warnings: 0. % vhdlan -nc 964b.vhd assert s = x"F?"; -- Note: Invalid ? in bit string literal ^ **Error: vhdlan,964 964b.vhd(11): Invalid character in bit string literal. "964b.vhd": errors: 1; warnings: 0. $YVSS-98 Message %1 Description This error message was issued because an assertion violation occurred or because you pressed interrupt (^C) while the simulator was elaborating a design. When elaborating the declarative part of a design unit, initializing each declarative item may require the execution of VHDL statements (i.e. calling a function). These statements are executed at elaboration time. Any assert statements used are therefore evaluated and potentially violated at elaboration time. This message is also generated if you press interrupt (^C) before the initial simulator prompt is issued. (i.e. before static elaboration is complete). What Next Check to see which assert is failing and why. Correct the code so that it is not violated. Recompile the design and resimulate. Example package DRAM is constant speed : time := 80 ns; end DRAM; use WORK.DRAM.speed; entity CPU is end CPU; architecture cpu_body of CPU is function max_frq(mem_access_time : time) return integerJ8$Y is constant clock_period : time := 100 ns; constant critical_path : time := 30 ns; begin -- The following assert is violated during elaboration. assert (clock_period - critical_path) >= mem_access_time report "RAM is too slow." return 1 ns / clock_period; end max_frq; constant clock_rate : integer := max_frq(work.DRAM.speed); begin end cpu_body; Example Message % vhdlsim -nc cpu (vhdlsim): Assertion error or keyboard interrupt during elaboration in: /CPU. Assertion ERROR at 0 NS in design unit CPU_BODY from process STATIC ELABORATION: "RAM is too slow." # YY(k). Here, k is a deferred constant whose value is not known until the design is elaborated. The analyzer has no way of knowing what bar(k) really means and whether it is a valid name. Example Message %vhdlan vss-996.vhd z := foo(bar(1)=>'0',bar(k)=>'1'); ^ **Error: vhdlan,996 vss-996.vhd(22): Formal name must be a locally static name. J8YYVSS-996 Message %1 Description This error was generated because named association is used in a function or procedure call, and the name of the formal cannot be identified during analysis. "Locally static" means that all the characteristics are known at analysis time. What Next Remove the offending statements and recode the function. Examples -- -- vss-996.vhd -- package p is constant k : integer; end p; package body p is constant k : integer := 2; end p; entity e is end; use work.p.all; Architecture A of e is function foo (bar : bit_vector(1 to 2)) return bit is begin return bar(1) and bar(2); end; begin p1: process variable z : bit; begin z := foo(bar(1)=>'0',bar(k)=>'1'); -- offending statement -- This can be fixed as follows -- z := foo(bar(1)=>'0',bar(2)=>'1'); end process; end; In this example, the call to function foo uses named association and refers to the formal bar Y!VSS-998 Message %1 Description This error was generated because a type conversion function is used in associating a formal paramater of class signal with an actual. What Next Remove the offending statements and recode the function. Examples -- -- vss-998.vhd -- entity e is end; Architecture A of e is signal s : bit; signal v : integer; procedure foo (signal x :out integer) is begin x <= 1; end; function conv(x : integer) return bit is begin if x = 1 then return '1'; else return '0'; end if; end; begin p0: process (v) begin foo(conv(x)=>s); -- conv(x) is illegal end process; end; In this example, the call to function foo uses named association and uses a type conversion function conv to convert the type of the formal from integer to bit. Example Message %vhdlan vss-996.vhd foo(conv(x)=>s); ^ **Error: vhdlan,98!Y B98 vss-998.vhd(23): Type conversion function is illegal here. "]K Opens the constraint windows for the selected elaborated implementation.28#]$Synthesis / Edit Constraints command$] Imports the post-place-and-route timing in Standard Delay Format (SDF) from ASIC Master, Actels place-and-route tool, when targeting any Actels ProASIC 500K devices. Also displays the timing in the constraint tables. There are two ways to open the Add SDF Sources dialog box to locate the SDF file. You can either select Synthesis>Back Annotate Chip from the Synthesis menu when an optimized chip is selected or right-click an optimized chip and select Back Annotate Chip. The information is then displayed as the Actual Delay in the appropriate constraint tables. The corresponding shell command for this feature is chip_read_sdf. Please refer to its man page for syntax and usage information.v8%Synthesis / Export Netlist command Export Netlist button Opens the Export Netlist dialog box and exports the selected optimized design for place-and-route. There are two ways to export a netlist. You can either select Synthesis>Export Netlist from the Synthesis menu or click the Export Netlist tool-bar icon. The netlists are automatically formatted into Electronic Data Interchange Format (EDIF) or Xilinx Netlist Format (XNF). You can specify the export design directory. Individual files names correspond to the source design names. They use the same name as the top-level entity or module. You can export Verilog or VHDL netlists for functional simulation along with the design netlist. You can pass timing constraints to the place-and-route tools by checking the Export Timing Specifications box. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express can also export Synopsys standard design databases in .db format, allowing projects created in FPGA Compiler IIFPGA Compiler I&w'ol sharing the operators in the module. When set to Off, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express implements each operator using a separate hardware resource and selects the best implementation of each of these resources. When set to On, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express determines which operators can be implemented sharing the same hardware resource in order to improve the area and speed of your design. It also selects the best implementation of every hardware resource it uses. Optimize for Speed or Area Use this setting to control whether you want to optimize for faster speed or smaller area. The default is to optimize for speed Effort Use this setting to control whether the mapping effort for this design is high or low. This option affects timing optimization most with little influence on area. Low effort takes the least time to compile. Use low if you are running a test to check the logic. Low is not recommended if the desigv8'&(n must meet area or timing goals. High effort takes longer to compile but should produce better designs. The mapping process proceeds until it has tried all strategies. Duplicate Register Merge Removes duplicate cells. Values include Inherit, Enable, and Disable. Location The Location column, which is available only for Altera APEX20K/E devices, allows users to define the location of the logic which is contained by that module and its submodules. Note that FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express does not check the validity of the location values defined by the user. Logic to Memory Mapping Some FPGA technologies have dedicated resources for memory that can also be used for logic. Use the Logic to Memory Mapping setting to control the memory mapping option for the subentities/submodules in the design hierarchy. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express checks to see if the chosen subentity/module meets the requirements of the targeted te(' chnology for memory mapping. If the requirements are met, the software presents you with two options: Default: Disables logic to memory mapping User Defined: Allows you to specify an option name for the target technology The option name must be a valid memory mapping option for the target technology. If the option name is invalid, an error message and a list of valid memory options are displayed. This feature is currently supported for Altera FLEX10K devices only. The option name is Use EAB. See also Editing Constraint Table Entries. VU8)Dentation status icons *y +es on the setting of the entity/module in which that entity/module is instantiated. Inherit : All the instances of that entity/module take on the setting of the entity/module in which that entity/module is instantiated. ]8+y *Dont Touch FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express allows you to set a dont touch attribute on a design/entity/module and also on cells and instances. Use this setting to control whether or not a portion of your design is optimized. When unoptimized, the software effectively treats a design as a black-box. This feature applies only when the design hierarchy is preserved. If the hierarchy is not preserved, then the dont touch setting is ignored. By default, the dont touch attribute is set to FALSE. The available options are: True: Enables Dont Touch on that entity/module/instance. All the lower entities/modules/instances inherit this setting. False: Disables Dont Touch on that entity/module/instance. All the lower entities/modules/instances inherit this setting. True : Enables Dont Touch on all the instances of that entity/module. False : Disables Dont Touch on all the instances of that entity/module. Inherit: Tak,iZLogic to Memory Mapping Some FPGA technologies have dedicated resources for memory that can also be used for logic. Use the Logic to Memory Mapping setting to control the memory mapping option for the subentities/submodules in the design hierarchy. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express checks to see if the chosen subentity/module meets the requirements of the targeted technology for memory mapping. If the requirements are met, the software presents you with two options: Default: Disables logic to memory mapping User Defined: Allows you to specify an option name for the target technology The option name must be a valid memory mapping option for the target technology. If the option name is invalid, an error message and a list of valid memory options are displayed. This feature is currently supported for Altera FLEX10K devices only. The option name is Use EAB. a8Logic to Memory Mapping. Tiler IIFPGA Compiler II Altera EditionFPGA Express, see the Tutorial. a8/cZ0rvidual register to edit its maximum fanout. Registers constraints only apply to Actel ProASIC 500K, Altera APEX20K, Lucent ORCA3, and Xilinx XC4000, Spartan, and Virtex devices only. Note that the default maximum fanout can be changed in the Options dialog box of the Synthesis menu. See Optimization Options for details. See also Editing Constraint Table Entries.0cZ/Registers Constraint Entry Use the Registers constraint table to specify maximum fanout for registers in the design. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express displays the constraint tables when you right click on an elaborated implementation and select Edit Constraints. For optimized implementations, the Registers constraint table displays the actual fanout of individual registers in the design. See Registers Constraint Table After Optimization. The Registers constraint table has these columns: Est. Fanout This is the estimated fanout of the selected register. Max Fanout The maximum fanout is None by default. To change it for a particular register, click the Max Fanout cell of the default entry, click the expand arrow that appears in the cell, and then select Define. This displays the Define Max Fanout dialog box where you can enter the new default maximum fanout. Once the default maximum fanout has been changed you can select Define for each indi=81XZUse the Registers Constraint table to enter constraints for registers. To access the table, right click on an elaborated implementation, select Edit Constraints and then the Registers tab. For more information, see Registers Constraint Entry. To see the results of optimization, right click the elaborated implementation, select View Results and then the Registers tab. See Registers Constraint Table After Optimization. 2pZRegisters Constraint Table383ZFor optimized implementations, the Registers constraint table shows the actual fanout instead of the estimated fanout: Actual Fanout This column displays the actual fanout of each register in the design hierarchy.4Z-Registers Constraint Table after Optimization_85/Preserve Hierarchy Controls whether the modules boundary is preserved or eliminated during optimization. When set to Preserve, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express retains the boundary and optimizes the module logic independently of that of the rest of the design. The module remains a module in the optimized implementation. When set to Eliminate, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express eliminates the boundary between the module and its container during optimization. FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express optimizes the logic of this module with the logic of the rest of the modules container. In general, eliminating hierarchy yields the best quality of results. However, preserving hierarchy reduces compilation time. kPreserve HierarchyZ87:ZFSM State Assignment FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express supports these types of FSM state assignment: Binary In general, 2n = Number of FSM States where n is the number of bits required to implement a binary FSM. An FSM with four states can therefore be implemented using two bits. The possible states are 00, 01, 10, and 11. One Hot In general, a one-hot FSM requires one bit per state. For example, a one-hot FSM with four states can be implemented with 0001, 0010, 0100, and 1000. Since only one bit is hot at any given time decoding is easier (less delay) but more registers are needed (more area). Zero One Hot Similar to one-hot, a zero-one-hot FSM requires one bit per state. The only difference is that the reset state is generally represented by all 0s. For example, a zero-one-hot FSM with four states can be implemented with 0000, 0001, 0010, and 0100.80 #f your vendor-specific questions. |89[Enable Verilog Preprocessor:[iVerilog Preprocessor constructs such as 'ifdef, 'else, 'endif are disabled by default. To enable the Verilog Preprocessor for subsequent HDL analyses of Verilog files, open the Project Options dialog box and check the Enable Verilog Preprocessor box. Note: You must reanalyze any previously analyzed files. Otherwise changes do not affect the synthesized RTL.ۺ8>; GHProgram BasicsG >< K]Using FPGA Compiler II Altera Edition#\ۺ8>= NyResponding to Error Messages$\>> sLDesigning for Synthesis%\ۺ8>? PQTutorial&\>@ Y[FPGA Scripting Tool'\ۺ8>A Z{Schematic Viewer (Vista)(\>B abGlossary)\ۺ8>C DInclude file: support.CNT (WinHelp Only)support.CNT]>D hCInclude file: appnotes.cnt (WinHelp Only)appnotes.cnt+\ۺ8>E]_]_ LtIntroductionWelcome_to_FPGA_Compiler_II_Altera_Edition_,\.>F0\0\ uGBenefits of Using FPGA Compiler II Altera EditionBenefits_of_Using_FPGA_Compiler_II_and_FPGA_Express/\/ۺ8>G3\3\ F;Using_FPGA_Express_in_Your_Design_Flow2\0>H6\6\ ;vLaunching the ProgramLaunching_the_Program5\ۺ8>I9\9\ vJFinding Help and InformationFinding_Help_and_Information8\>J<\<\ IKTips on Using FPGA Compiler II Altera EditionTips_on_Using_FPGA_Express;\Jۺ8>K?\?\ J<GlossaryGlossary>\>LB\B\ >MHDL Coding for FPGA SynthesisHDL_Coding_for_FPGA_SynthesisA\ۺ8>ME\E\ LNGeneral Coding Styles for SynthesisGeneral_Coding_Styles_for_SynthesisD\>NH\H\ M=Partitioning for SynthesisPartitioning_for_SynthesisG\ۺ8>OL\L\ yPError MessagesError_MessagesJ\>PN\N\ O?Viewing Errors and WarningsViewing_Errors_and_WarningsM\ۺ8>QQ\Q\ ?RTutorialTutorial_topicP\>RT\T\ QSSetting Up a ProjectSetting_Up_a_ProjectS\ۺ8>SW\W\ RTSynthesizing the DesignSynthesizing_the_DesignV\>TZ\Z\ SUEntering Design Constraints and ControlsEntering_Design_Constraints_and_ControlsY\ۺ8>U]\]\ TVOptimizing a Design ImplementationOptimizing_a_Design_Implementation\\>V`\`\ UWAnalyzing TimingAnalyzing_Timing_\ۺ8>Wc\c\ VzViewing SchematicsViewing_Schematicsb\>Xg\g\ zYRunning the FPGA Scripting ToolRunning_the_FPGA_Scripting_Toole\ۺ8>Yi\i\ X@SummarySummaryh\>Zl\l\ ^AFST Man PagesFST_Man_Pagesk\ۺ8>[o\o\ @\Introduction to FPGA Scripting Tool (FST)Introduction_to_FSTn\>\r\r\ [^Invoking FSTInvoking_FSTq\ۺ8>] <iDesign Flowst\>^v\v\ \ZFST Command OverviewFST_Command_Overviewu\ۺ8>_y\y\ |`Using the Vista Schematic WindowUsing_the_Vista_Schematic_Windowx\>`|\|\ _aViewing Unoptimized SchematicsViewing_Unoptimized_Schematics{\ۺ8>a\\ `BViewing Optimized SchematicsViewing_Optimized_Schematics~\>b\\ BcAnalysis TerminologyAnalysis_Terminology\ۺ8>c\\ bdGlobal Buffer TerminologyGlobal_Buffer_Terminology\>d\\ ceGlobal Set and Reset TerminologyGlobal_Set_and_Reset_Terminology\ۺ8>e\\ dfImplementation TerminologyImplementation_Terminology\>f\\ egModule and Hierarchy Optimization TerminologyModule_and_Hierarchy_Optimization\ۺ8>g\\ f}Port and Pad TerminologyPort_and_Pad_Terminology\>h\\ }DTiming TerminologyTiming_Terminology\ۺ8>i\\ ]wDesign Flow OverviewDesign_Flow_Overview\>j\\ klPerformance (Constraint-Driven) Design FlowPerformance_Flow\ۺ8>k\\ xjPushbutton Design FlowPushbutton_Flow\>l\\ jmHierarchical (Multiple Device )Design FlowMultiple_Device_Design_Flow\ۺ8>m\\ lnDesign Flow IterationDesign_Iteration\>n moSpecifying Timing Requirements\ۺ8>o\\ npHow_to_Use_FPGA_Express_in_Timing_Analysis\>p\\ oqHow to Specify Timing ConstraintsHow_to_specify_timing_constraints\ۺ8>q\\ prTiming SubpathsTiming_Subpaths\>r qsTargeting Specific Technologies\ۺ8>s\\ r>Supported ArchitecturesSupported_Architectures\>tw^w^ EuWhat is FPGA Compiler II Altera EditionWhat_is_FPGA_Express_u^# ۺ8>u\\ tFFPGA Compiler II Altera EditionFPGA_Compiler_II\/>v\\ HIStarting Work in FPGA Compiler II Altera EditionHIDR_MAINFRAME\Hۺ8>w\\ ixFPGA Compiler II / FPGA Express FunctionsFPGA_Express_Functions\>x\\ wkFPGA Compiler II / FPGA Express Design FlowsFPGA_Express_Design_Flows\ۺ8>y\\ =OOutput Window_1Output_Window_Defined\>z\\ WXGenerating Netlists and ReportsGenerating_Output\ۺ8>{\\ A|Schematic ViewerHIDD_DPMCTRL_SCHEMCTL\>|\\ {_Schematic Viewer FeaturesSchematic_Viewer_Features\ۺ8>}\\ ghProject Management TerminologyProject_Management\r~Using LPMs Library of Parameterized Macros (LPMs) can be either inferred or instantiated. You can control LPM inference in the LPM Options dialog box. For Altera MAX devices, LPMs are always inferred for arithmetic operators. For Altera APEX and FLEX devices, LPMs are inferred only for multipliers. Other arithmetic operators are implemented using Altera-specific primitives. For information about instantiating LPMs in HDL, refer to the application note "Using Altera MegaWizard Components in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. For a list of Altera MAX+PLUS II software megafunctions and LPMs, see Megafunctions/LPM. 8 $ $ $3y/u5{9 $oNiJYf_j $RL{HN $B<,2 $& " $ $    $2 . J N $c _ f j $ {   $    $  |  $v p l r $e _ O. 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Z80 Finding Help and Information For information about procedures and dialog boxes in FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, see this online help system and the FPGA Compiler II / FPGA Express Getting Started manual. Online Help System The online help system is the most complete source of information about FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. You can find the answer to almost any question about FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express using the online help system and documentation. Quick Tour Before you begin to use FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, step through the online Quick Tour (from the Help menu) and refer to Using FPGA Compiler II Altera FPGA Express in Your Design Flow  to become familiar with the design flow. The Quick Tour will answer many of your initial questions about FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. Sections can be replayed  mle; it can push the limits of minimum area or maximum speed, or it can be driven by a minimum design cycle. P8U^Welcome to FPGA Express! This introductory chapter of your online manual contains the following information: What is FPGA Express? FPGA Express Benefits of Using FPGA Express Using FPGA Express in Your Design Flow For information about program basics, see these topics: Launching the Program Starting Work in FPGA Express Finding Help and Information Tips on Using FPGA Express Glossary !^Welcome to FPGA Compiler II Altera Edition! This introductory chapter of your online manual contains the following information: What is FPGA Compiler II Altera Edition? FPGA Compiler II Altera EditionI Benefits of Using FPGA Compiler II Altera Edition Using FPGA Compiler II Altera Edition  For information about program basics, see these topics: Launching the Program Starting Work in FPGA Compiler II Altera Edition Finding Help and Information Tips on Using FPGA Compiler II Altera Edition Glossary k8 Benefits of Using FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express Adding Control to the Design Process Using FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express, you can produce the results you want without multiple design iterations. Because you enter the target performance in advance with design-specific constraints, you spend little or no time in iteration cycles. System clock speed, port delay, and path delay are some of the constraints you can specify. Migrating to HDL Design Methodology If you are migrating from a schematic-based to an HDL-based design methodology, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express adds HDL logic synthesis and optimization to your current FPGA design environment. You can completely define an FPGA design with HDL source code, or use a mixture of schematics and HDL source code to enter a design into FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express. Using an HDL-based design methodology`ing Constraint Table Entries. V8.~ming delays. Program the FPGA device.  For more information, see FPGA Compiler II Altera Edition FPGA Express Functions %FI Altera EditionFPGA Express to be used with other Synopsys tools. ƻ8 FPGA Compiler IIFPGA Compiler II Altera Edition FPGA Compiler IIFPGA Compiler II Altera Edition is a superset of the FPGA Express synthesis technology. It includes enhancements and additional features that especially benefit high-density FPGA and PLD design flows: Behavioral retiming and pipeliningRetiming redistributes registers in the critical paths to balance delay between them. Pipelining "breaks up" combinatorial logic by simple inclusion of a bank of registers placed before it to produce an optimized pipelined design. dc_shell scripting supportFPGA Compiler IIFPGA Compiler II Altera Edition both translates and writes out dc_shell scripts that you can use to migrate designs to ASIC technologies in Design Compiler. This feature exists only in FPGA Compiler IIFPGA Compiler II Altera Edition. .db file exportProjects created in FPGA Compiler IIFPGA Compiler II Altera Edition can be integrated into existing design flows with other Synopsys tools. This feature exieM 8^ Searches for nets, instances, ports, and modules in a schematic. This can be done either by selecting Find Schematic Object in the View menu or clicking the Find Schematic Object tool bar button.^AView / Find Schematic Object command Find Schematic Object buttonۻ8]Steps out of a hierarchy in a schematic. This can be done either by selecting Pop Up in the View menu or clicking the Pop Up tool bar button. ^#View / Pop Up command Pop Up button8])View / Push Down command Push Down button]Steps into a hierarchy in a schematic. This can be done either by selecting Pop Down in the View menu or clicking the Pop Down tool bar button.8] Demagnifies the schematic view by a factor of two. This can be done either by selecting Zoom Out in the View menu or clicking the Zoom Out tool bar button. ^'View / Zoom Out command Zoom Out button8] Magnifies the schematic view by a factor of two. This can be done either by selecting Zoom In in the View menu or clicking the Zoom In tool bar button.]%View / Zoom In command Zoom In buttonl8]-View / Zoom Full command Zoom Full-Fit button] Displays the entire schematic in one window. This can be done either by selecting Zoom Full-Fit in the View menu or clicking the Zoom Full-Fit tool-bar button. D8]View / View Tool Bar command]: Toggles display of the Tool Bar for schematic navigation.K8:Synthesis / Place and Route command Place and Route button}Z Launches Alteras Quartus place-and-route tool in the background and returns Quartus messages in the Status bar. There are two ways to launch Quartus. You can either select Synthesis>Place and Route Chip from the Synthesis menu or click the Place and Route tool bar icon when the optimized implementation is selected. This option is available for Alteras APEX20K and APEX20KE architectures only. R8Y]Back Annotate Chip When targeting any Actel ProASIC 500K device, FPGA Compiler IIFPGA Compiler II Altera EditionFPGA Express can import the post-place-and-route timing in SDF format from ASIC Master, Actels place-and-route tool, and display it in the constraint tables. Right-clicking an optimized chip and selecting Back Annotate Chip opens the Add SDF Sources dialog box for you to locate the SDF file. The information is then displayed as the Actual Delay in the appropriate constraint tables.8+T> d &WordMicrosoft Word   System    -& .  --    &WordMicrosoft Word  Systemw ;|w|wgww ; -@Times New Roman|wgw2 H - & .  --   b&*x &&#TNPPp0x & TNPP &&TNPP   b &,v&lr z& -333- * $+T $ $ $3y/u5{9 $oNiJYf_j $RL{HN $B<,2 $& " $ $    $2 . J N $c _ f j $ {   $    $  |  $v p l r $e _ O. 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Using Retiming for Pipelining To access retiming in the FPGA Compiler IIFPGA Compiler II Altera Edition GUI, right-click the elaborated chip in the Chips window and choose Edit Constraints from the pop-up menu. Select the Vendor Options tab and check the box next to Perform Retiming to enable the option. In the FPGA Compiler IIFPGA Compiler II Altera Edition shell, use the set_chip_retiming command on the elaborated chip: current_chip top set_chip_retiming enable The retiming feature is currently available for Alteras APEX20K and FLEX10K architectures and Xilinxs XC4000, Spartan, and Virtex architectures. Only flattened (non-hierarchical) designs can take advantage of this feature.`8 ]path of 11 ns and another path with a delay of 7.5 ns. By moving registers forward, retiming improves the critical path. In this example, moving the left register set forward would not improve the design performance. Moving the middle register set does increase the delay on the fastest path group (on the left) but it also reduces the delay on the slowest path group (on the right). Therefore, by moving the middle register set forward, the critical path can be improved from 11ns to 9.8 ns.  Register Retiming The availability of the retiming option also allows designers to pipeline combinatorial logic by adding registers at its input. In the example shown in Figure x, the original design had a combinatorial portion with a delay of 18 ns. A register bank (a bank of three registers in the example) can be added at the input of the design by easily editing the HDL source file. FPGA Compiler IIFPGA Compiler II Altera Edition will then, with the retiming option enabled, autom ]Register Retiming withFPGA Compiler IIFPGA Compiler II Altera Edition Register retiming is a high-level optimization technique to improve design performance and timing closure. This feature was only available in Synopsys Behavioral Compiler and Design Compiler Ultra for ASIC designers. In FPGA Compiler IIFPGA Compiler II Altera Edition, this capability has been tuned for high-density and high-performance programmable devices. The retiming technique applies when at least one critical path is not meeting timing requirements. It involves positioning the registers so that the delays from input to register, register to register, and register to output are all as small and as close to one another as possible. The retiming option allows designers to achieve better design performance, without having to manually modify the HDL source files. In the example shown in the following figure, the required clock period is 10 ns. The design implementation, before retiming, has a critical `8