Application Notes List    07/10/96

acf_app.wri	   ABEL pin assignments for PGA package -Altera
algrapnt.pdf       Use Acrobat reader - Allegro PCB Netlist Translator
arch.doc	   ABEL architecture & polarity discussion
back_up.wri	   Add backup a project command to Synario
bidirsim.wri	   Verilog simulation of bidir buses
brdsim22.zip	   V2.2 Board Simulation Example
cadence.zip	   Integrating Synario into the Cadence environment
cleanup.wri        Describes how to clean Synario/ABEL/SCS off PC
cypressfit.txt	   Suggestions for fitting Cypress devices
ecsconn.wri	   Large bussed connections in ECS
eet_app.doc	   Technical Paper: Multiple PLDs targeted to FPGA
fdkdoc.exe	   Technical Specification for FDK's; self-extracting
fdkdoc.zip	   Technical Specification for FDK's; zipped
larg_sim.wri       Increase memory available for large Verilog sims
liblist.doc	   Complete listing of PCB symbols for SECS V2.8
licdebug.doc	   Complete listing of Synario license error messages
m3_reuse.wri	   Reuse existing MAXPlus2 designs in Synario
macrolib.zip	   How to create a library of macro symbols + some macros
makebit.wri	   How to set command flag for Xilinx MAKEBIT program
massteck.doc	   How to use ECS with MASSTECK (ORCAD)
mentor.zip	   Intergrating Synario into the Mentor environment
neocad.zip	   Implement Xilinx,Motorola,ATT with neocad Place&Route 
netinst.wri	   Describes how to run Synario off of a network	 
pwrapppnt.pdf      Use Acrobat reader-PADs PowerPCB Netlist Translator
symbol.doc	   Creating Custom Symbols from ABEL modules
synpsys1.zip	   Migrating Synopsis VHDL designs to Synario V2.0    	
vbakint.zip	   Integrating VBAK into Project Navigator
vectors.wri	   How to create ABEL format test vectors from Verilog test fixture
vhdlapps.zip	   Various VHDL short app notes
vhdlcon.doc	   VHDL supported/unsupported constructs
vhdlex.zip	   VHDL simple test bench example
xblox.wri	   Tech Note: known problem with XBLOX output