module gcount; title '8 Bit Pseudo Grey Code Counter and decode for ATMEL V750 Keith Gudger ATMEL May 15, 1991' gcount device 'P750'; "ABEL 4.x Only @message 'Using P750 device file and ATMEL-ABEL'; " " This example is of a Mealy state machine - in other words, " combinatorial outputs are generated from the machine states and the " combinatorial inputs. This is actually a very common design - " decoding the state machine's outputs into combinatorial outputs. " Problems can arise when pure binary counters are used, as many bits " are changing simulataneously. Race conditions can result and " glitches appear on combinatorial outputs when many inputs change " simulataneously. We recommend using a grey coded counter. However, " it is easier to define a large counter with Boolean equations than " with a state machine diagram. This example is a pseudo grey code " counter for 8 bits. Smaller counters can be cut down from this one " and larger ones can be built up using the same algorithm. " " Clk , D0, D1, D2, D3 pin 1, 2, 3, 4, 5; rest, OEB pin 6, 7; O64 , O128 , O63 , O127 pin 14,15,16,17; " Some Combinatorial O16 , O32 , O15 , O31 pin 18,19,20,21; " Outputs O7 , O8 pin 22,23; Q0, Q1, Q2, Q3, Q4 node 26,35,27,34,28 istype 'reg_d'; " Buried State Q5, Q6, Q7 node 33,30,31 istype 'reg_d'; " Registers " Nodes Description " 26..35 Q1 for pins 14 to 23 "Sets (Sets make definitions easier) OUTS = [O128,O127,O64,O63,O32,O31,O16,O15,O8,O7] ; Qcks = [Q7.C,Q6.C,Q5.C,Q4.C,Q3.C,Q2.C,Q1.C,Q0.C] ; " Clock definitions Qrst = [Q7.RE,Q6.RE,Q5.RE,Q4.RE,Q3.RE,Q2.RE,Q1.RE,Q0.RE] ; " Reset definitions " Test Vector definitions QBur = [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0] ; Din = [D3,D2,D1,D0] ; H,L,Z,C,X,U,D = 1,0,.Z.,.C.,.X.,.U.,.D. ; Equations Qrst = rest ; " All the resets are defined at once this way Qcks = Clk ; " The V750 requires clock terms to be defined OUTS.OE = !OEB ; " defines all output enables at once Q0.D = !Q1 ; Q1.D = Q0 ; " The first 2 bits in this counter are very simple. Q2.D = !Q3 & Q1 & Q0 " These 2 terms get expanded for # Q2 & (!Q1 # !Q0) ; " each 2 bits added. Q3.D = Q2 & Q1 & Q0 # Q3 & (!Q1 # !Q0) ; Q4.D = !Q5 & Q3 & Q2 & Q1 & Q0 # Q4 & Q3 & Q2 & (!Q1 # !Q0) # Q4 & Q3 & !Q2 " 2 new terms are # Q4 & !Q3 ; " added each time Q5.D = Q4 & Q3 & Q2 & Q1 & Q0 # Q5 & Q3 & Q2 & (!Q1 # !Q0) # Q5 & Q3 & !Q2 # Q5 & !Q3 ; Q6.D = !Q7 & Q5 & Q4 & Q3 & Q2 & Q1 & Q0 # Q6 & Q5 & Q4 & Q3 & Q2 & (!Q1 # !Q0) # Q6 & Q5 & Q4 & Q3 & !Q2 # Q6 & Q5 & Q4 & !Q3 " Follow this format # Q6 & Q5 & !Q4 " for each new pair # Q6 & !Q5 ; " of bits added. Q7.D = Q6 & Q5 & Q4 & Q3 & Q2 & Q1 & Q0 # Q7 & Q5 & Q4 & Q3 & Q2 & (!Q1 # !Q0) # Q7 & Q5 & Q4 & Q3 & !Q2 # Q7 & Q5 & Q4 & !Q3 # Q7 & Q5 & !Q4 # Q7 & !Q5 ; " The following 10 output equations were chosen to select locations " that could cause problems in a straight binary counter, i.e. places " where many bits are changing states. O128 = ( D3 & !D2 & !D1 & D0 & Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & !Q1 & !Q0) # ( D3 & !D2 & D1 & !D0 & Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & !Q1 & !Q0); O127 = ( D3 & !D2 & !D1 & D0 & Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & Q1 & !Q0) # ( D3 & !D2 & D1 & !D0 & Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & Q1 & !Q0); O64 = (!D3 & D2 & D1 & D0 & !Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & !Q1 & !Q0) # ( D3 & !D2 & !D1 & !D0 & !Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & !Q1 & !Q0); O63 = (!D3 & D2 & D1 & D0 & !Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & Q1 & !Q0) # ( D3 & !D2 & !D1 & !D0 & !Q7 & Q6 & !Q5 & !Q4 & !Q3 & !Q2 & Q1 & !Q0); O32 = (!D3 & D2 & !D1 & D0 & !Q7 & !Q6 & Q5 & Q4 & !Q3 & !Q2 & !Q1 & !Q0) # (!D3 & D2 & D1 & !D0 & !Q7 & !Q6 & Q5 & Q4 & !Q3 & !Q2 & !Q1 & !Q0); O31 = (!D3 & D2 & !D1 & D0 & !Q7 & !Q6 & Q5 & Q4 & !Q3 & !Q2 & Q1 & !Q0) # (!D3 & D2 & D1 & !D0 & !Q7 & !Q6 & Q5 & Q4 & !Q3 & !Q2 & Q1 & !Q0); O16 = (!D3 & !D2 & D1 & D0 & !Q7 & !Q6 & !Q5 & Q4 & !Q3 & !Q2 & !Q1 & !Q0) # (!D3 & D2 & !D1 & !D0 & !Q7 & !Q6 & !Q5 & Q4 & !Q3 & !Q2 & !Q1 & !Q0); O15 = (!D3 & !D2 & D1 & D0 & !Q7 & !Q6 & !Q5 & Q4 & !Q3 & !Q2 & Q1 & !Q0) # (!D3 & D2 & !D1 & !D0 & !Q7 & !Q6 & !Q5 & Q4 & !Q3 & !Q2 & Q1 & !Q0); O8 = (!D3 & !D2 & !D1 & D0 & !Q7 & !Q6 & !Q5 & !Q4 & Q3 & Q2 & !Q1 & !Q0) # (!D3 & !D2 & D1 & !D0 & !Q7 & !Q6 & !Q5 & !Q4 & Q3 & Q2 & !Q1 & !Q0); O7 = (!D3 & !D2 & !D1 & D0 & !Q7 & !Q6 & !Q5 & !Q4 & Q3 & Q2 & Q1 & !Q0) # (!D3 & !D2 & D1 & !D0 & !Q7 & !Q6 & !Q5 & !Q4 & Q3 & Q2 & Q1 & !Q0); @radix 2; test_vectors ([Clk , Din ,rest,OEB] -> [ QBur , OUTS ]) [ 0 , 0001 , 1 , 1 ] -> [ 00000000 , Z ]; [ 0 , 0001 , 0 , 0 ] -> [ 00000000 , 0000000000 ]; [ C , 0001 , 0 , 0 ] -> [ 00000001 , 0000000000 ]; [ C , 0001 , 0 , 0 ] -> [ 00000011 , 0000000000 ]; [ C , 0001 , 0 , 0 ] -> [ 00000110 , 0000000000 ]; " 5 [ C , 0001 , 0 , 0 ] -> [ 00000100 , 0000000000 ]; [ C , 0001 , 0 , 0 ] -> [ 00000101 , 0000000000 ]; [ C , 0001 , 0 , 0 ] -> [ 00000111 , 0000000000 ]; " 8 [ C , 0001 , 0 , 0 ] -> [ 00001110 , 0000000001 ]; [ 0 , 0010 , 0 , 0 ] -> [ 00001110 , 0000000001 ]; [ 0 , 0011 , 0 , 0 ] -> [ 00001110 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00001100 , 0000000000 ]; [ 0 , 0010 , 0 , 0 ] -> [ 00001100 , 0000000010 ]; [ 0 , 0001 , 0 , 0 ] -> [ 00001100 , 0000000010 ]; [ C , 0011 , 0 , 0 ] -> [ 00001101 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00001111 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00011010 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00011000 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00011001 , 0000000000 ]; [ C , 0011 , 0 , 0 ] -> [ 00011011 , 0000000000 ]; " 16 [ C , 0011 , 0 , 0 ] -> [ 00010010 , 0000000100 ]; [ 0 , 0100 , 0 , 0 ] -> [ 00010010 , 0000000100 ]; [ 0 , 0101 , 0 , 0 ] -> [ 00010010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0101 , 0 , 0 ] -> [ 00010000 , 0000000000 ]; [ 0 , 0100 , 0 , 0 ] -> [ 00010000 , 0000001000 ]; [ 0 , 0011 , 0 , 0 ] -> [ 00010000 , 0000001000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00010111 , 0000000000 ]; " 24 [ C , 0110 , 0 , 0 ] -> [ 00011110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00011100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00011101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00011111 , 0000000000 ]; [ C , 1110 , 0 , 0 ] -> [ 00111010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00111000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00111001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 00111011 , 0000000000 ]; " 32 [ C , 0110 , 0 , 0 ] -> [ 00110010 , 0000010000 ]; [ 0 , 0101 , 0 , 0 ] -> [ 00110010 , 0000010000 ]; [ 0 , 0111 , 0 , 0 ] -> [ 00110010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0111 , 0 , 0 ] -> [ 00110000 , 0000000000 ]; [ 0 , 0110 , 0 , 0 ] -> [ 00110000 , 0000100000 ]; [ 0 , 0101 , 0 , 0 ] -> [ 00110000 , 0000100000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110001 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110011 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110110 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110100 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110101 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00110111 , 0000000000 ]; " 40 [ C , 0111 , 0 , 0 ] -> [ 00111110 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00111100 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00111101 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 00111111 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101010 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101000 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101001 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101011 , 0000000000 ]; " 48 [ C , 0111 , 0 , 0 ] -> [ 01100010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0111 , 0 , 0 ] -> [ 01100000 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100001 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100011 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100110 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100100 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100101 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01100111 , 0000000000 ]; " 56 [ C , 0111 , 0 , 0 ] -> [ 01101110 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101100 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101101 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01101111 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01001010 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01001000 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01001001 , 0000000000 ]; [ C , 0111 , 0 , 0 ] -> [ 01001011 , 0000000000 ]; " 64 [ C , 0111 , 0 , 0 ] -> [ 01000010 , 0001000000 ]; [ 0 , 1000 , 0 , 0 ] -> [ 01000010 , 0001000000 ]; [ 0 , 1001 , 0 , 0 ] -> [ 01000010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 1001 , 0 , 0 ] -> [ 01000000 , 0000000000 ]; [ 0 , 1000 , 0 , 0 ] -> [ 01000000 , 0010000000 ]; [ 0 , 0111 , 0 , 0 ] -> [ 01000000 , 0010000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01000111 , 0000000000 ]; " 72 [ C , 0110 , 0 , 0 ] -> [ 01001110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01001100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01001101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01001111 , 0000000000 ]; " 76 [ C , 0110 , 0 , 0 ] -> [ 01011010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011011 , 0000000000 ]; [ C , 1110 , 0 , 0 ] -> [ 01010010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 1110 , 0 , 0 ] -> [ 01010000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01010001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01010011 , 0000000000 ]; " 84 [ C , 0110 , 0 , 0 ] -> [ 01010110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01010100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01010101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01010111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01011111 , 0000000000 ]; " 92 [ C , 0110 , 0 , 0 ] -> [ 01111010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0110 , 0 , 0 ] -> [ 01110000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110011 , 0000000000 ]; "100 [ C , 0110 , 0 , 0 ] -> [ 01110110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01110111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 01111111 , 0000000000 ]; "108 [ C , 0110 , 0 , 0 ] -> [ 11101010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11101000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11101001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11101011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11100010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 1010 , 0 , 0 ] -> [ 11100000 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11100001 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11100011 , 0000000000 ]; "116 [ C , 1010 , 0 , 0 ] -> [ 11100110 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11100100 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11100101 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11100111 , 0000000000 ]; "120 [ C , 1010 , 0 , 0 ] -> [ 11101110 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11101100 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11101101 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11101111 , 0000000000 ]; "124 [ C , 1010 , 0 , 0 ] -> [ 11001010 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11001000 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11001001 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11001011 , 0000000000 ]; [ C , 1010 , 0 , 0 ] -> [ 11000010 , 0100000000 ]; [ 0 , 1001 , 0 , 0 ] -> [ 11000010 , 0100000000 ]; [ 0 , 0111 , 0 , 0 ] -> [ 11000010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0111 , 0 , 0 ] -> [ 11000000 , 0000000000 ]; [ 0 , 1001 , 0 , 0 ] -> [ 11000000 , 1000000000 ]; [ 0 , 1010 , 0 , 0 ] -> [ 11000000 , 1000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11000001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11000011 , 0000000000 ]; "132 [ C , 0110 , 0 , 0 ] -> [ 11000110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11000100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11000101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11000111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11001110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11001100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11001101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11001111 , 0000000000 ]; "140 [ C , 0110 , 0 , 0 ] -> [ 11011010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0110 , 0 , 0 ] -> [ 11010000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010011 , 0000000000 ]; "148 [ C , 0110 , 0 , 0 ] -> [ 11010110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11010111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11011111 , 0000000000 ]; "156 [ C , 0110 , 0 , 0 ] -> [ 11111010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0110 , 0 , 0 ] -> [ 11110000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110011 , 0000000000 ]; "164 [ C , 0110 , 0 , 0 ] -> [ 11110110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11110111 , 0000000000 ]; "168 [ C , 0110 , 0 , 0 ] -> [ 11111110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 11111111 , 0000000000 ]; "172 [ C , 0110 , 0 , 0 ] -> [ 10101010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101011 , 0000000000 ]; "176 [ C , 0110 , 0 , 0 ] -> [ 10100010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , ]) [ C , 0110 , 0 , 0 ] -> [ 10100000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10100001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10100011 , 0000000000 ]; "180 [ C , 0110 , 0 , 0 ] -> [ 10100110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10100100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10100101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10100111 , 0000000000 ]; "184 [ C , 0110 , 0 , 0 ] -> [ 10101110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10101111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001011 , 0000000000 ]; "192 [ C , 0110 , 0 , 0 ] -> [ 10000010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0110 , 0 , 0 ] -> [ 10000000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10000001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10000011 , 0000000000 ]; "200 [ C , 0110 , 0 , 0 ] -> [ 10000110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10000100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10000101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10000111 , 0000000000 ]; "204 [ C , 0110 , 0 , 0 ] -> [ 10001110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10001111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011011 , 0000000000 ]; "212 [ C , 0110 , 0 , 0 ] -> [ 10010010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , OUTS ]) [ C , 0110 , 0 , 0 ] -> [ 10010000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10010111 , 0000000000 ]; "220 [ C , 0110 , 0 , 0 ] -> [ 10011110 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011100 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011101 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10011111 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10111010 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10111000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10111001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10111011 , 0000000000 ]; "228 [ C , 0110 , 0 , 0 ] -> [ 10110010 , 0000000000 ]; "[Clk , Din ,rest,OEB] -> [ Qbur , ]) [ C , 0110 , 0 , 0 ] -> [ 10110000 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10110001 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10110011 , 0000000000 ]; [ C , 0110 , 0 , 0 ] -> [ 10110110 , 0000000000 ]; End