Answers Database
2.1i: TRCE/Timing Analyzer: Does not support reg_sr_clk path tracing control.
Record #6450
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 2.1i
Problem Title:
2.1i: TRCE/Timing Analyzer: Does not support reg_sr_clk path tracing control.
Problem Description:
Urgency: Standard
General Description:
How to get support for tracing control on the timing of the
Set/Reset to Clock on a flip flop?
Solution 1:
Set the following in the PCF file:
enable = reg_sr_clk
enable = reg_sr_q;
This will be fixed in a future release.
End of Record #6450 - Last Modified: 12/21/99 14:43 | 
