-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:18:05 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity IF_CASE is
  port (
    RESET : in STD_LOGIC := 'X' ;
    CLK : in STD_LOGIC := 'X' ;
    ADDR_A : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_B : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_C : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    ADDR_D : in  STD_LOGIC_VECTOR ( 1 downto 0 );
    DEC_Q : out  STD_LOGIC_VECTOR ( 5 downto 0 )
  ) ;
end IF_CASE ;

architecture STRUCTURE of IF_CASE is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N260 , N261 , N262 , N263 , N264 , N265 , N266 , N267 , N268 , N269 , 
  N312 , N311 , N333 , N332 , N335 , N334 , N336 , N338 , N337 , N340 , N339 , 
  DEC_Q_REG_5_1I11_QINT , DEC_Q_REG_5_1I11_OBUF_GTS_TRI , DEC_Q_REG_4_1I11_QINT 
  , DEC_Q_REG_4_1I11_OBUF_GTS_TRI , DEC_Q_REG_3_1I11_QINT , 
  DEC_Q_REG_3_1I11_OBUF_GTS_TRI , DEC_Q_REG_2_1I11_QINT , 
  DEC_Q_REG_2_1I11_OBUF_GTS_TRI , DEC_Q_REG_1_1I11_QINT , 
  DEC_Q_REG_1_1I11_OBUF_GTS_TRI , DEC_Q_REG_0_1I11_QINT , 
  DEC_Q_REG_0_1I11_OBUF_GTS_TRI , U126_CLKIO_BUFSIG , U127_2_0 , U127_2_1 , 
  U128_2_0 , U128_2_1 , U140_2_0 , U143_2_0 , U131_2_INV , U132_2_INV , 
  U133_2_INV , U134_2_INV , U135_2_INV , U137_2_INV , U127_N312_2_INV , 
  DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV , 
  DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV , 
  DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV , DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV , 
  GND , VCC , GSR , GTS : STD_LOGIC ;
  signal DEC_Q70 : STD_LOGIC_VECTOR ( 5 downto 0 );
  begin
    U117 : X_BUF 
      port map ( I => ADDR_A(1) , O => N260 ) ;
    U118 : X_BUF 
      port map ( I => ADDR_A(0) , O => N261 ) ;
    U119 : X_BUF 
      port map ( I => ADDR_B(1) , O => N262 ) ;
    U120 : X_BUF 
      port map ( I => ADDR_B(0) , O => N263 ) ;
    U121 : X_BUF 
      port map ( I => ADDR_C(1) , O => N264 ) ;
    U122 : X_BUF 
      port map ( I => ADDR_C(0) , O => N265 ) ;
    U123 : X_BUF 
      port map ( I => ADDR_D(1) , O => N266 ) ;
    U124 : X_BUF 
      port map ( I => ADDR_D(0) , O => N267 ) ;
    U125 : X_BUF 
      port map ( I => RESET , O => N268 ) ;
    U129 : X_INV 
      port map ( I => N332 , O => N333 ) ;
    U130 : X_XOR2 
      port map ( I0 => N263 , I1 => N262 , O => N332 ) ;
    U131 : X_OR2 
      port map ( I0 => N333 , I1 => N268 , O => U131_2_INV ) ;
    U132 : X_OR2 
      port map ( I0 => N263 , I1 => N268 , O => U132_2_INV ) ;
    U133 : X_OR2 
      port map ( I0 => N261 , I1 => N334 , O => U133_2_INV ) ;
    U134 : X_OR2 
      port map ( I0 => N312 , I1 => N311 , O => U134_2_INV ) ;
    U135 : X_OR2 
      port map ( I0 => N335 , I1 => N268 , O => U135_2_INV ) ;
    U136 : X_INV 
      port map ( I => N260 , O => N336 ) ;
    U137 : X_OR2 
      port map ( I0 => N268 , I1 => N336 , O => U137_2_INV ) ;
    U138 : X_OR2 
      port map ( I0 => N311 , I1 => N312 , O => N338 ) ;
    U139 : X_INV 
      port map ( I => N268 , O => N337 ) ;
    U141 : X_OR2 
      port map ( I0 => N311 , I1 => N312 , O => N340 ) ;
    U142 : X_INV 
      port map ( I => N268 , O => N339 ) ;
    DEC_Q_REG_5_1I11_FF : X_FF 
      port map ( I => DEC_Q70(5) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_5_1I11_QINT ) ;
    DEC_Q_REG_5_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_5_1I11_QINT , 
      O => DEC_Q_REG_5_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_5_1I11_OBUF_GTS_TRI_0 : X_TRI 
      port map ( I => DEC_Q_REG_5_1I11_OBUF_GTS_TRI , O => DEC_Q(5) , 
      CTL => DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_4_1I11_FF : X_FF 
      port map ( I => DEC_Q70(4) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_4_1I11_QINT ) ;
    DEC_Q_REG_4_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_4_1I11_QINT , 
      O => DEC_Q_REG_4_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_4_1I11_OBUF_GTS_TRI_1 : X_TRI 
      port map ( I => DEC_Q_REG_4_1I11_OBUF_GTS_TRI , O => DEC_Q(4) , 
      CTL => DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_3_1I11_FF : X_FF 
      port map ( I => DEC_Q70(3) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_3_1I11_QINT ) ;
    DEC_Q_REG_3_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_3_1I11_QINT , 
      O => DEC_Q_REG_3_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2 : X_TRI 
      port map ( I => DEC_Q_REG_3_1I11_OBUF_GTS_TRI , O => DEC_Q(3) , 
      CTL => DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_2_1I11_FF : X_FF 
      port map ( I => DEC_Q70(2) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_2_1I11_QINT ) ;
    DEC_Q_REG_2_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_2_1I11_QINT , 
      O => DEC_Q_REG_2_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_2_1I11_OBUF_GTS_TRI_3 : X_TRI 
      port map ( I => DEC_Q_REG_2_1I11_OBUF_GTS_TRI , O => DEC_Q(2) , 
      CTL => DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_1_1I11_FF : X_FF 
      port map ( I => DEC_Q70(1) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_1_1I11_QINT ) ;
    DEC_Q_REG_1_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_1_1I11_QINT , 
      O => DEC_Q_REG_1_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_1_1I11_OBUF_GTS_TRI_4 : X_TRI 
      port map ( I => DEC_Q_REG_1_1I11_OBUF_GTS_TRI , O => DEC_Q(1) , 
      CTL => DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_0_1I11_FF : X_FF 
      port map ( I => DEC_Q70(0) , CLK => N269 , CE => VCC , SET => GND , 
      RST => GSR , O => DEC_Q_REG_0_1I11_QINT ) ;
    DEC_Q_REG_0_1I11_OBUF : X_BUF 
      port map ( I => DEC_Q_REG_0_1I11_QINT , 
      O => DEC_Q_REG_0_1I11_OBUF_GTS_TRI ) ;
    DEC_Q_REG_0_1I11_OBUF_GTS_TRI_5 : X_TRI 
      port map ( I => DEC_Q_REG_0_1I11_OBUF_GTS_TRI , O => DEC_Q(0) , 
      CTL => DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    U126_CLKBUF : X_CKBUF 
      port map ( I => U126_CLKIO_BUFSIG , O => N269 ) ;
    U126_CLKIO_BUF : X_BUF 
      port map ( I => CLK , O => U126_CLKIO_BUFSIG ) ;
    U127_N312_2_0 : X_AND2 
      port map ( I0 => N263 , I1 => N264 , O => U127_2_0 ) ;
    U127_N312_2_1 : X_AND2 
      port map ( I0 => N266 , I1 => N267 , O => U127_2_1 ) ;
    U127_N312 : X_AND2 
      port map ( I0 => U127_2_0 , I1 => U127_2_1 , O => U127_N312_2_INV ) ;
    U128_N311_2_0 : X_OR2 
      port map ( I0 => N260 , I1 => N261 , O => U128_2_0 ) ;
    U128_N311_2_1 : X_OR2 
      port map ( I0 => N262 , I1 => N265 , O => U128_2_1 ) ;
    U128_N311 : X_OR2 
      port map ( I0 => U128_2_0 , I1 => U128_2_1 , O => N311 ) ;
    U140_DEC_Q70_4_2_0 : X_AND2 
      port map ( I0 => N338 , I1 => N337 , O => U140_2_0 ) ;
    U140_DEC_Q70_4_Q : X_AND2 
      port map ( I0 => U140_2_0 , I1 => N267 , O => DEC_Q70(4) ) ;
    U143_DEC_Q70_5_2_0 : X_AND2 
      port map ( I0 => N340 , I1 => N339 , O => U143_2_0 ) ;
    U143_DEC_Q70_5_Q : X_AND2 
      port map ( I0 => U143_2_0 , I1 => N266 , O => DEC_Q70(5) ) ;
    U131_2_INV_6 : X_INV 
      port map ( I => U131_2_INV , O => DEC_Q70(1) ) ;
    U132_2_INV_7 : X_INV 
      port map ( I => U132_2_INV , O => DEC_Q70(0) ) ;
    U133_2_INV_8 : X_INV 
      port map ( I => U133_2_INV , O => N335 ) ;
    U134_2_INV_9 : X_INV 
      port map ( I => U134_2_INV , O => N334 ) ;
    U135_2_INV_10 : X_INV 
      port map ( I => U135_2_INV , O => DEC_Q70(2) ) ;
    U137_2_INV_11 : X_INV 
      port map ( I => U137_2_INV , O => DEC_Q70(3) ) ;
    U127_N312_2_INV_12 : X_INV 
      port map ( I => U127_N312_2_INV , O => N312 ) ;
    DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV_13 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV_14 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV_15 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV_16 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV_17 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV_18 : X_INV 
      port map ( I => GTS , O => DEC_Q_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    VCC_19 : X_ONE 
      port map ( O => VCC ) ;
    GND_20 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

