-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:08:55 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity RAM_PRIMITIVE is
  port (
    WE : in STD_LOGIC := 'X' ;
    CLOCK : in STD_LOGIC := 'X' ;
    DATA_IN : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    ADDR : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    DATA_OUT : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end RAM_PRIMITIVE ;

architecture STRUCTURE of RAM_PRIMITIVE is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N90 , N31 , N32 , N33 , N34 , N35 , N36 , N37 , N89 , N30 , N88 , N29 
  , N87 , N28 , U68_1I20_GTS_TRI , U69_1I20_GTS_TRI , U70_1I20_GTS_TRI , 
  U71_1I20_GTS_TRI , U67_CLKIO_BUFSIG , U68_1I20_GTS_TRI_2_INV , 
  U69_1I20_GTS_TRI_2_INV , U70_1I20_GTS_TRI_2_INV , U71_1I20_GTS_TRI_2_INV , 
  GTS : STD_LOGIC ;
  begin
    RAM0 : X_RAMS16 
      generic map ( INIT => "FFF0" ) 
      port map ( ADR0 => N35 , ADR1 => N34 , ADR2 => N33 , ADR3 => N32 , 
      I => N31 , CLK => N37 , WE => N36 , O => N90 ) ;
    RAM1 : X_RAMS16 
      generic map ( INIT => "C848" ) 
      port map ( ADR0 => N35 , ADR1 => N34 , ADR2 => N33 , ADR3 => N32 , 
      I => N30 , CLK => N37 , WE => N36 , O => N89 ) ;
    RAM2 : X_RAMS16 
      generic map ( INIT => "8484" ) 
      port map ( ADR0 => N35 , ADR1 => N34 , ADR2 => N33 , ADR3 => N32 , 
      I => N29 , CLK => N37 , WE => N36 , O => N88 ) ;
    RAM3 : X_RAMS16 
      generic map ( INIT => "F302" ) 
      port map ( ADR0 => N35 , ADR1 => N34 , ADR2 => N33 , ADR3 => N32 , 
      I => N28 , CLK => N37 , WE => N36 , O => N87 ) ;
    U58 : X_BUF 
      port map ( I => DATA_IN(3) , O => N28 ) ;
    U59 : X_BUF 
      port map ( I => DATA_IN(2) , O => N29 ) ;
    U60 : X_BUF 
      port map ( I => DATA_IN(1) , O => N30 ) ;
    U61 : X_BUF 
      port map ( I => DATA_IN(0) , O => N31 ) ;
    U62 : X_BUF 
      port map ( I => ADDR(3) , O => N32 ) ;
    U63 : X_BUF 
      port map ( I => ADDR(2) , O => N33 ) ;
    U64 : X_BUF 
      port map ( I => ADDR(1) , O => N34 ) ;
    U65 : X_BUF 
      port map ( I => ADDR(0) , O => N35 ) ;
    U66 : X_BUF 
      port map ( I => WE , O => N36 ) ;
    U68_1I20 : X_BUF 
      port map ( I => N87 , O => U68_1I20_GTS_TRI ) ;
    U68_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U68_1I20_GTS_TRI , O => DATA_OUT(3) , 
      CTL => U68_1I20_GTS_TRI_2_INV ) ;
    U69_1I20 : X_BUF 
      port map ( I => N88 , O => U69_1I20_GTS_TRI ) ;
    U69_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U69_1I20_GTS_TRI , O => DATA_OUT(2) , 
      CTL => U69_1I20_GTS_TRI_2_INV ) ;
    U70_1I20 : X_BUF 
      port map ( I => N89 , O => U70_1I20_GTS_TRI ) ;
    U70_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U70_1I20_GTS_TRI , O => DATA_OUT(1) , 
      CTL => U70_1I20_GTS_TRI_2_INV ) ;
    U71_1I20 : X_BUF 
      port map ( I => N90 , O => U71_1I20_GTS_TRI ) ;
    U71_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U71_1I20_GTS_TRI , O => DATA_OUT(0) , 
      CTL => U71_1I20_GTS_TRI_2_INV ) ;
    U67_CLKBUF : X_CKBUF 
      port map ( I => U67_CLKIO_BUFSIG , O => N37 ) ;
    U67_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U67_CLKIO_BUFSIG ) ;
    U68_1I20_GTS_TRI_2_INV_4 : X_INV 
      port map ( I => GTS , O => U68_1I20_GTS_TRI_2_INV ) ;
    U69_1I20_GTS_TRI_2_INV_5 : X_INV 
      port map ( I => GTS , O => U69_1I20_GTS_TRI_2_INV ) ;
    U70_1I20_GTS_TRI_2_INV_6 : X_INV 
      port map ( I => GTS , O => U70_1I20_GTS_TRI_2_INV ) ;
    U71_1I20_GTS_TRI_2_INV_7 : X_INV 
      port map ( I => GTS , O => U71_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

