---------------------------------------
--  BIDIR_LOGIBLOX.VHD Version 1.0   --
--  Example of using LogiBLOX        --
--  to create a Bi-directional port  --
--  August 1997                      --
---------------------------------------
------------------------------------------------------
-- LogiBLOX BIDI Module "bidir_io_from_lb"
-- Created by LogiBLOX version M1.3.7
--    on Mon Sep  8 13:14:02 1997
-- Attributes 
--    MODTYPE = BIDI
--    BUS_WIDTH = 2
--    IN_TYPE = LATCH
--    OUT_TYPE = TRI
------------------------------------------------------

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity bidir_logiblox is

    port (DATA :       inout STD_LOGIC_VECTOR(1 downto 0);
	  READ_WRITE : in    STD_LOGIC);

end bidir_logiblox;

architecture XILINX of bidir_logiblox is

    signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0);
    signal DATA_OUT :  STD_LOGIC_VECTOR(1 downto 0);

    ----------------------------------------------------
    -- Component Declaration 
    ----------------------------------------------------
    component bidir_io_from_lb
        PORT( O:     IN    STD_LOGIC_VECTOR(1 DOWNTO 0);
              OE:    IN    STD_LOGIC;
              IGATE: IN    STD_LOGIC;
              IQ:    OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
              P:     INOUT STD_LOGIC_VECTOR(1 DOWNTO 0));
    end component;

    begin
		
    DATA_OUT(0) <= LATCH_OUT(0) and LATCH_OUT(1);
    DATA_OUT(1) <= LATCH_OUT(0) or LATCH_OUT(1);

    ----------------------------------------------------
    -- Component Instantiation 
    ----------------------------------------------------
    BIDIR_BUSSED_PORT : bidir_io_from_lb 
        port map (O => DATA_OUT, OE => READ_WRITE,
                  IGATE => READ_WRITE, IQ => LATCH_OUT, P => DATA);

end XILINX;
