Gate_clock and Gate_clock2
Synopsys Synthesis Design Guide
May 1997
===============================

Both examples contain the same code, a single FF with a clock enable being
clocked by a gated signal consisting of a three input NAND gate with the
inputs consisitng of IN1, IN2 and CLK.  The difference between Gate_clock
and Gate_clock2 is in the controlling of the clock buffers from the synthesis
script.  Gate_clock does a standard set_port_is_pad "*" and insert_pads.
Since Synopsys identifies that each of these signals arives at a FF clock
pin, it inserts a clock buffer on each port.  The second script forces
Synopsys to use standard IBUFs on IN1 and IN2 while CLK gets a global buffer. 
The idea is to save the global buffers for the higher fanout signals.

Typically, a better implementation would be to use the clock enable pin as
illustrated in the Clock_Enable example.
