------------------------------------------
-- RAM_PRIMITIVE.VHD Version 1.0        --
-- Example of instantiating 4           --
-- 16x1 synchronous RAMs                --
-- HDL Synthesis Design Guide for FPGAs --
-- May 1997                             --
------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

 
entity ram_primitive is

   port ( DATA_IN, ADDR  : in STD_LOGIC_VECTOR(3 downto 0);
          WE, CLOCK      : in STD_LOGIC;
          DATA_OUT       : out STD_LOGIC_VECTOR(3 downto 0));

end ram_primitive;


architecture STRUCTURAL_RAM of ram_primitive is

   component RAM16X1S
       port (D, A3, A2, A1, A0, WE, WCLK : in STD_LOGIC;
             O : out STD_LOGIC);
   end component;
 
begin

   RAM0 :  RAM16X1S port map (O => DATA_OUT(0), D => DATA_IN(0), 
                              A3 => ADDR(3), A2 => ADDR(2), 
                              A1 => ADDR(1), A0 => ADDR(0),
                              WE => WE, WCLK => CLOCK);

   RAM1 :  RAM16X1S port map (O => DATA_OUT(1), D => DATA_IN(1), 
                              A3 => ADDR(3), A2 => ADDR(2),
                              A1 => ADDR(1), A0 => ADDR(0), 
                              WE => WE, WCLK => CLOCK);

   RAM2 :  RAM16X1S port map (O => DATA_OUT(2), D => DATA_IN(2), 
                              A3 => ADDR(3), A2 => ADDR(2),
                              A1 => ADDR(1), A0 => ADDR(0), 
                              WE => WE, WCLK => CLOCK);

   RAM3 :  RAM16X1S port map (O => DATA_OUT(3), D => DATA_IN(3), 
                              A3 => ADDR(3), A2 => ADDR(2),
                              A1 => ADDR(1), A0 => ADDR(0), 
                              WE => WE, WCLK => CLOCK);

end STRUCTURAL_RAM;
