-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:05:37 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity FF_EXAMPLE is
  port (
    RESET : in STD_LOGIC := 'X' ;
    CLOCK : in STD_LOGIC := 'X' ;
    ENABLE : in STD_LOGIC := 'X' ;
    D_IN : in  STD_LOGIC_VECTOR ( 7 downto 0 );
    A_Q_OUT : out  STD_LOGIC_VECTOR ( 7 downto 0 );
    B_Q_OUT : out  STD_LOGIC_VECTOR ( 7 downto 0 );
    C_Q_OUT : out  STD_LOGIC_VECTOR ( 7 downto 0 );
    D_Q_OUT : out  STD_LOGIC_VECTOR ( 7 downto 0 )
  ) ;
end FF_EXAMPLE ;

architecture STRUCTURE of FF_EXAMPLE is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N232 , N233 , N234 , N235 , N236 , N237 , N238 , N239 , N240 , N241 , 
  N242 , N447 , N448 , N449 , N450 , N451 , N452 , N453 , N454 , N455 , N456 , 
  N457 , N458 , N459 , N460 , N461 , N462 , N463 , N464 , N465 , N466 , N467 , 
  N468 , N469 , N470 , D_Q_OUT_REG_6_GSR_OR , D_Q_OUT_REG_7_GSR_OR , 
  D_Q_OUT_REG_4_GSR_OR , D_Q_OUT_REG_5_GSR_OR , D_Q_OUT_REG_2_GSR_OR , 
  D_Q_OUT_REG_3_GSR_OR , D_Q_OUT_REG_0_GSR_OR , D_Q_OUT_REG_1_GSR_OR , 
  A_Q_OUT_REG_7_1I11_QINT , A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_6_1I11_QINT , A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_5_1I11_QINT , A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_4_1I11_QINT , A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_3_1I11_QINT , A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_2_1I11_QINT , A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_1_1I11_QINT , A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI , 
  A_Q_OUT_REG_0_1I11_QINT , A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI , U275_1I20_GTS_TRI 
  , U276_1I20_GTS_TRI , U277_1I20_GTS_TRI , U278_1I20_GTS_TRI , 
  U279_1I20_GTS_TRI , U280_1I20_GTS_TRI , U281_1I20_GTS_TRI , U282_1I20_GTS_TRI 
  , U283_1I20_GTS_TRI , U284_1I20_GTS_TRI , U285_1I20_GTS_TRI , 
  U286_1I20_GTS_TRI , U287_1I20_GTS_TRI , U288_1I20_GTS_TRI , U289_1I20_GTS_TRI 
  , U290_1I20_GTS_TRI , U291_1I20_GTS_TRI , U292_1I20_GTS_TRI , 
  U293_1I20_GTS_TRI , U294_1I20_GTS_TRI , U295_1I20_GTS_TRI , U296_1I20_GTS_TRI 
  , U297_1I20_GTS_TRI , U298_1I20_GTS_TRI , B_Q_OUT_REG_6_1I13_GSR_OR , 
  B_Q_OUT_REG_7_1I13_GSR_OR , B_Q_OUT_REG_4_1I13_GSR_OR , 
  B_Q_OUT_REG_5_1I13_GSR_OR , B_Q_OUT_REG_2_1I13_GSR_OR , 
  B_Q_OUT_REG_3_1I13_GSR_OR , B_Q_OUT_REG_0_1I13_GSR_OR , 
  B_Q_OUT_REG_1_1I13_GSR_OR , C_Q_OUT_REG_6_1I13_GSR_OR , 
  C_Q_OUT_REG_7_1I13_GSR_OR , C_Q_OUT_REG_4_1I13_GSR_OR , 
  C_Q_OUT_REG_5_1I13_GSR_OR , C_Q_OUT_REG_2_1I13_GSR_OR , 
  C_Q_OUT_REG_3_1I13_GSR_OR , C_Q_OUT_REG_0_1I13_GSR_OR , 
  C_Q_OUT_REG_1_1I13_GSR_OR , U265_CLKIO_BUFSIG , 
  A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI_2_INV , A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI_2_INV 
  , A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI_2_INV , 
  A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI_2_INV , A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI_2_INV 
  , A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI_2_INV , 
  A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI_2_INV , A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI_2_INV 
  , U275_1I20_GTS_TRI_2_INV , U276_1I20_GTS_TRI_2_INV , U277_1I20_GTS_TRI_2_INV 
  , U278_1I20_GTS_TRI_2_INV , U279_1I20_GTS_TRI_2_INV , U280_1I20_GTS_TRI_2_INV 
  , U281_1I20_GTS_TRI_2_INV , U282_1I20_GTS_TRI_2_INV , U283_1I20_GTS_TRI_2_INV 
  , U284_1I20_GTS_TRI_2_INV , U285_1I20_GTS_TRI_2_INV , U286_1I20_GTS_TRI_2_INV 
  , U287_1I20_GTS_TRI_2_INV , U288_1I20_GTS_TRI_2_INV , U289_1I20_GTS_TRI_2_INV 
  , U290_1I20_GTS_TRI_2_INV , U291_1I20_GTS_TRI_2_INV , U292_1I20_GTS_TRI_2_INV 
  , U293_1I20_GTS_TRI_2_INV , U294_1I20_GTS_TRI_2_INV , U295_1I20_GTS_TRI_2_INV 
  , U296_1I20_GTS_TRI_2_INV , U297_1I20_GTS_TRI_2_INV , U298_1I20_GTS_TRI_2_INV 
  , GND , GSR , VCC , GTS : STD_LOGIC ;
  begin
    U264 : X_BUF 
      port map ( I => RESET , O => N232 ) ;
    U266 : X_BUF 
      port map ( I => ENABLE , O => N234 ) ;
    U267 : X_BUF 
      port map ( I => D_IN(7) , O => N235 ) ;
    U268 : X_BUF 
      port map ( I => D_IN(6) , O => N236 ) ;
    U269 : X_BUF 
      port map ( I => D_IN(5) , O => N237 ) ;
    U270 : X_BUF 
      port map ( I => D_IN(4) , O => N238 ) ;
    U271 : X_BUF 
      port map ( I => D_IN(3) , O => N239 ) ;
    U272 : X_BUF 
      port map ( I => D_IN(2) , O => N240 ) ;
    U273 : X_BUF 
      port map ( I => D_IN(1) , O => N241 ) ;
    U274 : X_BUF 
      port map ( I => D_IN(0) , O => N242 ) ;
    D_Q_OUT_REG_6_Q : X_FF 
      port map ( I => N236 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_6_GSR_OR , O => N464 ) ;
    D_Q_OUT_REG_7_Q : X_FF 
      port map ( I => N235 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_7_GSR_OR , O => N463 ) ;
    D_Q_OUT_REG_4_Q : X_FF 
      port map ( I => N238 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_4_GSR_OR , O => N466 ) ;
    D_Q_OUT_REG_5_Q : X_FF 
      port map ( I => N237 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_5_GSR_OR , O => N465 ) ;
    D_Q_OUT_REG_2_Q : X_FF 
      port map ( I => N240 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_2_GSR_OR , O => N468 ) ;
    D_Q_OUT_REG_3_Q : X_FF 
      port map ( I => N239 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_3_GSR_OR , O => N467 ) ;
    D_Q_OUT_REG_0_Q : X_FF 
      port map ( I => N242 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_0_GSR_OR , O => N470 ) ;
    D_Q_OUT_REG_1_Q : X_FF 
      port map ( I => N241 , CLK => N233 , CE => N234 , SET => GND , 
      RST => D_Q_OUT_REG_1_GSR_OR , O => N469 ) ;
    D_Q_OUT_REG_6_GSR_OR_0 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_6_GSR_OR ) ;
    D_Q_OUT_REG_7_GSR_OR_1 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_7_GSR_OR ) ;
    D_Q_OUT_REG_4_GSR_OR_2 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_4_GSR_OR ) ;
    D_Q_OUT_REG_5_GSR_OR_3 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_5_GSR_OR ) ;
    D_Q_OUT_REG_2_GSR_OR_4 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_2_GSR_OR ) ;
    D_Q_OUT_REG_3_GSR_OR_5 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_3_GSR_OR ) ;
    D_Q_OUT_REG_0_GSR_OR_6 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_0_GSR_OR ) ;
    D_Q_OUT_REG_1_GSR_OR_7 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => D_Q_OUT_REG_1_GSR_OR ) ;
    A_Q_OUT_REG_7_1I11_FF : X_FF 
      port map ( I => N235 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_7_1I11_QINT ) ;
    A_Q_OUT_REG_7_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_7_1I11_QINT , 
      O => A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI_8 : X_TRI 
      port map ( I => A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI , O => A_Q_OUT(7) , 
      CTL => A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_6_1I11_FF : X_FF 
      port map ( I => N236 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_6_1I11_QINT ) ;
    A_Q_OUT_REG_6_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_6_1I11_QINT , 
      O => A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI_9 : X_TRI 
      port map ( I => A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI , O => A_Q_OUT(6) , 
      CTL => A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_5_1I11_FF : X_FF 
      port map ( I => N237 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_5_1I11_QINT ) ;
    A_Q_OUT_REG_5_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_5_1I11_QINT , 
      O => A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI_10 : X_TRI 
      port map ( I => A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI , O => A_Q_OUT(5) , 
      CTL => A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_4_1I11_FF : X_FF 
      port map ( I => N238 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_4_1I11_QINT ) ;
    A_Q_OUT_REG_4_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_4_1I11_QINT , 
      O => A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI_11 : X_TRI 
      port map ( I => A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI , O => A_Q_OUT(4) , 
      CTL => A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_3_1I11_FF : X_FF 
      port map ( I => N239 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_3_1I11_QINT ) ;
    A_Q_OUT_REG_3_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_3_1I11_QINT , 
      O => A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI_12 : X_TRI 
      port map ( I => A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI , O => A_Q_OUT(3) , 
      CTL => A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_2_1I11_FF : X_FF 
      port map ( I => N240 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_2_1I11_QINT ) ;
    A_Q_OUT_REG_2_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_2_1I11_QINT , 
      O => A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI_13 : X_TRI 
      port map ( I => A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI , O => A_Q_OUT(2) , 
      CTL => A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_1_1I11_FF : X_FF 
      port map ( I => N241 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_1_1I11_QINT ) ;
    A_Q_OUT_REG_1_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_1_1I11_QINT , 
      O => A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI_14 : X_TRI 
      port map ( I => A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI , O => A_Q_OUT(1) , 
      CTL => A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_0_1I11_FF : X_FF 
      port map ( I => N242 , CLK => N233 , CE => VCC , SET => GND , RST => GSR 
      , O => A_Q_OUT_REG_0_1I11_QINT ) ;
    A_Q_OUT_REG_0_1I11_OBUF : X_BUF 
      port map ( I => A_Q_OUT_REG_0_1I11_QINT , 
      O => A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI ) ;
    A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI_15 : X_TRI 
      port map ( I => A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI , O => A_Q_OUT(0) , 
      CTL => A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    U275_1I20 : X_BUF 
      port map ( I => N447 , O => U275_1I20_GTS_TRI ) ;
    U275_1I20_GTS_TRI_16 : X_TRI 
      port map ( I => U275_1I20_GTS_TRI , O => B_Q_OUT(7) , 
      CTL => U275_1I20_GTS_TRI_2_INV ) ;
    U276_1I20 : X_BUF 
      port map ( I => N448 , O => U276_1I20_GTS_TRI ) ;
    U276_1I20_GTS_TRI_17 : X_TRI 
      port map ( I => U276_1I20_GTS_TRI , O => B_Q_OUT(6) , 
      CTL => U276_1I20_GTS_TRI_2_INV ) ;
    U277_1I20 : X_BUF 
      port map ( I => N449 , O => U277_1I20_GTS_TRI ) ;
    U277_1I20_GTS_TRI_18 : X_TRI 
      port map ( I => U277_1I20_GTS_TRI , O => B_Q_OUT(5) , 
      CTL => U277_1I20_GTS_TRI_2_INV ) ;
    U278_1I20 : X_BUF 
      port map ( I => N450 , O => U278_1I20_GTS_TRI ) ;
    U278_1I20_GTS_TRI_19 : X_TRI 
      port map ( I => U278_1I20_GTS_TRI , O => B_Q_OUT(4) , 
      CTL => U278_1I20_GTS_TRI_2_INV ) ;
    U279_1I20 : X_BUF 
      port map ( I => N451 , O => U279_1I20_GTS_TRI ) ;
    U279_1I20_GTS_TRI_20 : X_TRI 
      port map ( I => U279_1I20_GTS_TRI , O => B_Q_OUT(3) , 
      CTL => U279_1I20_GTS_TRI_2_INV ) ;
    U280_1I20 : X_BUF 
      port map ( I => N452 , O => U280_1I20_GTS_TRI ) ;
    U280_1I20_GTS_TRI_21 : X_TRI 
      port map ( I => U280_1I20_GTS_TRI , O => B_Q_OUT(2) , 
      CTL => U280_1I20_GTS_TRI_2_INV ) ;
    U281_1I20 : X_BUF 
      port map ( I => N453 , O => U281_1I20_GTS_TRI ) ;
    U281_1I20_GTS_TRI_22 : X_TRI 
      port map ( I => U281_1I20_GTS_TRI , O => B_Q_OUT(1) , 
      CTL => U281_1I20_GTS_TRI_2_INV ) ;
    U282_1I20 : X_BUF 
      port map ( I => N454 , O => U282_1I20_GTS_TRI ) ;
    U282_1I20_GTS_TRI_23 : X_TRI 
      port map ( I => U282_1I20_GTS_TRI , O => B_Q_OUT(0) , 
      CTL => U282_1I20_GTS_TRI_2_INV ) ;
    U283_1I20 : X_BUF 
      port map ( I => N455 , O => U283_1I20_GTS_TRI ) ;
    U283_1I20_GTS_TRI_24 : X_TRI 
      port map ( I => U283_1I20_GTS_TRI , O => C_Q_OUT(7) , 
      CTL => U283_1I20_GTS_TRI_2_INV ) ;
    U284_1I20 : X_BUF 
      port map ( I => N456 , O => U284_1I20_GTS_TRI ) ;
    U284_1I20_GTS_TRI_25 : X_TRI 
      port map ( I => U284_1I20_GTS_TRI , O => C_Q_OUT(6) , 
      CTL => U284_1I20_GTS_TRI_2_INV ) ;
    U285_1I20 : X_BUF 
      port map ( I => N457 , O => U285_1I20_GTS_TRI ) ;
    U285_1I20_GTS_TRI_26 : X_TRI 
      port map ( I => U285_1I20_GTS_TRI , O => C_Q_OUT(5) , 
      CTL => U285_1I20_GTS_TRI_2_INV ) ;
    U286_1I20 : X_BUF 
      port map ( I => N458 , O => U286_1I20_GTS_TRI ) ;
    U286_1I20_GTS_TRI_27 : X_TRI 
      port map ( I => U286_1I20_GTS_TRI , O => C_Q_OUT(4) , 
      CTL => U286_1I20_GTS_TRI_2_INV ) ;
    U287_1I20 : X_BUF 
      port map ( I => N459 , O => U287_1I20_GTS_TRI ) ;
    U287_1I20_GTS_TRI_28 : X_TRI 
      port map ( I => U287_1I20_GTS_TRI , O => C_Q_OUT(3) , 
      CTL => U287_1I20_GTS_TRI_2_INV ) ;
    U288_1I20 : X_BUF 
      port map ( I => N460 , O => U288_1I20_GTS_TRI ) ;
    U288_1I20_GTS_TRI_29 : X_TRI 
      port map ( I => U288_1I20_GTS_TRI , O => C_Q_OUT(2) , 
      CTL => U288_1I20_GTS_TRI_2_INV ) ;
    U289_1I20 : X_BUF 
      port map ( I => N461 , O => U289_1I20_GTS_TRI ) ;
    U289_1I20_GTS_TRI_30 : X_TRI 
      port map ( I => U289_1I20_GTS_TRI , O => C_Q_OUT(1) , 
      CTL => U289_1I20_GTS_TRI_2_INV ) ;
    U290_1I20 : X_BUF 
      port map ( I => N462 , O => U290_1I20_GTS_TRI ) ;
    U290_1I20_GTS_TRI_31 : X_TRI 
      port map ( I => U290_1I20_GTS_TRI , O => C_Q_OUT(0) , 
      CTL => U290_1I20_GTS_TRI_2_INV ) ;
    U291_1I20 : X_BUF 
      port map ( I => N463 , O => U291_1I20_GTS_TRI ) ;
    U291_1I20_GTS_TRI_32 : X_TRI 
      port map ( I => U291_1I20_GTS_TRI , O => D_Q_OUT(7) , 
      CTL => U291_1I20_GTS_TRI_2_INV ) ;
    U292_1I20 : X_BUF 
      port map ( I => N464 , O => U292_1I20_GTS_TRI ) ;
    U292_1I20_GTS_TRI_33 : X_TRI 
      port map ( I => U292_1I20_GTS_TRI , O => D_Q_OUT(6) , 
      CTL => U292_1I20_GTS_TRI_2_INV ) ;
    U293_1I20 : X_BUF 
      port map ( I => N465 , O => U293_1I20_GTS_TRI ) ;
    U293_1I20_GTS_TRI_34 : X_TRI 
      port map ( I => U293_1I20_GTS_TRI , O => D_Q_OUT(5) , 
      CTL => U293_1I20_GTS_TRI_2_INV ) ;
    U294_1I20 : X_BUF 
      port map ( I => N466 , O => U294_1I20_GTS_TRI ) ;
    U294_1I20_GTS_TRI_35 : X_TRI 
      port map ( I => U294_1I20_GTS_TRI , O => D_Q_OUT(4) , 
      CTL => U294_1I20_GTS_TRI_2_INV ) ;
    U295_1I20 : X_BUF 
      port map ( I => N467 , O => U295_1I20_GTS_TRI ) ;
    U295_1I20_GTS_TRI_36 : X_TRI 
      port map ( I => U295_1I20_GTS_TRI , O => D_Q_OUT(3) , 
      CTL => U295_1I20_GTS_TRI_2_INV ) ;
    U296_1I20 : X_BUF 
      port map ( I => N468 , O => U296_1I20_GTS_TRI ) ;
    U296_1I20_GTS_TRI_37 : X_TRI 
      port map ( I => U296_1I20_GTS_TRI , O => D_Q_OUT(2) , 
      CTL => U296_1I20_GTS_TRI_2_INV ) ;
    U297_1I20 : X_BUF 
      port map ( I => N469 , O => U297_1I20_GTS_TRI ) ;
    U297_1I20_GTS_TRI_38 : X_TRI 
      port map ( I => U297_1I20_GTS_TRI , O => D_Q_OUT(1) , 
      CTL => U297_1I20_GTS_TRI_2_INV ) ;
    U298_1I20 : X_BUF 
      port map ( I => N470 , O => U298_1I20_GTS_TRI ) ;
    U298_1I20_GTS_TRI_39 : X_TRI 
      port map ( I => U298_1I20_GTS_TRI , O => D_Q_OUT(0) , 
      CTL => U298_1I20_GTS_TRI_2_INV ) ;
    B_Q_OUT_REG_6_1I13 : X_FF 
      port map ( I => N236 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_6_1I13_GSR_OR , O => N448 ) ;
    B_Q_OUT_REG_6_1I13_GSR_OR_40 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_6_1I13_GSR_OR ) ;
    B_Q_OUT_REG_7_1I13 : X_FF 
      port map ( I => N235 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_7_1I13_GSR_OR , O => N447 ) ;
    B_Q_OUT_REG_7_1I13_GSR_OR_41 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_7_1I13_GSR_OR ) ;
    B_Q_OUT_REG_4_1I13 : X_FF 
      port map ( I => N238 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_4_1I13_GSR_OR , O => N450 ) ;
    B_Q_OUT_REG_4_1I13_GSR_OR_42 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_4_1I13_GSR_OR ) ;
    B_Q_OUT_REG_5_1I13 : X_FF 
      port map ( I => N237 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_5_1I13_GSR_OR , O => N449 ) ;
    B_Q_OUT_REG_5_1I13_GSR_OR_43 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_5_1I13_GSR_OR ) ;
    B_Q_OUT_REG_2_1I13 : X_FF 
      port map ( I => N240 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_2_1I13_GSR_OR , O => N452 ) ;
    B_Q_OUT_REG_2_1I13_GSR_OR_44 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_2_1I13_GSR_OR ) ;
    B_Q_OUT_REG_3_1I13 : X_FF 
      port map ( I => N239 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_3_1I13_GSR_OR , O => N451 ) ;
    B_Q_OUT_REG_3_1I13_GSR_OR_45 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_3_1I13_GSR_OR ) ;
    B_Q_OUT_REG_0_1I13 : X_FF 
      port map ( I => N242 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_0_1I13_GSR_OR , O => N454 ) ;
    B_Q_OUT_REG_0_1I13_GSR_OR_46 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_0_1I13_GSR_OR ) ;
    B_Q_OUT_REG_1_1I13 : X_FF 
      port map ( I => N241 , CLK => N233 , CE => VCC , SET => GND , 
      RST => B_Q_OUT_REG_1_1I13_GSR_OR , O => N453 ) ;
    B_Q_OUT_REG_1_1I13_GSR_OR_47 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => B_Q_OUT_REG_1_1I13_GSR_OR ) ;
    C_Q_OUT_REG_6_1I13 : X_FF 
      port map ( I => N236 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_6_1I13_GSR_OR , RST => GND , O => N456 ) ;
    C_Q_OUT_REG_6_1I13_GSR_OR_48 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_6_1I13_GSR_OR ) ;
    C_Q_OUT_REG_7_1I13 : X_FF 
      port map ( I => N235 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_7_1I13_GSR_OR , RST => GND , O => N455 ) ;
    C_Q_OUT_REG_7_1I13_GSR_OR_49 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_7_1I13_GSR_OR ) ;
    C_Q_OUT_REG_4_1I13 : X_FF 
      port map ( I => N238 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_4_1I13_GSR_OR , RST => GND , O => N458 ) ;
    C_Q_OUT_REG_4_1I13_GSR_OR_50 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_4_1I13_GSR_OR ) ;
    C_Q_OUT_REG_5_1I13 : X_FF 
      port map ( I => N237 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_5_1I13_GSR_OR , RST => GND , O => N457 ) ;
    C_Q_OUT_REG_5_1I13_GSR_OR_51 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_5_1I13_GSR_OR ) ;
    C_Q_OUT_REG_2_1I13 : X_FF 
      port map ( I => N240 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_2_1I13_GSR_OR , RST => GND , O => N460 ) ;
    C_Q_OUT_REG_2_1I13_GSR_OR_52 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_2_1I13_GSR_OR ) ;
    C_Q_OUT_REG_3_1I13 : X_FF 
      port map ( I => N239 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_3_1I13_GSR_OR , RST => GND , O => N459 ) ;
    C_Q_OUT_REG_3_1I13_GSR_OR_53 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_3_1I13_GSR_OR ) ;
    C_Q_OUT_REG_0_1I13 : X_FF 
      port map ( I => N242 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_0_1I13_GSR_OR , RST => GND , O => N462 ) ;
    C_Q_OUT_REG_0_1I13_GSR_OR_54 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_0_1I13_GSR_OR ) ;
    C_Q_OUT_REG_1_1I13 : X_FF 
      port map ( I => N241 , CLK => N233 , CE => VCC , 
      SET => C_Q_OUT_REG_1_1I13_GSR_OR , RST => GND , O => N461 ) ;
    C_Q_OUT_REG_1_1I13_GSR_OR_55 : X_OR2 
      port map ( I0 => N232 , I1 => GSR , O => C_Q_OUT_REG_1_1I13_GSR_OR ) ;
    U265_CLKBUF : X_CKBUF 
      port map ( I => U265_CLKIO_BUFSIG , O => N233 ) ;
    U265_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U265_CLKIO_BUFSIG ) ;
    A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI_2_INV_56 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_7_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI_2_INV_57 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_6_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI_2_INV_58 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_5_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI_2_INV_59 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_4_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI_2_INV_60 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_3_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI_2_INV_61 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_2_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI_2_INV_62 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_1_1I11_OBUF_GTS_TRI_2_INV ) ;
    A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI_2_INV_63 : X_INV 
      port map ( I => GTS , O => A_Q_OUT_REG_0_1I11_OBUF_GTS_TRI_2_INV ) ;
    U275_1I20_GTS_TRI_2_INV_64 : X_INV 
      port map ( I => GTS , O => U275_1I20_GTS_TRI_2_INV ) ;
    U276_1I20_GTS_TRI_2_INV_65 : X_INV 
      port map ( I => GTS , O => U276_1I20_GTS_TRI_2_INV ) ;
    U277_1I20_GTS_TRI_2_INV_66 : X_INV 
      port map ( I => GTS , O => U277_1I20_GTS_TRI_2_INV ) ;
    U278_1I20_GTS_TRI_2_INV_67 : X_INV 
      port map ( I => GTS , O => U278_1I20_GTS_TRI_2_INV ) ;
    U279_1I20_GTS_TRI_2_INV_68 : X_INV 
      port map ( I => GTS , O => U279_1I20_GTS_TRI_2_INV ) ;
    U280_1I20_GTS_TRI_2_INV_69 : X_INV 
      port map ( I => GTS , O => U280_1I20_GTS_TRI_2_INV ) ;
    U281_1I20_GTS_TRI_2_INV_70 : X_INV 
      port map ( I => GTS , O => U281_1I20_GTS_TRI_2_INV ) ;
    U282_1I20_GTS_TRI_2_INV_71 : X_INV 
      port map ( I => GTS , O => U282_1I20_GTS_TRI_2_INV ) ;
    U283_1I20_GTS_TRI_2_INV_72 : X_INV 
      port map ( I => GTS , O => U283_1I20_GTS_TRI_2_INV ) ;
    U284_1I20_GTS_TRI_2_INV_73 : X_INV 
      port map ( I => GTS , O => U284_1I20_GTS_TRI_2_INV ) ;
    U285_1I20_GTS_TRI_2_INV_74 : X_INV 
      port map ( I => GTS , O => U285_1I20_GTS_TRI_2_INV ) ;
    U286_1I20_GTS_TRI_2_INV_75 : X_INV 
      port map ( I => GTS , O => U286_1I20_GTS_TRI_2_INV ) ;
    U287_1I20_GTS_TRI_2_INV_76 : X_INV 
      port map ( I => GTS , O => U287_1I20_GTS_TRI_2_INV ) ;
    U288_1I20_GTS_TRI_2_INV_77 : X_INV 
      port map ( I => GTS , O => U288_1I20_GTS_TRI_2_INV ) ;
    U289_1I20_GTS_TRI_2_INV_78 : X_INV 
      port map ( I => GTS , O => U289_1I20_GTS_TRI_2_INV ) ;
    U290_1I20_GTS_TRI_2_INV_79 : X_INV 
      port map ( I => GTS , O => U290_1I20_GTS_TRI_2_INV ) ;
    U291_1I20_GTS_TRI_2_INV_80 : X_INV 
      port map ( I => GTS , O => U291_1I20_GTS_TRI_2_INV ) ;
    U292_1I20_GTS_TRI_2_INV_81 : X_INV 
      port map ( I => GTS , O => U292_1I20_GTS_TRI_2_INV ) ;
    U293_1I20_GTS_TRI_2_INV_82 : X_INV 
      port map ( I => GTS , O => U293_1I20_GTS_TRI_2_INV ) ;
    U294_1I20_GTS_TRI_2_INV_83 : X_INV 
      port map ( I => GTS , O => U294_1I20_GTS_TRI_2_INV ) ;
    U295_1I20_GTS_TRI_2_INV_84 : X_INV 
      port map ( I => GTS , O => U295_1I20_GTS_TRI_2_INV ) ;
    U296_1I20_GTS_TRI_2_INV_85 : X_INV 
      port map ( I => GTS , O => U296_1I20_GTS_TRI_2_INV ) ;
    U297_1I20_GTS_TRI_2_INV_86 : X_INV 
      port map ( I => GTS , O => U297_1I20_GTS_TRI_2_INV ) ;
    U298_1I20_GTS_TRI_2_INV_87 : X_INV 
      port map ( I => GTS , O => U298_1I20_GTS_TRI_2_INV ) ;
    VCC_88 : X_ONE 
      port map ( O => VCC ) ;
    GND_89 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

