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-- MUX_TBUF.VHD Version 1.0                    --
-- 5-to-1 Mux Implemented in 3-State Buffers   --
-- Xilinx HDL Synthesis Design Guide for FPGAs --
-- May 1997                                    --
-------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_tbuf is
port (	SEL: in STD_LOGIC_VECTOR (4 downto 0);
	A,B,C,D,E: in STD_LOGIC;
        SIG: out STD_LOGIC);
end mux_tbuf;

architecture RTL of mux_tbuf is
begin

    SIG <= A when (SEL(0)='0') else 'Z';
    SIG <= B when (SEL(1)='0') else 'Z';
    SIG <= C when (SEL(2)='0') else 'Z';
    SIG <= D when (SEL(3)='0') else 'Z';
    SIG <= E when (SEL(4)='0') else 'Z';

end RTL;
