-------------------------------------------------------
-- PRESET_5K.VHD Version 1.0                         --
-- Code describing an asynchronous set in a 5200     --
-- implemented by placing inverters on the input and --
-- output of FF since FFs only have async. resets    --
-- May 1997                                          --
-------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity preset_5k is
    port (CLK, DATA, PRESET: in STD_LOGIC;
	  Q: out STD_LOGIC);
end preset_5k;

architecture BEHAV of preset_5k is
begin
SET_FLOP: process (CLK, PRESET)
    begin
        if (PRESET='1') then
   	    Q <= '1';
        elsif (CLK'event and CLK='1') then
   	    Q <= DATA;
	end if;
    end process; -- End SET_FLOP
end BEHAV;
