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-- ROM_RTL.VHD Version 1.0           --
-- Xilinx HDL Synthesis Design Guide --
-- Behavioral 16x4 ROM Example       --
-- December 1997                     --
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library IEEE;
use IEEE.std_logic_1164.all;

entity rom_rtl is
     port (ADDR: in INTEGER range 0 to 15;
           DATA: out STD_LOGIC_VECTOR (3 downto 0));
end rom_rtl;

architecture XILINX of rom_rtl is

    subtype ROM_WORD is STD_LOGIC_VECTOR (3 downto 0);
    type ROM_TABLE is array (0 to 15) of ROM_WORD;
    constant ROM: ROM_TABLE := ROM_TABLE'(
        ROM_WORD'("0000"),
        ROM_WORD'("0001"),
        ROM_WORD'("0010"),
        ROM_WORD'("0100"),
        ROM_WORD'("1000"),
        ROM_WORD'("1100"),
        ROM_WORD'("1010"),
        ROM_WORD'("1001"),
        ROM_WORD'("1001"),
        ROM_WORD'("1010"),
        ROM_WORD'("1100"),
        ROM_WORD'("1001"),
        ROM_WORD'("1001"),
        ROM_WORD'("1101"),
        ROM_WORD'("1011"),
        ROM_WORD'("1111"));

    begin
        DATA <= ROM(ADDR);  -- Read from the ROM

end XILINX;
