-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 15:57:20 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity ONE_HOT is
  port (
    CLOCK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    E : in STD_LOGIC := 'X' ;
    SINGLE : out STD_LOGIC ;
    MULTI : out STD_LOGIC ;
    CONTIG : out STD_LOGIC 
  ) ;
end ONE_HOT ;

architecture STRUCTURE of ONE_HOT is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N85 , N86 , N87 , N88 , N89 , N90 , N91 , N180 , N181 , N182 , N144 , 
  N142 , N143 , N145 , N122 , N146 , N147 , N125 , N148 , N121 , N152 , N126 , 
  N151 , N150 , N149 , N153 , N155 , N154 , N156 , N163 , N160 , N162 , N157 , 
  N159 , N158 , N161 , N164 , N165 , N167 , N166 , N168 , N169 , N173 , N171 , 
  N170 , N172 , N174 , N179 , N178 , N175 , N176 , N177 , U108_1I20_GTS_TRI , 
  U109_1I20_GTS_TRI , U110_1I20_GTS_TRI , CS_REG_3_1I13_GSR_OR , 
  CS_REG_5_1I13_GSR_OR , CS_REG_2_1I13_GSR_OR , CS_REG_6_1I13_GSR_OR , 
  CS_REG_4_1I13_GSR_OR , CS_REG_1_1I13_GSR_OR , U101_CLKIO_BUFSIG , U111_2_0 , 
  U120_2_0 , U126_2_0 , U130_2_0 , U130_2_1 , U133_2_0 , U144_2_0 , U144_2_1 , 
  U152_2_0 , U152_2_1 , U154_2_0 , U154_2_1 , U112_2_INV , U114_2_INV , 
  U116_2_INV , U118_2_INV , U121_2_INV , U122_2_INV , U124_2_INV , U128_2_INV , 
  U131_2_INV , U132_2_INV , U134_2_INV , U137_2_INV , U140_2_INV , U142_2_INV , 
  U147_2_INV , U149_2_INV , U154_N121_2_INV , U108_1I20_GTS_TRI_2_INV , 
  U109_1I20_GTS_TRI_2_INV , U110_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS 
  : STD_LOGIC ;
  signal CS : STD_LOGIC_VECTOR ( 6 downto 1 );
  begin
    U102 : X_BUF 
      port map ( I => RESET , O => N86 ) ;
    U103 : X_BUF 
      port map ( I => A , O => N87 ) ;
    U104 : X_BUF 
      port map ( I => B , O => N88 ) ;
    U105 : X_BUF 
      port map ( I => C , O => N89 ) ;
    U106 : X_BUF 
      port map ( I => D , O => N90 ) ;
    U107 : X_BUF 
      port map ( I => E , O => N91 ) ;
    U112 : X_AND2 
      port map ( I0 => N142 , I1 => N145 , O => U112_2_INV ) ;
    U113 : X_INV 
      port map ( I => CS(4) , O => N142 ) ;
    U114 : X_AND2 
      port map ( I0 => N143 , I1 => N144 , O => U114_2_INV ) ;
    U115 : X_XOR2 
      port map ( I0 => CS(1) , I1 => CS(3) , O => N145 ) ;
    U116 : X_OR2 
      port map ( I0 => N180 , I1 => CS(6) , O => U116_2_INV ) ;
    U117 : X_INV 
      port map ( I => CS(3) , O => N146 ) ;
    U118 : X_OR2 
      port map ( I0 => N125 , I1 => N146 , O => U118_2_INV ) ;
    U119 : X_AND2 
      port map ( I0 => N125 , I1 => N121 , O => N148 ) ;
    U121 : X_AND2 
      port map ( I0 => N90 , I1 => CS(1) , O => U121_2_INV ) ;
    U122 : X_AND2 
      port map ( I0 => N149 , I1 => CS(2) , O => U122_2_INV ) ;
    U123 : X_OR2 
      port map ( I0 => N87 , I1 => N90 , O => N149 ) ;
    U124 : X_AND2 
      port map ( I0 => N150 , I1 => N151 , O => U124_2_INV ) ;
    U125 : X_INV 
      port map ( I => N89 , O => N153 ) ;
    U127 : X_INV 
      port map ( I => N154 , O => N155 ) ;
    U128 : X_AND2 
      port map ( I0 => N180 , I1 => N91 , O => U128_2_INV ) ;
    U129 : X_OR2 
      port map ( I0 => CS(4) , I1 => N155 , O => N156 ) ;
    U131 : X_AND2 
      port map ( I0 => N160 , I1 => N157 , O => U131_2_INV ) ;
    U132 : X_AND2 
      port map ( I0 => N159 , I1 => N158 , O => U132_2_INV ) ;
    U134 : X_AND2 
      port map ( I0 => N161 , I1 => N164 , O => U134_2_INV ) ;
    U135 : X_INV 
      port map ( I => CS(6) , O => N160 ) ;
    U136 : X_INV 
      port map ( I => N180 , O => N161 ) ;
    U137 : X_AND2 
      port map ( I0 => N162 , I1 => N163 , O => U137_2_INV ) ;
    U138 : X_XOR2 
      port map ( I0 => CS(2) , I1 => CS(3) , O => N164 ) ;
    U139 : X_INV 
      port map ( I => N87 , O => N165 ) ;
    U140 : X_OR2 
      port map ( I0 => CS(1) , I1 => N166 , O => U140_2_INV ) ;
    U141 : X_AND2 
      port map ( I0 => N165 , I1 => CS(2) , O => N166 ) ;
    U142 : X_OR2 
      port map ( I0 => N167 , I1 => N90 , O => U142_2_INV ) ;
    U143 : X_INV 
      port map ( I => N89 , O => N169 ) ;
    U145 : X_INV 
      port map ( I => N170 , O => N171 ) ;
    U146 : X_OR2 
      port map ( I0 => CS(6) , I1 => N180 , O => N170 ) ;
    U147 : X_OR2 
      port map ( I0 => N171 , I1 => N91 , O => U147_2_INV ) ;
    U148 : X_INV 
      port map ( I => N121 , O => N174 ) ;
    U149 : X_OR2 
      port map ( I0 => N178 , I1 => N174 , O => U149_2_INV ) ;
    U150 : X_INV 
      port map ( I => N89 , O => N175 ) ;
    U151 : X_INV 
      port map ( I => N87 , O => N176 ) ;
    U153 : X_INV 
      port map ( I => N122 , O => N177 ) ;
    U108_1I20 : X_BUF 
      port map ( I => N180 , O => U108_1I20_GTS_TRI ) ;
    U108_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U108_1I20_GTS_TRI , O => SINGLE , 
      CTL => U108_1I20_GTS_TRI_2_INV ) ;
    U109_1I20 : X_BUF 
      port map ( I => N181 , O => U109_1I20_GTS_TRI ) ;
    U109_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U109_1I20_GTS_TRI , O => MULTI , 
      CTL => U109_1I20_GTS_TRI_2_INV ) ;
    U110_1I20 : X_BUF 
      port map ( I => N182 , O => U110_1I20_GTS_TRI ) ;
    U110_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U110_1I20_GTS_TRI , O => CONTIG , 
      CTL => U110_1I20_GTS_TRI_2_INV ) ;
    CS_REG_3_1I13 : X_FF 
      port map ( I => N152 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_3_1I13_GSR_OR , O => CS(3) ) ;
    CS_REG_3_1I13_GSR_OR_3 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_3_1I13_GSR_OR ) ;
    CS_REG_5_1I13 : X_FF 
      port map ( I => N156 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_5_1I13_GSR_OR , O => N180 ) ;
    CS_REG_5_1I13_GSR_OR_4 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_5_1I13_GSR_OR ) ;
    CS_REG_2_1I13 : X_FF 
      port map ( I => N168 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_2_1I13_GSR_OR , O => CS(2) ) ;
    CS_REG_2_1I13_GSR_OR_5 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_2_1I13_GSR_OR ) ;
    CS_REG_6_1I13 : X_FF 
      port map ( I => N172 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_6_1I13_GSR_OR , O => CS(6) ) ;
    CS_REG_6_1I13_GSR_OR_6 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_6_1I13_GSR_OR ) ;
    CS_REG_4_1I13 : X_FF 
      port map ( I => N173 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_4_1I13_GSR_OR , O => CS(4) ) ;
    CS_REG_4_1I13_GSR_OR_7 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_4_1I13_GSR_OR ) ;
    CS_REG_1_1I13 : X_FF 
      port map ( I => N179 , CLK => N85 , CE => VCC , SET => GND , 
      RST => CS_REG_1_1I13_GSR_OR , O => CS(1) ) ;
    CS_REG_1_1I13_GSR_OR_8 : X_OR2 
      port map ( I0 => N86 , I1 => GSR , O => CS_REG_1_1I13_GSR_OR ) ;
    U101_CLKBUF : X_CKBUF 
      port map ( I => U101_CLKIO_BUFSIG , O => N85 ) ;
    U101_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U101_CLKIO_BUFSIG ) ;
    U111_N144_2_0 : X_OR2 
      port map ( I0 => CS(1) , I1 => CS(3) , O => U111_2_0 ) ;
    U111_N144 : X_OR2 
      port map ( I0 => U111_2_0 , I1 => N142 , O => N144 ) ;
    U120_N152_2_0 : X_OR2 
      port map ( I0 => N148 , I1 => N147 , O => U120_2_0 ) ;
    U120_N152 : X_OR2 
      port map ( I0 => U120_2_0 , I1 => N126 , O => N152 ) ;
    U126_N125_2_0 : X_AND2 
      port map ( I0 => N88 , I1 => N153 , O => U126_2_0 ) ;
    U126_N125 : X_AND2 
      port map ( I0 => U126_2_0 , I1 => N87 , O => N125 ) ;
    U130_N163_2_0 : X_OR2 
      port map ( I0 => CS(3) , I1 => N180 , O => U130_2_0 ) ;
    U130_N163_2_1 : X_OR2 
      port map ( I0 => CS(2) , I1 => N160 , O => U130_2_1 ) ;
    U130_N163 : X_OR2 
      port map ( I0 => U130_2_0 , I1 => U130_2_1 , O => N163 ) ;
    U133_N158_2_0 : X_OR2 
      port map ( I0 => CS(2) , I1 => CS(3) , O => U133_2_0 ) ;
    U133_N158 : X_OR2 
      port map ( I0 => U133_2_0 , I1 => N161 , O => N158 ) ;
    U144_N173_2_0 : X_AND2 
      port map ( I0 => N87 , I1 => N88 , O => U144_2_0 ) ;
    U144_N173_2_1 : X_AND2 
      port map ( I0 => CS(3) , I1 => N169 , O => U144_2_1 ) ;
    U144_N173 : X_AND2 
      port map ( I0 => U144_2_0 , I1 => U144_2_1 , O => N173 ) ;
    U152_N178_2_0 : X_OR2 
      port map ( I0 => N176 , I1 => N88 , O => U152_2_0 ) ;
    U152_N178_2_1 : X_OR2 
      port map ( I0 => N175 , I1 => CS(2) , O => U152_2_1 ) ;
    U152_N178 : X_OR2 
      port map ( I0 => U152_2_0 , I1 => U152_2_1 , O => N178 ) ;
    U154_N121_2_0 : X_OR2 
      port map ( I0 => CS(4) , I1 => CS(3) , O => U154_2_0 ) ;
    U154_N121_2_1 : X_OR2 
      port map ( I0 => CS(1) , I1 => N177 , O => U154_2_1 ) ;
    U154_N121 : X_OR2 
      port map ( I0 => U154_2_0 , I1 => U154_2_1 , O => U154_N121_2_INV ) ;
    U112_2_INV_9 : X_INV 
      port map ( I => U112_2_INV , O => N143 ) ;
    U114_2_INV_10 : X_INV 
      port map ( I => U114_2_INV , O => N181 ) ;
    U116_2_INV_11 : X_INV 
      port map ( I => U116_2_INV , O => N122 ) ;
    U118_2_INV_12 : X_INV 
      port map ( I => U118_2_INV , O => N147 ) ;
    U121_2_INV_13 : X_INV 
      port map ( I => U121_2_INV , O => N151 ) ;
    U122_2_INV_14 : X_INV 
      port map ( I => U122_2_INV , O => N150 ) ;
    U124_2_INV_15 : X_INV 
      port map ( I => U124_2_INV , O => N126 ) ;
    U128_2_INV_16 : X_INV 
      port map ( I => U128_2_INV , O => N154 ) ;
    U131_2_INV_17 : X_INV 
      port map ( I => U131_2_INV , O => N162 ) ;
    U132_2_INV_18 : X_INV 
      port map ( I => U132_2_INV , O => N157 ) ;
    U134_2_INV_19 : X_INV 
      port map ( I => U134_2_INV , O => N159 ) ;
    U137_2_INV_20 : X_INV 
      port map ( I => U137_2_INV , O => N182 ) ;
    U140_2_INV_21 : X_INV 
      port map ( I => U140_2_INV , O => N167 ) ;
    U142_2_INV_22 : X_INV 
      port map ( I => U142_2_INV , O => N168 ) ;
    U147_2_INV_23 : X_INV 
      port map ( I => U147_2_INV , O => N172 ) ;
    U149_2_INV_24 : X_INV 
      port map ( I => U149_2_INV , O => N179 ) ;
    U154_N121_2_INV_25 : X_INV 
      port map ( I => U154_N121_2_INV , O => N121 ) ;
    U108_1I20_GTS_TRI_2_INV_26 : X_INV 
      port map ( I => GTS , O => U108_1I20_GTS_TRI_2_INV ) ;
    U109_1I20_GTS_TRI_2_INV_27 : X_INV 
      port map ( I => GTS , O => U109_1I20_GTS_TRI_2_INV ) ;
    U110_1I20_GTS_TRI_2_INV_28 : X_INV 
      port map ( I => GTS , O => U110_1I20_GTS_TRI_2_INV ) ;
    VCC_29 : X_ONE 
      port map ( O => VCC ) ;
    GND_30 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

