-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:29:47 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity BND_SCAN is
  port (
    TDO_NET : out STD_LOGIC ;
    TDI_NET : in STD_LOGIC := 'X' ;
    TMS_NET : in STD_LOGIC := 'X' ;
    TCK_NET : in STD_LOGIC := 'X' ;
    LOAD_P : in STD_LOGIC := 'X' ;
    CE_P : in STD_LOGIC := 'X' ;
    CLOCK_P : in STD_LOGIC := 'X' ;
    RESET_P : in STD_LOGIC := 'X' ;
    DATA_P : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    COUT_P : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end BND_SCAN ;

architecture STRUCTURE of BND_SCAN is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal NET3 , NET4 , N8 , N9 , N10 , N11 , U6_N144 , U6_N148 , U6_N145 , 
  U6_N150 , U6_N220 , U6_N219 , U6_N218 , U6_N217 , U6_N187 , U6_N186 , U6_N185 
  , U6_N192 , U6_N191 , U6_N188 , U6_N190 , U6_N189 , U6_N195 , U6_N194 , 
  U6_N193 , U6_N200 , U6_N199 , U6_N196 , U6_N198 , U6_N197 , U6_N203 , U6_N202 
  , U6_N201 , U6_N208 , U6_N207 , U6_N204 , U6_N206 , U6_N205 , U6_N211 , 
  U6_N210 , U6_N209 , U6_N216 , U6_N215 , U6_N212 , U6_N214 , U6_N213 , 
  U6_ADD_31_PLUS_PLUS_N19 , U6_U79_1I20_GTS_TRI , U6_U80_1I20_GTS_TRI , 
  U6_U81_1I20_GTS_TRI , U6_U82_1I20_GTS_TRI , U6_QOUT_REG_0_1I13_GSR_OR , 
  U6_QOUT_REG_1_1I13_GSR_OR , U6_QOUT_REG_2_1I13_GSR_OR , 
  U6_QOUT_REG_3_1I13_GSR_OR , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_4 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , U26_CLKIO_BUFSIG , U6_U90_2_0 
  , U6_U98_2_0 , U6_U106_2_0 , U6_U114_2_0 , U6_U85_2_INV , U6_U93_2_INV , 
  U6_U101_2_INV , U6_U109_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_2_0_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_2_0_0_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_2_0_0_INV , 
  U6_U79_1I20_GTS_TRI_2_INV , U6_U80_1I20_GTS_TRI_2_INV , 
  U6_U81_1I20_GTS_TRI_2_INV , U6_U82_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS 
  : STD_LOGIC ;
  signal U6_ARG95 : STD_LOGIC_VECTOR ( 3 downto 0 );
  begin
    U24 : X_BUF 
      port map ( I => LOAD_P , O => N8 ) ;
    U25 : X_BUF 
      port map ( I => CE_P , O => N9 ) ;
    U27 : X_BUF 
      port map ( I => RESET_P , O => N11 ) ;
    U6_U75 : X_BUF 
      port map ( I => DATA_P(3) , O => U6_N144 ) ;
    U6_U76 : X_BUF 
      port map ( I => DATA_P(2) , O => U6_N148 ) ;
    U6_U77 : X_BUF 
      port map ( I => DATA_P(1) , O => U6_N145 ) ;
    U6_U78 : X_BUF 
      port map ( I => DATA_P(0) , O => U6_N150 ) ;
    U6_U83 : X_INV 
      port map ( I => U6_N186 , O => U6_N187 ) ;
    U6_U84 : X_INV 
      port map ( I => N9 , O => U6_N185 ) ;
    U6_U85 : X_AND2 
      port map ( I0 => U6_N185 , I1 => U6_N217 , O => U6_U85_2_INV ) ;
    U6_U86 : X_OR2 
      port map ( I0 => U6_N191 , I1 => U6_N187 , O => U6_N192 ) ;
    U6_U87 : X_INV 
      port map ( I => N8 , O => U6_N188 ) ;
    U6_U88 : X_OR2 
      port map ( I0 => U6_ARG95(0) , I1 => N8 , O => U6_N190 ) ;
    U6_U89 : X_OR2 
      port map ( I0 => U6_N188 , I1 => U6_N150 , O => U6_N189 ) ;
    U6_U91 : X_INV 
      port map ( I => U6_N194 , O => U6_N195 ) ;
    U6_U92 : X_INV 
      port map ( I => N9 , O => U6_N193 ) ;
    U6_U93 : X_AND2 
      port map ( I0 => U6_N193 , I1 => U6_N218 , O => U6_U93_2_INV ) ;
    U6_U94 : X_OR2 
      port map ( I0 => U6_N199 , I1 => U6_N195 , O => U6_N200 ) ;
    U6_U95 : X_INV 
      port map ( I => N8 , O => U6_N196 ) ;
    U6_U96 : X_OR2 
      port map ( I0 => U6_ARG95(1) , I1 => N8 , O => U6_N198 ) ;
    U6_U97 : X_OR2 
      port map ( I0 => U6_N196 , I1 => U6_N145 , O => U6_N197 ) ;
    U6_U99 : X_INV 
      port map ( I => U6_N202 , O => U6_N203 ) ;
    U6_U100 : X_INV 
      port map ( I => N9 , O => U6_N201 ) ;
    U6_U101 : X_AND2 
      port map ( I0 => U6_N201 , I1 => U6_N219 , O => U6_U101_2_INV ) ;
    U6_U102 : X_OR2 
      port map ( I0 => U6_N207 , I1 => U6_N203 , O => U6_N208 ) ;
    U6_U103 : X_INV 
      port map ( I => N8 , O => U6_N204 ) ;
    U6_U104 : X_OR2 
      port map ( I0 => U6_ARG95(2) , I1 => N8 , O => U6_N206 ) ;
    U6_U105 : X_OR2 
      port map ( I0 => U6_N204 , I1 => U6_N148 , O => U6_N205 ) ;
    U6_U107 : X_INV 
      port map ( I => U6_N210 , O => U6_N211 ) ;
    U6_U108 : X_INV 
      port map ( I => N9 , O => U6_N209 ) ;
    U6_U109 : X_AND2 
      port map ( I0 => U6_N209 , I1 => U6_N220 , O => U6_U109_2_INV ) ;
    U6_U110 : X_OR2 
      port map ( I0 => U6_N215 , I1 => U6_N211 , O => U6_N216 ) ;
    U6_U111 : X_INV 
      port map ( I => N8 , O => U6_N212 ) ;
    U6_U112 : X_OR2 
      port map ( I0 => U6_ARG95(3) , I1 => N8 , O => U6_N214 ) ;
    U6_U113 : X_OR2 
      port map ( I0 => U6_N212 , I1 => U6_N144 , O => U6_N213 ) ;
    NET3_ZERO : X_ZERO 
      port map ( O => NET3 ) ;
    NET4_ZERO : X_ZERO 
      port map ( O => NET4 ) ;
    U6_ADD_31_PLUS_PLUS_N19_ONE : X_ONE 
      port map ( O => U6_ADD_31_PLUS_PLUS_N19 ) ;
    U6_U79_1I20 : X_BUF 
      port map ( I => U6_N220 , O => U6_U79_1I20_GTS_TRI ) ;
    U6_U79_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U6_U79_1I20_GTS_TRI , O => COUT_P(3) , 
      CTL => U6_U79_1I20_GTS_TRI_2_INV ) ;
    U6_U80_1I20 : X_BUF 
      port map ( I => U6_N219 , O => U6_U80_1I20_GTS_TRI ) ;
    U6_U80_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U6_U80_1I20_GTS_TRI , O => COUT_P(2) , 
      CTL => U6_U80_1I20_GTS_TRI_2_INV ) ;
    U6_U81_1I20 : X_BUF 
      port map ( I => U6_N218 , O => U6_U81_1I20_GTS_TRI ) ;
    U6_U81_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U6_U81_1I20_GTS_TRI , O => COUT_P(1) , 
      CTL => U6_U81_1I20_GTS_TRI_2_INV ) ;
    U6_U82_1I20 : X_BUF 
      port map ( I => U6_N217 , O => U6_U82_1I20_GTS_TRI ) ;
    U6_U82_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U6_U82_1I20_GTS_TRI , O => COUT_P(0) , 
      CTL => U6_U82_1I20_GTS_TRI_2_INV ) ;
    U6_QOUT_REG_0_1I13 : X_FF 
      port map ( I => U6_N192 , CLK => N10 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_0_1I13_GSR_OR , O => U6_N217 ) ;
    U6_QOUT_REG_0_1I13_GSR_OR_4 : X_OR2 
      port map ( I0 => N11 , I1 => GSR , O => U6_QOUT_REG_0_1I13_GSR_OR ) ;
    U6_QOUT_REG_1_1I13 : X_FF 
      port map ( I => U6_N200 , CLK => N10 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_1_1I13_GSR_OR , O => U6_N218 ) ;
    U6_QOUT_REG_1_1I13_GSR_OR_5 : X_OR2 
      port map ( I0 => N11 , I1 => GSR , O => U6_QOUT_REG_1_1I13_GSR_OR ) ;
    U6_QOUT_REG_2_1I13 : X_FF 
      port map ( I => U6_N208 , CLK => N10 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_2_1I13_GSR_OR , O => U6_N219 ) ;
    U6_QOUT_REG_2_1I13_GSR_OR_6 : X_OR2 
      port map ( I0 => N11 , I1 => GSR , O => U6_QOUT_REG_2_1I13_GSR_OR ) ;
    U6_QOUT_REG_3_1I13 : X_FF 
      port map ( I => U6_N216 , CLK => N10 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_3_1I13_GSR_OR , O => U6_N220 ) ;
    U6_QOUT_REG_3_1I13_GSR_OR_7 : X_OR2 
      port map ( I0 => N11 , I1 => GSR , O => U6_QOUT_REG_3_1I13_GSR_OR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_INV1_F_SUM_0 : X_INV 
      port map ( I => U6_N217 , O => U6_ARG95(0) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_8 : X_AND3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_9 : X_AND3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C_10 : X_AND3 
      port map ( I0 => U6_N219 , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_11 : X_OR3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_12 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND_13 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      I1 => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_14 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND_15 : X_AND2 
      port map ( I0 => VCC , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR_16 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR_17 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
      I1 => U6_N219 , O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_18 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND_19 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_20 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND_21 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_22 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND_23 : X_AND2 
      port map ( I0 => VCC , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR_24 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR_25 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
      I1 => U6_N220 , O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND_26 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_27 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND_28 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_29 : X_AND2 
      port map ( I0 => U6_N220 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_4 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_30 : X_AND3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_31 : X_AND3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C_32 : X_AND3 
      port map ( I0 => U6_N217 , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT_33 : X_OR3 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
      I2 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_34 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND_35 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      I1 => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_36 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND_37 : X_AND2 
      port map ( I0 => VCC , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR_38 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR_39 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
      I1 => U6_N217 , O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_40 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND_41 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT_42 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND_43 : X_AND2 
      port map ( I0 => VCC , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_44 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND_45 : X_AND2 
      port map ( I0 => VCC , I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR_46 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR_47 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
      I1 => U6_N218 , O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND_48 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_49 : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND_50 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_51 : X_AND2 
      port map ( I0 => U6_N218 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C0BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C1BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C2BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C3BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C4BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C5BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C6BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C7BUF : X_BUF 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ZERO : X_ZERO 
      port map ( O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ONE : X_ONE 
      port map ( O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_2_0 : X_XOR2 
      port map ( 
      I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_2_0_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_Q : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
      I1 => U6_N220 , O => U6_ARG95(3) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_2_0 : X_XOR2 
      port map ( 
      I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_2_0_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_Q : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
      I1 => U6_N219 , O => U6_ARG95(2) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_2_0 : X_XOR2 
      port map ( 
      I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_2_0_0_INV , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_Q : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , 
      I1 => U6_N218 , O => U6_ARG95(1) ) ;
    U26_CLKBUF : X_CKBUF 
      port map ( I => U26_CLKIO_BUFSIG , O => N10 ) ;
    U26_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK_P , O => U26_CLKIO_BUFSIG ) ;
    U6_U90_U6_N191_2_0 : X_AND2 
      port map ( I0 => U6_N190 , I1 => U6_N189 , O => U6_U90_2_0 ) ;
    U6_U90_U6_N191 : X_AND2 
      port map ( I0 => U6_U90_2_0 , I1 => N9 , O => U6_N191 ) ;
    U6_U98_U6_N199_2_0 : X_AND2 
      port map ( I0 => U6_N198 , I1 => U6_N197 , O => U6_U98_2_0 ) ;
    U6_U98_U6_N199 : X_AND2 
      port map ( I0 => U6_U98_2_0 , I1 => N9 , O => U6_N199 ) ;
    U6_U106_U6_N207_2_0 : X_AND2 
      port map ( I0 => U6_N206 , I1 => U6_N205 , O => U6_U106_2_0 ) ;
    U6_U106_U6_N207 : X_AND2 
      port map ( I0 => U6_U106_2_0 , I1 => N9 , O => U6_N207 ) ;
    U6_U114_U6_N215_2_0 : X_AND2 
      port map ( I0 => U6_N214 , I1 => U6_N213 , O => U6_U114_2_0 ) ;
    U6_U114_U6_N215 : X_AND2 
      port map ( I0 => U6_U114_2_0 , I1 => N9 , O => U6_N215 ) ;
    U6_U85_2_INV_52 : X_INV 
      port map ( I => U6_U85_2_INV , O => U6_N186 ) ;
    U6_U93_2_INV_53 : X_INV 
      port map ( I => U6_U93_2_INV , O => U6_N194 ) ;
    U6_U101_2_INV_54 : X_INV 
      port map ( I => U6_U101_2_INV , O => U6_N202 ) ;
    U6_U109_2_INV_55 : X_INV 
      port map ( I => U6_U109_2_INV , O => U6_N210 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_56 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_57 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_58 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_59 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_60 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_61 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_62 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_63 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_64 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_65 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV_66 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV_67 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV_68 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV_69 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV_70 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV_71 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV_72 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV_73 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV_74 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV_75 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_2_0_0_INV_76 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_U6_ARG95_3_2_0_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_2_0_0_INV_77 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_U6_ARG95_2_2_0_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_2_0_0_INV_78 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_U6_ARG95_1_2_0_0_INV ) ;
    U6_U79_1I20_GTS_TRI_2_INV_79 : X_INV 
      port map ( I => GTS , O => U6_U79_1I20_GTS_TRI_2_INV ) ;
    U6_U80_1I20_GTS_TRI_2_INV_80 : X_INV 
      port map ( I => GTS , O => U6_U80_1I20_GTS_TRI_2_INV ) ;
    U6_U81_1I20_GTS_TRI_2_INV_81 : X_INV 
      port map ( I => GTS , O => U6_U81_1I20_GTS_TRI_2_INV ) ;
    U6_U82_1I20_GTS_TRI_2_INV_82 : X_INV 
      port map ( I => GTS , O => U6_U82_1I20_GTS_TRI_2_INV ) ;
    VCC_83 : X_ONE 
      port map ( O => VCC ) ;
    GND_84 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

