-------------------------------------------
-- LOGIBLOX_DP_RAM.VHD Version 1.0       --
-- Xilinx HDL Synthesis Design Guide     --
-- Example of instantiating a LogiBLOX   --
-- Duel Port RAM component               --
-- May 1997                              --
-------------------------------------------

------------------------------------------------------
-- LogiBLOX DP_RAM Module "lb_dp_ram"
-- Created by LogiBLOX version M1.3.7
--    on Wed Sep  3 07:59:50 1997
-- Attributes 
--    MODTYPE = DP_RAM
--    BUS_WIDTH = 4
--    DEPTH = 16
--    MEMFILE = lb_memfile
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

 
entity logiblox_dp_ram is

   port ( DATA_IN        : in  STD_LOGIC_VECTOR(3 downto 0);
          WRITE_ADDR     : in  STD_LOGIC_VECTOR(3 downto 0);
          READ_ADDR      : in  STD_LOGIC_VECTOR(3 downto 0);
          WE, CLOCK      : in  STD_LOGIC;
          DATA_OUT       : out STD_LOGIC_VECTOR(3 downto 0));

end logiblox_dp_ram;


architecture LOGIBLOX_RAM of logiblox_dp_ram is

----------------------------------------------------
-- Component Declaration 
----------------------------------------------------
component lb_dp_ram

  port(A: IN std_logic_vector(3 DOWNTO 0);
       DI: IN std_logic_vector(3 DOWNTO 0);
       WR_EN: IN std_logic;
       WR_CLK: IN std_logic;
       DPRA: IN std_logic_vector(3 DOWNTO 0);
       SPO: OUT std_logic_vector(3 DOWNTO 0);
       DPO: OUT std_logic_vector(3 DOWNTO 0));

end component;

begin

----------------------------------------------------
-- Component Instantiation 
----------------------------------------------------
DPRAM16X4 : lb_dp_ram port map (A => WRITE_ADDR,
               DI => DATA_IN, WR_EN => WE, 
               WR_CLK => CLOCK, DPRA => READ_ADDR,
               DPO => DATA_OUT);

end LOGIBLOX_RAM;
