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-- LogiBLOX SHIFT Module "shifter_16"
-- Created by LogiBLOX version M1.3.7
--    on Wed Aug 13 17:35:39 1997
-- Attributes 
--    MODTYPE = SHIFT
--    BUS_WIDTH = 16
--    ENCODING = UNSIGNED
--    OPTYPE = RIGHT
--    SHIFT_TYPE = LOGICAL
--    SYNC_VAL = 0
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;

ENTITY shifter_16 IS
  PORT(
    MS_IN: IN std_logic;
    SYNC_CTRL: IN std_logic;
    CLK_EN: IN std_logic;
    CLOCK: IN std_logic;
    Q_OUT: OUT std_logic_vector(15 DOWNTO 0));
END shifter_16;

ARCHITECTURE sim OF shifter_16 IS
    SIGNAL GSR: std_logic := '1';
BEGIN
  PROCESS
    VARIABLE VD_IN: std_logic_vector(15 DOWNTO 0);
    VARIABLE VLOAD: std_logic;
    VARIABLE VMS_IN: std_logic;
    VARIABLE VLS_IN: std_logic;
    VARIABLE VRIGHT_LEFT: std_logic;
    VARIABLE VASYNC_CTRL: std_logic;
    VARIABLE VSYNC_CTRL: std_logic;
    VARIABLE VCLK_EN: std_logic;
    VARIABLE VCLOCK: std_logic;
    VARIABLE VQ_OUT: std_logic_vector(15 DOWNTO 0);
    VARIABLE VLS_OUT: std_logic;
    VARIABLE VMS_OUT: std_logic;
    BEGIN
      VLOAD := '0';
      VMS_IN := stdbit2mvl(MS_IN);
      VRIGHT_LEFT := '1';
      VASYNC_CTRL := '0';
      VSYNC_CTRL := stdbit2mvl(SYNC_CTRL);
      VRIGHT_LEFT := '1';
      VLS_IN := '0';
      IF(
       (CLOCK'EVENT AND stdbit2mvl(CLOCK)='1' AND stdbit2mvl(CLOCK'LAST_VALUE)='0' AND stdbit2mvl(CLK_EN)='1')
       OR ( stdbit2mvl(GSR)='1')
      ) THEN
      xb_shift(
             GSR,
             VLS_IN,
             VMS_IN,
             VRIGHT_LEFT,
             VASYNC_CTRL,
             ('0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'),
             VSYNC_CTRL,
             ('0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0'),
             VLOAD,
             VD_IN,
             LOGICAL,
             VQ_OUT,
             VLS_OUT,
             VMS_OUT);
      Q_OUT <= VQ_OUT;
      ELSIF(
       (stdbit2mvl(CLOCK) = 'X')
       OR (CLOCK'EVENT AND stdbit2mvl(CLOCK)='1' AND stdbit2mvl(CLOCK'LAST_VALUE)='0'
           AND stdbit2mvl(CLK_EN) = 'X' )
      ) THEN
      VQ_OUT := ('X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X');
      Q_OUT <= VQ_OUT;
      END IF;
      IF (GSR='1') THEN
        GSR <= '0' AFTER 1 ns;
      END IF;
      WAIT ON MS_IN, SYNC_CTRL, CLK_EN, CLOCK, GSR;
  END PROCESS;
END sim;
