-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan 13 10:07:55 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity XOR_VAR is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    X : out STD_LOGIC ;
    Y : out STD_LOGIC 
  ) ;
end XOR_VAR ;

architecture STRUCTURE of XOR_VAR is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N20 , N21 , N22 , N45 , N46 , U34_1I20_GTS_TRI , U35_1I20_GTS_TRI , 
  U34_1I20_GTS_TRI_2_INV , U35_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U31 : X_BUF 
      port map ( I => A , O => N20 ) ;
    U32 : X_BUF 
      port map ( I => B , O => N21 ) ;
    U33 : X_BUF 
      port map ( I => C , O => N22 ) ;
    U36 : X_XOR2 
      port map ( I0 => N22 , I1 => N20 , O => N45 ) ;
    U37 : X_XOR2 
      port map ( I0 => N22 , I1 => N21 , O => N46 ) ;
    U34_1I20 : X_BUF 
      port map ( I => N45 , O => U34_1I20_GTS_TRI ) ;
    U34_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U34_1I20_GTS_TRI , O => X , CTL => U34_1I20_GTS_TRI_2_INV 
      ) ;
    U35_1I20 : X_BUF 
      port map ( I => N46 , O => U35_1I20_GTS_TRI ) ;
    U35_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U35_1I20_GTS_TRI , O => Y , CTL => U35_1I20_GTS_TRI_2_INV 
      ) ;
    U34_1I20_GTS_TRI_2_INV_2 : X_INV 
      port map ( I => GTS , O => U34_1I20_GTS_TRI_2_INV ) ;
    U35_1I20_GTS_TRI_2_INV_3 : X_INV 
      port map ( I => GTS , O => U35_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

