--------------------------------------------
-- D_LATCH.VHD Version 1.0                --
-- Example of a behavioral description of --
-- a transparent latch.                   --
-- HDL Synthesis Design Guide for FPGAs   --
-- May 1997                               --
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity d_latch is
    port (GATE, DATA: in STD_LOGIC;
	  Q: out STD_LOGIC);
end d_latch;

architecture BEHAV of d_latch is
begin
LATCH: process (GATE, DATA)
    begin
	if (GATE = '1') then
	    Q <= DATA;
        end if;
    end process; -- end LATCH

end BEHAV;
