------------------------------------------
-- OMUX_EXAMPLE.VHD Version 1.0         --
-- Example of OMUX instantiation        --
-- For an XC4000EX/XL/XV device         --
-- HDL Synthesis Design Guide for FPGAs --
-- August 1997                          --
------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
 
entity  omux_example is

    port (DATA_IN: in STD_LOGIC_VECTOR (1 downto 0);
          SEL: in STD_LOGIC;
          DATA_OUT: out STD_LOGIC);

end omux_example;
 
architecture XILINX of omux_example is

    component OMUX2
        port (D0, D1, S0 : in  STD_LOGIC;
              O :          out STD_LOGIC);
    end component;

begin

     DUEL_OUT: OMUX2 port map (O=>DATA_OUT, D0=>DATA_IN(0), 
                               D1=>DATA_IN(1), S0=>SEL);

end XILINX;
