----------------------------------------------
-- IF_EX.VHD Version 1.0                    --
-- Example of a If statement showing a      --
-- mux created using priority encoded logic --
-- HDL Synthesis Design Guide for FPGAs     --
-- May 1997                                 --
----------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity if_ex is
    port (SEL: in STD_LOGIC_VECTOR(1 downto 0);
	  A,B,C,D: in STD_LOGIC;
	  MUX_OUT: out STD_LOGIC);
end if_ex;

architecture BEHAV of if_ex is
begin

    IF_PRO: process (SEL,A,B,C,D) 
    begin
        if    (SEL="00") then	MUX_OUT <= A;
	elsif (SEL="01") then 	MUX_OUT <= B;
	elsif (SEL="10") then 	MUX_OUT <= C;
	elsif (SEL="11") then 	MUX_OUT <= D;
	else 		 	MUX_OUT <= '0';
    end if;
end process; --END IF_PRO

end BEHAV;
