--------------------------------------------
-- D_REGISTER.VHD Version 1.0             --
-- Example of a behavioral description of --
-- a D register.                          --
-- HDL Synthesis Design Guide for FPGAs   --
-- May 1997                               --
--------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity d_register is
    port (CLK, DATA: in STD_LOGIC;
	  Q: out STD_LOGIC);
end d_register;

architecture BEHAV of d_register is
begin
My_D_Reg: process (CLK, DATA)
    begin
        if (CLK'event and CLK='1') then
   	    Q <= DATA;
	end if;
    end process; -- End My_D_Reg
end BEHAV;
