------------------------------------------------
-- USE_GR.VHD Version 1.0                     --
-- Xilinx HDL Synthesis Design Guide          --
-- The signal RESET initializes all registers --
-- Using the global reset resources since     --
-- STARTBUF block was added                   --
-- December 1997                              --
------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity use_gr is
port ( CLOCK: in STD_LOGIC;
       RESET: in STD_LOGIC;
       UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
       DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end use_gr;

architecture XILINX of use_gr is

component STARTBUF
    port (GSRIN:  in  STD_LOGIC;
          GSROUT: out STD_LOGIC);
end component;

signal RESET_INT: STD_LOGIC;
signal UP_CNT:    STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT:    STD_LOGIC_VECTOR (3 downto 0);

begin

    U1: STARTBUF port map(GSRIN=>RESET, GSROUT=>RESET_INT);

    UP_COUNTER: process(CLOCK, RESET_INT)
    begin
        if (RESET_INT = '1') then
            UP_CNT <= "0000";
        elsif (CLOCK'event and CLOCK = '1') then
            UP_CNT <= UP_CNT + 1;
        end if;
    end process;
 
    DN_COUNTER: process(CLOCK, RESET_INT) 
    begin
        if (RESET_INT = '1') then
            DN_CNT <= "1111";
        elsif (CLOCK'event and CLOCK = '1') then
            DN_CNT <= DN_CNT - 1;
        end if;
    end process;
 
    UPCNT <= UP_CNT;
    DNCNT <= DN_CNT;

end XILINX;
