-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:26:52 1998
-- Design file: time_sim.nga
-- Device: 5202pc84-4
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity BND_SCAN is
  port (
    RESET_P : in STD_LOGIC := 'X' ;
    CLOCK_P : in STD_LOGIC := 'X' ;
    CE_P : in STD_LOGIC := 'X' ;
    LOAD_P : in STD_LOGIC := 'X' ;
    COUT_P : out  STD_LOGIC_VECTOR ( 3 downto 0 );
    DATA_P : in  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end BND_SCAN ;

architecture STRUCTURE of BND_SCAN is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal TDO_NET , TDI_NET , TMS_NET , TCK_NET , NET3 , NET4 , N8 , N7 , N6 , 
  N5 , U6_N157 , U6_N158 , U6_N159 , U6_N160 , U6_N142 , U6_N137 , U6_N140 , 
  U6_N136 , U6_N152 , U6_N153 , U6_N154 , U6_N155 , U6_ADD_31_PLUS_PLUS_N19 , 
  U6_U42_1I20_GTS_TRI , U6_U43_1I20_GTS_TRI , U6_U44_1I20_GTS_TRI , 
  U6_U45_1I20_GTS_TRI , U6_U50_AND0 , U6_U50_AND1 , U6_U51_AND0 , U6_U52_AND0 , 
  U6_U52_AND1 , U6_U53_AND0 , U6_U54_AND0 , U6_U54_AND1 , U6_U55_AND0 , 
  U6_U56_AND0 , U6_U56_AND1 , U6_U57_AND0 , U6_QOUT_REG_3_1I13_GR_OR , 
  U6_QOUT_REG_2_1I13_GR_OR , U6_QOUT_REG_1_1I13_GR_OR , 
  U6_QOUT_REG_0_1I13_GR_OR , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_3 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , U6_ADD_31_PLUS_PLUS_U6_GND , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 , U15_CLKIO_BUFSIG , 
  U6_U50_AND0_0_INV , U6_U50_AND1_0_INV , U6_U52_AND0_0_INV , U6_U52_AND1_0_INV 
  , U6_U54_AND0_0_INV , U6_U54_AND1_0_INV , U6_U56_AND0_0_INV , 
  U6_U56_AND1_0_INV , U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV , 
  U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV , U6_U42_1I20_GTS_TRI_2_INV 
  , U6_U43_1I20_GTS_TRI_2_INV , U6_U44_1I20_GTS_TRI_2_INV , 
  U6_U45_1I20_GTS_TRI_2_INV , GND , GR , VCC , GTS : STD_LOGIC ;
  signal U6_ARG95 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal U6_QOUT47 : STD_LOGIC_VECTOR ( 3 downto 0 );
  begin
    U14 : X_BUF 
      port map ( I => RESET_P , O => N8 ) ;
    U16 : X_BUF 
      port map ( I => CE_P , O => N6 ) ;
    U17 : X_BUF 
      port map ( I => LOAD_P , O => N5 ) ;
    U6_U46 : X_BUF 
      port map ( I => DATA_P(0) , O => U6_N142 ) ;
    U6_U47 : X_BUF 
      port map ( I => DATA_P(1) , O => U6_N137 ) ;
    U6_U48 : X_BUF 
      port map ( I => DATA_P(2) , O => U6_N140 ) ;
    U6_U49 : X_BUF 
      port map ( I => DATA_P(3) , O => U6_N136 ) ;
    NET3_ZERO : X_ZERO 
      port map ( O => NET3 ) ;
    NET4_ZERO : X_ZERO 
      port map ( O => NET4 ) ;
    U6_ADD_31_PLUS_PLUS_N19_ONE : X_ONE 
      port map ( O => U6_ADD_31_PLUS_PLUS_N19 ) ;
    U6_U42_1I20 : X_BUF 
      port map ( I => U6_N157 , O => U6_U42_1I20_GTS_TRI ) ;
    U6_U42_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U6_U42_1I20_GTS_TRI , O => COUT_P(0) , 
      CTL => U6_U42_1I20_GTS_TRI_2_INV ) ;
    U6_U43_1I20 : X_BUF 
      port map ( I => U6_N158 , O => U6_U43_1I20_GTS_TRI ) ;
    U6_U43_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U6_U43_1I20_GTS_TRI , O => COUT_P(1) , 
      CTL => U6_U43_1I20_GTS_TRI_2_INV ) ;
    U6_U44_1I20 : X_BUF 
      port map ( I => U6_N159 , O => U6_U44_1I20_GTS_TRI ) ;
    U6_U44_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U6_U44_1I20_GTS_TRI , O => COUT_P(2) , 
      CTL => U6_U44_1I20_GTS_TRI_2_INV ) ;
    U6_U45_1I20 : X_BUF 
      port map ( I => U6_N160 , O => U6_U45_1I20_GTS_TRI ) ;
    U6_U45_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U6_U45_1I20_GTS_TRI , O => COUT_P(3) , 
      CTL => U6_U45_1I20_GTS_TRI_2_INV ) ;
    U6_U50_AND0_4 : X_AND3 
      port map ( I0 => U6_U50_AND0_0_INV , I1 => N6 , I2 => U6_ARG95(3) , 
      O => U6_U50_AND0 ) ;
    U6_U50_AND1_5 : X_AND2 
      port map ( I0 => U6_U50_AND1_0_INV , I1 => U6_N160 , O => U6_U50_AND1 ) ;
    U6_U50_OR2 : X_OR2 
      port map ( I0 => U6_U50_AND0 , I1 => U6_U50_AND1 , O => U6_N152 ) ;
    U6_U51_AND0_6 : X_AND3 
      port map ( I0 => N5 , I1 => N6 , I2 => U6_N136 , O => U6_U51_AND0 ) ;
    U6_U51_OR1 : X_OR2 
      port map ( I0 => U6_U51_AND0 , I1 => U6_N152 , O => U6_QOUT47(3) ) ;
    U6_U52_AND0_7 : X_AND3 
      port map ( I0 => U6_U52_AND0_0_INV , I1 => N6 , I2 => U6_ARG95(2) , 
      O => U6_U52_AND0 ) ;
    U6_U52_AND1_8 : X_AND2 
      port map ( I0 => U6_U52_AND1_0_INV , I1 => U6_N159 , O => U6_U52_AND1 ) ;
    U6_U52_OR2 : X_OR2 
      port map ( I0 => U6_U52_AND0 , I1 => U6_U52_AND1 , O => U6_N153 ) ;
    U6_U53_AND0_9 : X_AND3 
      port map ( I0 => N5 , I1 => N6 , I2 => U6_N140 , O => U6_U53_AND0 ) ;
    U6_U53_OR1 : X_OR2 
      port map ( I0 => U6_U53_AND0 , I1 => U6_N153 , O => U6_QOUT47(2) ) ;
    U6_U54_AND0_10 : X_AND3 
      port map ( I0 => U6_U54_AND0_0_INV , I1 => N6 , I2 => U6_ARG95(1) , 
      O => U6_U54_AND0 ) ;
    U6_U54_AND1_11 : X_AND2 
      port map ( I0 => U6_U54_AND1_0_INV , I1 => U6_N158 , O => U6_U54_AND1 ) ;
    U6_U54_OR2 : X_OR2 
      port map ( I0 => U6_U54_AND0 , I1 => U6_U54_AND1 , O => U6_N154 ) ;
    U6_U55_AND0_12 : X_AND3 
      port map ( I0 => N5 , I1 => N6 , I2 => U6_N137 , O => U6_U55_AND0 ) ;
    U6_U55_OR1 : X_OR2 
      port map ( I0 => U6_U55_AND0 , I1 => U6_N154 , O => U6_QOUT47(1) ) ;
    U6_U56_AND0_13 : X_AND3 
      port map ( I0 => U6_U56_AND0_0_INV , I1 => N6 , I2 => U6_ARG95(0) , 
      O => U6_U56_AND0 ) ;
    U6_U56_AND1_14 : X_AND2 
      port map ( I0 => U6_U56_AND1_0_INV , I1 => U6_N157 , O => U6_U56_AND1 ) ;
    U6_U56_OR2 : X_OR2 
      port map ( I0 => U6_U56_AND0 , I1 => U6_U56_AND1 , O => U6_N155 ) ;
    U6_U57_AND0_15 : X_AND3 
      port map ( I0 => N5 , I1 => N6 , I2 => U6_N142 , O => U6_U57_AND0 ) ;
    U6_U57_OR1 : X_OR2 
      port map ( I0 => U6_U57_AND0 , I1 => U6_N155 , O => U6_QOUT47(0) ) ;
    U6_QOUT_REG_3_1I13 : X_FF 
      port map ( I => U6_QOUT47(3) , CLK => N7 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_3_1I13_GR_OR , O => U6_N160 ) ;
    U6_QOUT_REG_3_1I13_GR_OR_16 : X_OR2 
      port map ( I0 => N8 , I1 => GR , O => U6_QOUT_REG_3_1I13_GR_OR ) ;
    U6_QOUT_REG_2_1I13 : X_FF 
      port map ( I => U6_QOUT47(2) , CLK => N7 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_2_1I13_GR_OR , O => U6_N159 ) ;
    U6_QOUT_REG_2_1I13_GR_OR_17 : X_OR2 
      port map ( I0 => N8 , I1 => GR , O => U6_QOUT_REG_2_1I13_GR_OR ) ;
    U6_QOUT_REG_1_1I13 : X_FF 
      port map ( I => U6_QOUT47(1) , CLK => N7 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_1_1I13_GR_OR , O => U6_N158 ) ;
    U6_QOUT_REG_1_1I13_GR_OR_18 : X_OR2 
      port map ( I0 => N8 , I1 => GR , O => U6_QOUT_REG_1_1I13_GR_OR ) ;
    U6_QOUT_REG_0_1I13 : X_FF 
      port map ( I => U6_QOUT47(0) , CLK => N7 , CE => VCC , SET => GND , 
      RST => U6_QOUT_REG_0_1I13_GR_OR , O => U6_N157 ) ;
    U6_QOUT_REG_0_1I13_GR_OR_19 : X_OR2 
      port map ( I0 => N8 , I1 => GR , O => U6_QOUT_REG_0_1I13_GR_OR ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR8_SUM_1_3 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_3 , O => U6_ARG95(3) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3 : X_XOR2 
      port map ( I0 => U6_N160 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_3 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR6_SUM_1_2 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , O => U6_ARG95(2) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2 : X_XOR2 
      port map ( I0 => U6_N159 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR4_SUM_1_1 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , O => U6_ARG95(1) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1 : X_XOR2 
      port map ( I0 => U6_N158 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR2_SUM_1_0 : X_XOR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , O => U6_ARG95(0) ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0 : X_XOR2 
      port map ( I0 => U6_N157 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_GND_ZERO : X_ZERO 
      port map ( O => U6_ADD_31_PLUS_PLUS_U6_GND ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_20 : X_AND2 
      port map ( I0 => U6_N159 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1_21 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_OR : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_22 : X_AND2 
      port map ( I0 => U6_N158 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1_23 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_OR : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_24 : X_AND2 
      port map ( I0 => U6_N157 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1_25 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_OR : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_26 : X_AND2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_N19 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1_27 : X_AND2 
      port map ( I0 => VCC , I1 => U6_ADD_31_PLUS_PLUS_U6_GND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_OR : X_OR2 
      port map ( I0 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0 , 
      I1 => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CO_0 ) ;
    U15_CLKBUF : X_CKBUF 
      port map ( I => U15_CLKIO_BUFSIG , O => N7 ) ;
    U15_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK_P , O => U15_CLKIO_BUFSIG ) ;
    U6_U50_AND0_0_INV_28 : X_INV 
      port map ( I => N5 , O => U6_U50_AND0_0_INV ) ;
    U6_U50_AND1_0_INV_29 : X_INV 
      port map ( I => N6 , O => U6_U50_AND1_0_INV ) ;
    U6_U52_AND0_0_INV_30 : X_INV 
      port map ( I => N5 , O => U6_U52_AND0_0_INV ) ;
    U6_U52_AND1_0_INV_31 : X_INV 
      port map ( I => N6 , O => U6_U52_AND1_0_INV ) ;
    U6_U54_AND0_0_INV_32 : X_INV 
      port map ( I => N5 , O => U6_U54_AND0_0_INV ) ;
    U6_U54_AND1_0_INV_33 : X_INV 
      port map ( I => N6 , O => U6_U54_AND1_0_INV ) ;
    U6_U56_AND0_0_INV_34 : X_INV 
      port map ( I => N5 , O => U6_U56_AND0_0_INV ) ;
    U6_U56_AND1_0_INV_35 : X_INV 
      port map ( I => N6 , O => U6_U56_AND1_0_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV_36 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR7_MUX_SEL_1_3_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV_37 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR5_MUX_SEL_1_2_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV_38 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR3_MUX_SEL_1_1_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV_39 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_N19 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_XOR1_MUX_SEL_1_0_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV_40 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_2 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_2_AND0_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV_41 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_1 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_1_AND0_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV_42 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_S0_1_MUX_SEL_1_0 , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_1_0_AND0_1_INV ) ;
    U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV_43 : X_INV 
      port map ( I => U6_ADD_31_PLUS_PLUS_U6_GND , 
      O => U6_ADD_31_PLUS_PLUS_U6_S0_1_CY_MUX_0_3_AND0_1_INV ) ;
    U6_U42_1I20_GTS_TRI_2_INV_44 : X_INV 
      port map ( I => GTS , O => U6_U42_1I20_GTS_TRI_2_INV ) ;
    U6_U43_1I20_GTS_TRI_2_INV_45 : X_INV 
      port map ( I => GTS , O => U6_U43_1I20_GTS_TRI_2_INV ) ;
    U6_U44_1I20_GTS_TRI_2_INV_46 : X_INV 
      port map ( I => GTS , O => U6_U44_1I20_GTS_TRI_2_INV ) ;
    U6_U45_1I20_GTS_TRI_2_INV_47 : X_INV 
      port map ( I => GTS , O => U6_U45_1I20_GTS_TRI_2_INV ) ;
    VCC_48 : X_ONE 
      port map ( O => VCC ) ;
    GND_49 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

