-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:54:22 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity NO_GSR is
  port (
    CLOCK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    UPCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 );
    DNCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end NO_GSR ;

architecture STRUCTURE of NO_GSR is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N197 , N198 , N254 , N255 , N256 , N257 , N258 , N259 , N260 , N261 , 
  ADD_31_PLUS_PLUS_N19 , SUB_40_MINUS_MINUS_N20 , U93_1I20_GTS_TRI , 
  U94_1I20_GTS_TRI , U95_1I20_GTS_TRI , U96_1I20_GTS_TRI , U97_1I20_GTS_TRI , 
  U98_1I20_GTS_TRI , U99_1I20_GTS_TRI , U100_1I20_GTS_TRI , 
  UP_CNT_REG_2_1I13_GSR_OR , UP_CNT_REG_3_1I13_GSR_OR , 
  UP_CNT_REG_0_1I13_GSR_OR , UP_CNT_REG_1_1I13_GSR_OR , 
  DN_CNT_REG_2_1I13_GSR_OR , DN_CNT_REG_3_1I13_GSR_OR , 
  DN_CNT_REG_0_1I13_GSR_OR , DN_CNT_REG_1_1I13_GSR_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CO_4 , ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , SUB_40_MINUS_MINUS_U6_S0_1_CO_4 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 , U91_CLKIO_BUFSIG , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV , 
  ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
  SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV , 
  U93_1I20_GTS_TRI_2_INV , U94_1I20_GTS_TRI_2_INV , U95_1I20_GTS_TRI_2_INV , 
  U96_1I20_GTS_TRI_2_INV , U97_1I20_GTS_TRI_2_INV , U98_1I20_GTS_TRI_2_INV , 
  U99_1I20_GTS_TRI_2_INV , U100_1I20_GTS_TRI_2_INV , GND , GSR , VCC , GTS 
  : STD_LOGIC ;
  signal ARG58 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal ARG139 : STD_LOGIC_VECTOR ( 3 downto 0 );
  begin
    U92 : X_BUF 
      port map ( I => RESET , O => N198 ) ;
    ADD_31_PLUS_PLUS_N19_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_N19 ) ;
    SUB_40_MINUS_MINUS_N20_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_N20 ) ;
    U93_1I20 : X_BUF 
      port map ( I => N254 , O => U93_1I20_GTS_TRI ) ;
    U93_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U93_1I20_GTS_TRI , O => UPCNT(3) , 
      CTL => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20 : X_BUF 
      port map ( I => N255 , O => U94_1I20_GTS_TRI ) ;
    U94_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U94_1I20_GTS_TRI , O => UPCNT(2) , 
      CTL => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20 : X_BUF 
      port map ( I => N256 , O => U95_1I20_GTS_TRI ) ;
    U95_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U95_1I20_GTS_TRI , O => UPCNT(1) , 
      CTL => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20 : X_BUF 
      port map ( I => N257 , O => U96_1I20_GTS_TRI ) ;
    U96_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U96_1I20_GTS_TRI , O => UPCNT(0) , 
      CTL => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20 : X_BUF 
      port map ( I => N258 , O => U97_1I20_GTS_TRI ) ;
    U97_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U97_1I20_GTS_TRI , O => DNCNT(3) , 
      CTL => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20 : X_BUF 
      port map ( I => N259 , O => U98_1I20_GTS_TRI ) ;
    U98_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U98_1I20_GTS_TRI , O => DNCNT(2) , 
      CTL => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20 : X_BUF 
      port map ( I => N260 , O => U99_1I20_GTS_TRI ) ;
    U99_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U99_1I20_GTS_TRI , O => DNCNT(1) , 
      CTL => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20 : X_BUF 
      port map ( I => N261 , O => U100_1I20_GTS_TRI ) ;
    U100_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U100_1I20_GTS_TRI , O => DNCNT(0) , 
      CTL => U100_1I20_GTS_TRI_2_INV ) ;
    UP_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG58(2) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_2_1I13_GSR_OR , O => N255 ) ;
    UP_CNT_REG_2_1I13_GSR_OR_8 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_2_1I13_GSR_OR ) ;
    UP_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG58(3) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_3_1I13_GSR_OR , O => N254 ) ;
    UP_CNT_REG_3_1I13_GSR_OR_9 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_3_1I13_GSR_OR ) ;
    UP_CNT_REG_0_1I13 : X_FF 
      port map ( I => ARG58(0) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_0_1I13_GSR_OR , O => N257 ) ;
    UP_CNT_REG_0_1I13_GSR_OR_10 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_0_1I13_GSR_OR ) ;
    UP_CNT_REG_1_1I13 : X_FF 
      port map ( I => ARG58(1) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_1_1I13_GSR_OR , O => N256 ) ;
    UP_CNT_REG_1_1I13_GSR_OR_11 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => UP_CNT_REG_1_1I13_GSR_OR ) ;
    DN_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG139(2) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_2_1I13_GSR_OR , RST => GND , O => N259 ) ;
    DN_CNT_REG_2_1I13_GSR_OR_12 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_2_1I13_GSR_OR ) ;
    DN_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG139(3) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_3_1I13_GSR_OR , RST => GND , O => N258 ) ;
    DN_CNT_REG_3_1I13_GSR_OR_13 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_3_1I13_GSR_OR ) ;
    DN_CNT_REG_0_1I13 : X_FF 
      port map ( I => ARG139(0) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_0_1I13_GSR_OR , RST => GND , O => N261 ) ;
    DN_CNT_REG_0_1I13_GSR_OR_14 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_0_1I13_GSR_OR ) ;
    DN_CNT_REG_1_1I13 : X_FF 
      port map ( I => ARG139(1) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_1_1I13_GSR_OR , RST => GND , O => N260 ) ;
    DN_CNT_REG_1_1I13_GSR_OR_15 : X_OR2 
      port map ( I0 => N198 , I1 => GSR , O => DN_CNT_REG_1_1I13_GSR_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_INV1_F_SUM_0 : X_INV 
      port map ( I => N257 , O => ARG58(0) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_16 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_17 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C_18 : X_AND3 
      port map ( I0 => N255 , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_19 : X_OR3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_20 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND_21 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      I1 => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_22 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND_23 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR_24 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR_25 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N255 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_26 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND_27 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_28 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND_29 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_30 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND_31 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR_32 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR_33 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N254 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND_34 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_35 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND_36 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_37 : X_AND2 
      port map ( I0 => N254 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C7 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_38 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_39 : X_AND3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C_40 : X_AND3 
      port map ( I0 => N257 , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT_41 : X_OR3 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B , 
      I2 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_C , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_42 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND_43 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      I1 => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_44 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND_45 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR_46 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR_47 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F2_XOR , I1 => N257 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_48 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND_49 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT_50 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C3_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND_51 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT 
      , O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_52 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND_53 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR_54 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR_55 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G1_XOR , I1 => N256 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND_56 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_57 : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND_58 : X_AND2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_59 : X_AND2 
      port map ( I0 => N256 , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT : X_OR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
      I1 => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C0BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C1BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C1 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C2BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C2 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C3BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C4BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C5BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C6BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_C7BUF : X_BUF 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C7 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ZERO : X_ZERO 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ZERO ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_X_ONE : X_ONE 
      port map ( O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_33_ONE ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N254 , 
      O => ARG58(3) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_2 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N255 , 
      O => ARG58(2) ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0 : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV 
      , I1 => ADD_31_PLUS_PLUS_U6_S0_1_CO_1 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_Q : X_XOR2 
      port map ( I0 => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_2_0 , I1 => N256 , 
      O => ARG58(1) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_INV1_F_SUM_0 : X_INV 
      port map ( I => N261 , O => ARG139(0) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_60 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_61 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C_62 : X_AND3 
      port map ( I0 => N259 , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_63 : X_OR3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_64 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND_65 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      I1 => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_66 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND_67 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR_68 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR_69 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N259 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_70 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND_71 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_72 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND_73 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_74 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND_75 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR_76 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR_77 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N258 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND_78 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_79 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND_80 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_81 : X_AND2 
      port map ( I0 => N258 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C7 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_82 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_83 : X_AND3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C_84 : X_AND3 
      port map ( I0 => N261 , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT_85 : X_OR3 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B , 
      I2 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_C , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_86 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND_87 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , 
      I1 => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_88 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND_89 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR_90 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR_91 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F2_XOR , I1 => N261 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_92 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND_93 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_F1_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT_94 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C3_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND_95 : X_AND2 
      port map ( I0 => VCC , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_96 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_OUT , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_CIN_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND_97 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR_98 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR_99 : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G1_XOR , I1 => N260 
      , O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND_100 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_XOR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_101 : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND_102 : X_AND2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_103 : X_AND2 
      port map ( I0 => N260 , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT : X_OR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_COUT0_AND , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C0BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C1BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C1 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C2BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C2 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C3BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C4BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C5BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C6BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_C7BUF : X_BUF 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C7 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_X_ZERO : X_ZERO 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ZERO ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_X_ONE : X_ONE 
      port map ( O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_33_ONE ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N258 
      , O => ARG139(3) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_2 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N259 
      , O => ARG139(2) ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV , 
      I1 => SUB_40_MINUS_MINUS_U6_S0_1_CO_1 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_Q : X_XOR2 
      port map ( I0 => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_2_0 , I1 => N260 
      , O => ARG139(1) ) ;
    U91_CLKBUF : X_CKBUF 
      port map ( I => U91_CLKIO_BUFSIG , O => N197 ) ;
    U91_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U91_CLKIO_BUFSIG ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_104 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_105 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_106 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_107 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_108 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_109 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_110 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_111 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_112 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_113 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV_114 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C5 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV_115 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV_116 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV_117 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C4 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV_118 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C0 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV_119 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXA_OUT ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV_120 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C3 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV_121 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV_122 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_C6 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV_123 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_124 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_125 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_126 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_127 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_128 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_129 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_130 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_131 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_132 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_133 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV_134 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C5 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV_135 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_A_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV_136 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV_137 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C4 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_AND3_B_2_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV_138 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C0 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C1_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV_139 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT_2_INV , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXA_OUT ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV_140 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C3 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C2_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV_141 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXB_OUT , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_MUXC_AND_1_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV_142 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_C6 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV_143 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_C6_OR , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_CY4_0_CY4_G4_AND_1_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV_144 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV_145 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV ) ;
    ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV_146 : X_INV 
      port map ( I => ADD_31_PLUS_PLUS_N19 , 
      O => ADD_31_PLUS_PLUS_U6_S0_1_XOR1_G_SUM_0_ARG58_1_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV_147 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV_148 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV ) ;
    SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV_149 : X_INV 
      port map ( I => SUB_40_MINUS_MINUS_N20 , 
      O => SUB_40_MINUS_MINUS_U6_S0_1_XOR1_G_SUM_0_ARG139_1_2_0_0_INV ) ;
    U93_1I20_GTS_TRI_2_INV_150 : X_INV 
      port map ( I => GTS , O => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20_GTS_TRI_2_INV_151 : X_INV 
      port map ( I => GTS , O => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20_GTS_TRI_2_INV_152 : X_INV 
      port map ( I => GTS , O => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20_GTS_TRI_2_INV_153 : X_INV 
      port map ( I => GTS , O => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20_GTS_TRI_2_INV_154 : X_INV 
      port map ( I => GTS , O => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20_GTS_TRI_2_INV_155 : X_INV 
      port map ( I => GTS , O => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20_GTS_TRI_2_INV_156 : X_INV 
      port map ( I => GTS , O => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20_GTS_TRI_2_INV_157 : X_INV 
      port map ( I => GTS , O => U100_1I20_GTS_TRI_2_INV ) ;
    VCC_158 : X_ONE 
      port map ( O => VCC ) ;
    GND_159 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

