-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:31:37 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity LOGIBLOX_SR is
  port (
    DATA_IN : in STD_LOGIC := 'X' ;
    CLOCK : in STD_LOGIC := 'X' ;
    ENABLE : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    DATA_OUT : out  STD_LOGIC_VECTOR ( 15 downto 0 )
  ) ;
end LOGIBLOX_SR ;

architecture STRUCTURE of LOGIBLOX_SR is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N41 , N44 , N43 , N42 , N137 , N138 , N139 , N140 , N141 , N142 , N143 
  , N144 , N145 , N146 , N147 , N148 , N149 , N150 , N151 , N152 , 
  LB_EXAMPLE_LB_GND , LB_EXAMPLE_AND10_OUT , LB_EXAMPLE_INV0_OUT , 
  LB_EXAMPLE_AND20_OUT , LB_EXAMPLE_OR0_OUT , LB_EXAMPLE_AND11_OUT , 
  LB_EXAMPLE_INV1_OUT , LB_EXAMPLE_AND21_OUT , LB_EXAMPLE_OR1_OUT , 
  LB_EXAMPLE_AND12_OUT , LB_EXAMPLE_INV2_OUT , LB_EXAMPLE_AND22_OUT , 
  LB_EXAMPLE_OR2_OUT , LB_EXAMPLE_AND13_OUT , LB_EXAMPLE_INV3_OUT , 
  LB_EXAMPLE_AND23_OUT , LB_EXAMPLE_OR3_OUT , LB_EXAMPLE_AND14_OUT , 
  LB_EXAMPLE_INV4_OUT , LB_EXAMPLE_AND24_OUT , LB_EXAMPLE_OR4_OUT , 
  LB_EXAMPLE_AND15_OUT , LB_EXAMPLE_INV5_OUT , LB_EXAMPLE_AND25_OUT , 
  LB_EXAMPLE_OR5_OUT , LB_EXAMPLE_AND16_OUT , LB_EXAMPLE_INV6_OUT , 
  LB_EXAMPLE_AND26_OUT , LB_EXAMPLE_OR6_OUT , LB_EXAMPLE_AND17_OUT , 
  LB_EXAMPLE_INV7_OUT , LB_EXAMPLE_AND27_OUT , LB_EXAMPLE_OR7_OUT , 
  LB_EXAMPLE_AND18_OUT , LB_EXAMPLE_INV8_OUT , LB_EXAMPLE_AND28_OUT , 
  LB_EXAMPLE_OR8_OUT , LB_EXAMPLE_AND19_OUT , LB_EXAMPLE_INV9_OUT , 
  LB_EXAMPLE_AND29_OUT , LB_EXAMPLE_OR9_OUT , LB_EXAMPLE_AND110_OUT , 
  LB_EXAMPLE_INV10_OUT , LB_EXAMPLE_AND210_OUT , LB_EXAMPLE_OR10_OUT , 
  LB_EXAMPLE_AND111_OUT , LB_EXAMPLE_INV11_OUT , LB_EXAMPLE_AND211_OUT , 
  LB_EXAMPLE_OR11_OUT , LB_EXAMPLE_AND112_OUT , LB_EXAMPLE_INV12_OUT , 
  LB_EXAMPLE_AND212_OUT , LB_EXAMPLE_OR12_OUT , LB_EXAMPLE_AND113_OUT , 
  LB_EXAMPLE_INV13_OUT , LB_EXAMPLE_AND213_OUT , LB_EXAMPLE_OR13_OUT , 
  LB_EXAMPLE_AND114_OUT , LB_EXAMPLE_INV14_OUT , LB_EXAMPLE_AND214_OUT , 
  LB_EXAMPLE_OR14_OUT , LB_EXAMPLE_AND115_OUT , LB_EXAMPLE_INV15_OUT , 
  LB_EXAMPLE_AND215_OUT , LB_EXAMPLE_OR15_OUT , U88_1I20_GTS_TRI , 
  U89_1I20_GTS_TRI , U90_1I20_GTS_TRI , U91_1I20_GTS_TRI , U92_1I20_GTS_TRI , 
  U93_1I20_GTS_TRI , U94_1I20_GTS_TRI , U95_1I20_GTS_TRI , U96_1I20_GTS_TRI , 
  U97_1I20_GTS_TRI , U98_1I20_GTS_TRI , U99_1I20_GTS_TRI , U100_1I20_GTS_TRI , 
  U101_1I20_GTS_TRI , U102_1I20_GTS_TRI , U103_1I20_GTS_TRI , 
  U88_1I20_GTS_TRI_2_INV , U89_1I20_GTS_TRI_2_INV , U90_1I20_GTS_TRI_2_INV , 
  U91_1I20_GTS_TRI_2_INV , U92_1I20_GTS_TRI_2_INV , U93_1I20_GTS_TRI_2_INV , 
  U94_1I20_GTS_TRI_2_INV , U95_1I20_GTS_TRI_2_INV , U96_1I20_GTS_TRI_2_INV , 
  U97_1I20_GTS_TRI_2_INV , U98_1I20_GTS_TRI_2_INV , U99_1I20_GTS_TRI_2_INV , 
  U100_1I20_GTS_TRI_2_INV , U101_1I20_GTS_TRI_2_INV , U102_1I20_GTS_TRI_2_INV , 
  U103_1I20_GTS_TRI_2_INV , GND , GSR , GTS : STD_LOGIC ;
  begin
    U84 : X_BUF 
      port map ( I => DATA_IN , O => N41 ) ;
    U85 : X_BUF 
      port map ( I => CLOCK , O => N42 ) ;
    U86 : X_BUF 
      port map ( I => ENABLE , O => N43 ) ;
    U87 : X_BUF 
      port map ( I => RESET , O => N44 ) ;
    LB_EXAMPLE_LOGIC0 : X_ZERO 
      port map ( O => LB_EXAMPLE_LB_GND ) ;
    LB_EXAMPLE_AND10 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND10_OUT ) ;
    LB_EXAMPLE_INV0 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV0_OUT ) ;
    LB_EXAMPLE_AND20 : X_AND2 
      port map ( I0 => N151 , I1 => LB_EXAMPLE_INV0_OUT , 
      O => LB_EXAMPLE_AND20_OUT ) ;
    LB_EXAMPLE_OR0 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND10_OUT , I1 => LB_EXAMPLE_AND20_OUT , 
      O => LB_EXAMPLE_OR0_OUT ) ;
    LB_EXAMPLE_FF0 : X_FF 
      port map ( I => LB_EXAMPLE_OR0_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N152 ) ;
    LB_EXAMPLE_AND11 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND11_OUT ) ;
    LB_EXAMPLE_INV1 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV1_OUT ) ;
    LB_EXAMPLE_AND21 : X_AND2 
      port map ( I0 => N150 , I1 => LB_EXAMPLE_INV1_OUT , 
      O => LB_EXAMPLE_AND21_OUT ) ;
    LB_EXAMPLE_OR1 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND11_OUT , I1 => LB_EXAMPLE_AND21_OUT , 
      O => LB_EXAMPLE_OR1_OUT ) ;
    LB_EXAMPLE_FF1 : X_FF 
      port map ( I => LB_EXAMPLE_OR1_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N151 ) ;
    LB_EXAMPLE_AND12 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND12_OUT ) ;
    LB_EXAMPLE_INV2 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV2_OUT ) ;
    LB_EXAMPLE_AND22 : X_AND2 
      port map ( I0 => N149 , I1 => LB_EXAMPLE_INV2_OUT , 
      O => LB_EXAMPLE_AND22_OUT ) ;
    LB_EXAMPLE_OR2 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND12_OUT , I1 => LB_EXAMPLE_AND22_OUT , 
      O => LB_EXAMPLE_OR2_OUT ) ;
    LB_EXAMPLE_FF2 : X_FF 
      port map ( I => LB_EXAMPLE_OR2_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N150 ) ;
    LB_EXAMPLE_AND13 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND13_OUT ) ;
    LB_EXAMPLE_INV3 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV3_OUT ) ;
    LB_EXAMPLE_AND23 : X_AND2 
      port map ( I0 => N148 , I1 => LB_EXAMPLE_INV3_OUT , 
      O => LB_EXAMPLE_AND23_OUT ) ;
    LB_EXAMPLE_OR3 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND13_OUT , I1 => LB_EXAMPLE_AND23_OUT , 
      O => LB_EXAMPLE_OR3_OUT ) ;
    LB_EXAMPLE_FF3 : X_FF 
      port map ( I => LB_EXAMPLE_OR3_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N149 ) ;
    LB_EXAMPLE_AND14 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND14_OUT ) ;
    LB_EXAMPLE_INV4 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV4_OUT ) ;
    LB_EXAMPLE_AND24 : X_AND2 
      port map ( I0 => N147 , I1 => LB_EXAMPLE_INV4_OUT , 
      O => LB_EXAMPLE_AND24_OUT ) ;
    LB_EXAMPLE_OR4 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND14_OUT , I1 => LB_EXAMPLE_AND24_OUT , 
      O => LB_EXAMPLE_OR4_OUT ) ;
    LB_EXAMPLE_FF4 : X_FF 
      port map ( I => LB_EXAMPLE_OR4_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N148 ) ;
    LB_EXAMPLE_AND15 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND15_OUT ) ;
    LB_EXAMPLE_INV5 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV5_OUT ) ;
    LB_EXAMPLE_AND25 : X_AND2 
      port map ( I0 => N146 , I1 => LB_EXAMPLE_INV5_OUT , 
      O => LB_EXAMPLE_AND25_OUT ) ;
    LB_EXAMPLE_OR5 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND15_OUT , I1 => LB_EXAMPLE_AND25_OUT , 
      O => LB_EXAMPLE_OR5_OUT ) ;
    LB_EXAMPLE_FF5 : X_FF 
      port map ( I => LB_EXAMPLE_OR5_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N147 ) ;
    LB_EXAMPLE_AND16 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND16_OUT ) ;
    LB_EXAMPLE_INV6 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV6_OUT ) ;
    LB_EXAMPLE_AND26 : X_AND2 
      port map ( I0 => N145 , I1 => LB_EXAMPLE_INV6_OUT , 
      O => LB_EXAMPLE_AND26_OUT ) ;
    LB_EXAMPLE_OR6 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND16_OUT , I1 => LB_EXAMPLE_AND26_OUT , 
      O => LB_EXAMPLE_OR6_OUT ) ;
    LB_EXAMPLE_FF6 : X_FF 
      port map ( I => LB_EXAMPLE_OR6_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N146 ) ;
    LB_EXAMPLE_AND17 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND17_OUT ) ;
    LB_EXAMPLE_INV7 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV7_OUT ) ;
    LB_EXAMPLE_AND27 : X_AND2 
      port map ( I0 => N144 , I1 => LB_EXAMPLE_INV7_OUT , 
      O => LB_EXAMPLE_AND27_OUT ) ;
    LB_EXAMPLE_OR7 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND17_OUT , I1 => LB_EXAMPLE_AND27_OUT , 
      O => LB_EXAMPLE_OR7_OUT ) ;
    LB_EXAMPLE_FF7 : X_FF 
      port map ( I => LB_EXAMPLE_OR7_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N145 ) ;
    LB_EXAMPLE_AND18 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND18_OUT ) ;
    LB_EXAMPLE_INV8 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV8_OUT ) ;
    LB_EXAMPLE_AND28 : X_AND2 
      port map ( I0 => N143 , I1 => LB_EXAMPLE_INV8_OUT , 
      O => LB_EXAMPLE_AND28_OUT ) ;
    LB_EXAMPLE_OR8 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND18_OUT , I1 => LB_EXAMPLE_AND28_OUT , 
      O => LB_EXAMPLE_OR8_OUT ) ;
    LB_EXAMPLE_FF8 : X_FF 
      port map ( I => LB_EXAMPLE_OR8_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N144 ) ;
    LB_EXAMPLE_AND19 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND19_OUT ) ;
    LB_EXAMPLE_INV9 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV9_OUT ) ;
    LB_EXAMPLE_AND29 : X_AND2 
      port map ( I0 => N142 , I1 => LB_EXAMPLE_INV9_OUT , 
      O => LB_EXAMPLE_AND29_OUT ) ;
    LB_EXAMPLE_OR9 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND19_OUT , I1 => LB_EXAMPLE_AND29_OUT , 
      O => LB_EXAMPLE_OR9_OUT ) ;
    LB_EXAMPLE_FF9 : X_FF 
      port map ( I => LB_EXAMPLE_OR9_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N143 ) ;
    LB_EXAMPLE_AND110 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND110_OUT ) ;
    LB_EXAMPLE_INV10 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV10_OUT ) ;
    LB_EXAMPLE_AND210 : X_AND2 
      port map ( I0 => N141 , I1 => LB_EXAMPLE_INV10_OUT , 
      O => LB_EXAMPLE_AND210_OUT ) ;
    LB_EXAMPLE_OR10 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND110_OUT , I1 => LB_EXAMPLE_AND210_OUT , 
      O => LB_EXAMPLE_OR10_OUT ) ;
    LB_EXAMPLE_FF10 : X_FF 
      port map ( I => LB_EXAMPLE_OR10_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N142 ) ;
    LB_EXAMPLE_AND111 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND111_OUT ) ;
    LB_EXAMPLE_INV11 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV11_OUT ) ;
    LB_EXAMPLE_AND211 : X_AND2 
      port map ( I0 => N140 , I1 => LB_EXAMPLE_INV11_OUT , 
      O => LB_EXAMPLE_AND211_OUT ) ;
    LB_EXAMPLE_OR11 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND111_OUT , I1 => LB_EXAMPLE_AND211_OUT , 
      O => LB_EXAMPLE_OR11_OUT ) ;
    LB_EXAMPLE_FF11 : X_FF 
      port map ( I => LB_EXAMPLE_OR11_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N141 ) ;
    LB_EXAMPLE_AND112 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND112_OUT ) ;
    LB_EXAMPLE_INV12 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV12_OUT ) ;
    LB_EXAMPLE_AND212 : X_AND2 
      port map ( I0 => N139 , I1 => LB_EXAMPLE_INV12_OUT , 
      O => LB_EXAMPLE_AND212_OUT ) ;
    LB_EXAMPLE_OR12 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND112_OUT , I1 => LB_EXAMPLE_AND212_OUT , 
      O => LB_EXAMPLE_OR12_OUT ) ;
    LB_EXAMPLE_FF12 : X_FF 
      port map ( I => LB_EXAMPLE_OR12_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N140 ) ;
    LB_EXAMPLE_AND113 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND113_OUT ) ;
    LB_EXAMPLE_INV13 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV13_OUT ) ;
    LB_EXAMPLE_AND213 : X_AND2 
      port map ( I0 => N138 , I1 => LB_EXAMPLE_INV13_OUT , 
      O => LB_EXAMPLE_AND213_OUT ) ;
    LB_EXAMPLE_OR13 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND113_OUT , I1 => LB_EXAMPLE_AND213_OUT , 
      O => LB_EXAMPLE_OR13_OUT ) ;
    LB_EXAMPLE_FF13 : X_FF 
      port map ( I => LB_EXAMPLE_OR13_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N139 ) ;
    LB_EXAMPLE_AND114 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND114_OUT ) ;
    LB_EXAMPLE_INV14 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV14_OUT ) ;
    LB_EXAMPLE_AND214 : X_AND2 
      port map ( I0 => N137 , I1 => LB_EXAMPLE_INV14_OUT , 
      O => LB_EXAMPLE_AND214_OUT ) ;
    LB_EXAMPLE_OR14 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND114_OUT , I1 => LB_EXAMPLE_AND214_OUT , 
      O => LB_EXAMPLE_OR14_OUT ) ;
    LB_EXAMPLE_FF14 : X_FF 
      port map ( I => LB_EXAMPLE_OR14_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N138 ) ;
    LB_EXAMPLE_AND115 : X_AND2 
      port map ( I0 => LB_EXAMPLE_LB_GND , I1 => N44 , 
      O => LB_EXAMPLE_AND115_OUT ) ;
    LB_EXAMPLE_INV15 : X_INV 
      port map ( I => N44 , O => LB_EXAMPLE_INV15_OUT ) ;
    LB_EXAMPLE_AND215 : X_AND2 
      port map ( I0 => N41 , I1 => LB_EXAMPLE_INV15_OUT , 
      O => LB_EXAMPLE_AND215_OUT ) ;
    LB_EXAMPLE_OR15 : X_OR2 
      port map ( I0 => LB_EXAMPLE_AND115_OUT , I1 => LB_EXAMPLE_AND215_OUT , 
      O => LB_EXAMPLE_OR15_OUT ) ;
    LB_EXAMPLE_FF15 : X_FF 
      port map ( I => LB_EXAMPLE_OR15_OUT , CLK => N42 , CE => N43 , SET => GND 
      , RST => GSR , O => N137 ) ;
    U88_1I20 : X_BUF 
      port map ( I => N137 , O => U88_1I20_GTS_TRI ) ;
    U88_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U88_1I20_GTS_TRI , O => DATA_OUT(15) , 
      CTL => U88_1I20_GTS_TRI_2_INV ) ;
    U89_1I20 : X_BUF 
      port map ( I => N138 , O => U89_1I20_GTS_TRI ) ;
    U89_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U89_1I20_GTS_TRI , O => DATA_OUT(14) , 
      CTL => U89_1I20_GTS_TRI_2_INV ) ;
    U90_1I20 : X_BUF 
      port map ( I => N139 , O => U90_1I20_GTS_TRI ) ;
    U90_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U90_1I20_GTS_TRI , O => DATA_OUT(13) , 
      CTL => U90_1I20_GTS_TRI_2_INV ) ;
    U91_1I20 : X_BUF 
      port map ( I => N140 , O => U91_1I20_GTS_TRI ) ;
    U91_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U91_1I20_GTS_TRI , O => DATA_OUT(12) , 
      CTL => U91_1I20_GTS_TRI_2_INV ) ;
    U92_1I20 : X_BUF 
      port map ( I => N141 , O => U92_1I20_GTS_TRI ) ;
    U92_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U92_1I20_GTS_TRI , O => DATA_OUT(11) , 
      CTL => U92_1I20_GTS_TRI_2_INV ) ;
    U93_1I20 : X_BUF 
      port map ( I => N142 , O => U93_1I20_GTS_TRI ) ;
    U93_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U93_1I20_GTS_TRI , O => DATA_OUT(10) , 
      CTL => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20 : X_BUF 
      port map ( I => N143 , O => U94_1I20_GTS_TRI ) ;
    U94_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U94_1I20_GTS_TRI , O => DATA_OUT(9) , 
      CTL => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20 : X_BUF 
      port map ( I => N144 , O => U95_1I20_GTS_TRI ) ;
    U95_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U95_1I20_GTS_TRI , O => DATA_OUT(8) , 
      CTL => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20 : X_BUF 
      port map ( I => N145 , O => U96_1I20_GTS_TRI ) ;
    U96_1I20_GTS_TRI_8 : X_TRI 
      port map ( I => U96_1I20_GTS_TRI , O => DATA_OUT(7) , 
      CTL => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20 : X_BUF 
      port map ( I => N146 , O => U97_1I20_GTS_TRI ) ;
    U97_1I20_GTS_TRI_9 : X_TRI 
      port map ( I => U97_1I20_GTS_TRI , O => DATA_OUT(6) , 
      CTL => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20 : X_BUF 
      port map ( I => N147 , O => U98_1I20_GTS_TRI ) ;
    U98_1I20_GTS_TRI_10 : X_TRI 
      port map ( I => U98_1I20_GTS_TRI , O => DATA_OUT(5) , 
      CTL => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20 : X_BUF 
      port map ( I => N148 , O => U99_1I20_GTS_TRI ) ;
    U99_1I20_GTS_TRI_11 : X_TRI 
      port map ( I => U99_1I20_GTS_TRI , O => DATA_OUT(4) , 
      CTL => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20 : X_BUF 
      port map ( I => N149 , O => U100_1I20_GTS_TRI ) ;
    U100_1I20_GTS_TRI_12 : X_TRI 
      port map ( I => U100_1I20_GTS_TRI , O => DATA_OUT(3) , 
      CTL => U100_1I20_GTS_TRI_2_INV ) ;
    U101_1I20 : X_BUF 
      port map ( I => N150 , O => U101_1I20_GTS_TRI ) ;
    U101_1I20_GTS_TRI_13 : X_TRI 
      port map ( I => U101_1I20_GTS_TRI , O => DATA_OUT(2) , 
      CTL => U101_1I20_GTS_TRI_2_INV ) ;
    U102_1I20 : X_BUF 
      port map ( I => N151 , O => U102_1I20_GTS_TRI ) ;
    U102_1I20_GTS_TRI_14 : X_TRI 
      port map ( I => U102_1I20_GTS_TRI , O => DATA_OUT(1) , 
      CTL => U102_1I20_GTS_TRI_2_INV ) ;
    U103_1I20 : X_BUF 
      port map ( I => N152 , O => U103_1I20_GTS_TRI ) ;
    U103_1I20_GTS_TRI_15 : X_TRI 
      port map ( I => U103_1I20_GTS_TRI , O => DATA_OUT(0) , 
      CTL => U103_1I20_GTS_TRI_2_INV ) ;
    U88_1I20_GTS_TRI_2_INV_16 : X_INV 
      port map ( I => GTS , O => U88_1I20_GTS_TRI_2_INV ) ;
    U89_1I20_GTS_TRI_2_INV_17 : X_INV 
      port map ( I => GTS , O => U89_1I20_GTS_TRI_2_INV ) ;
    U90_1I20_GTS_TRI_2_INV_18 : X_INV 
      port map ( I => GTS , O => U90_1I20_GTS_TRI_2_INV ) ;
    U91_1I20_GTS_TRI_2_INV_19 : X_INV 
      port map ( I => GTS , O => U91_1I20_GTS_TRI_2_INV ) ;
    U92_1I20_GTS_TRI_2_INV_20 : X_INV 
      port map ( I => GTS , O => U92_1I20_GTS_TRI_2_INV ) ;
    U93_1I20_GTS_TRI_2_INV_21 : X_INV 
      port map ( I => GTS , O => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20_GTS_TRI_2_INV_22 : X_INV 
      port map ( I => GTS , O => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20_GTS_TRI_2_INV_23 : X_INV 
      port map ( I => GTS , O => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20_GTS_TRI_2_INV_24 : X_INV 
      port map ( I => GTS , O => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20_GTS_TRI_2_INV_25 : X_INV 
      port map ( I => GTS , O => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20_GTS_TRI_2_INV_26 : X_INV 
      port map ( I => GTS , O => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20_GTS_TRI_2_INV_27 : X_INV 
      port map ( I => GTS , O => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20_GTS_TRI_2_INV_28 : X_INV 
      port map ( I => GTS , O => U100_1I20_GTS_TRI_2_INV ) ;
    U101_1I20_GTS_TRI_2_INV_29 : X_INV 
      port map ( I => GTS , O => U101_1I20_GTS_TRI_2_INV ) ;
    U102_1I20_GTS_TRI_2_INV_30 : X_INV 
      port map ( I => GTS , O => U102_1I20_GTS_TRI_2_INV ) ;
    U103_1I20_GTS_TRI_2_INV_31 : X_INV 
      port map ( I => GTS , O => U103_1I20_GTS_TRI_2_INV ) ;
    GND_32 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

