-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:20:48 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity IF_EX is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    MUX_OUT : out STD_LOGIC ;
    SEL : in  STD_LOGIC_VECTOR ( 1 downto 0 )
  ) ;
end IF_EX ;

architecture STRUCTURE of IF_EX is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N226 , N227 , N228 , N229 , N230 , N231 , N264 , N262 , N263 , N256 , 
  N258 , N257 , N259 , N260 , N261 , U66_1I20_GTS_TRI , U71_2_0 , U75_2_0 , 
  U69_2_INV , U73_2_INV , U74_2_INV , U75_N262_2_INV , U66_1I20_GTS_TRI_2_INV , 
  GTS : STD_LOGIC ;
  begin
    U60 : X_BUF 
      port map ( I => SEL(1) , O => N226 ) ;
    U61 : X_BUF 
      port map ( I => SEL(0) , O => N227 ) ;
    U62 : X_BUF 
      port map ( I => A , O => N228 ) ;
    U63 : X_BUF 
      port map ( I => B , O => N229 ) ;
    U64 : X_BUF 
      port map ( I => C , O => N230 ) ;
    U65 : X_BUF 
      port map ( I => D , O => N231 ) ;
    U67 : X_OR2 
      port map ( I0 => N262 , I1 => N263 , O => N264 ) ;
    U68 : X_INV 
      port map ( I => N231 , O => N256 ) ;
    U69 : X_AND2 
      port map ( I0 => N227 , I1 => N256 , O => U69_2_INV ) ;
    U70 : X_OR2 
      port map ( I0 => N230 , I1 => N227 , O => N257 ) ;
    U72 : X_INV 
      port map ( I => N227 , O => N259 ) ;
    U73 : X_OR2 
      port map ( I0 => N259 , I1 => N229 , O => U73_2_INV ) ;
    U74 : X_OR2 
      port map ( I0 => N228 , I1 => N227 , O => U74_2_INV ) ;
    U66_1I20 : X_BUF 
      port map ( I => N264 , O => U66_1I20_GTS_TRI ) ;
    U66_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U66_1I20_GTS_TRI , O => MUX_OUT , 
      CTL => U66_1I20_GTS_TRI_2_INV ) ;
    U71_N263_2_0 : X_AND2 
      port map ( I0 => N258 , I1 => N257 , O => U71_2_0 ) ;
    U71_N263 : X_AND2 
      port map ( I0 => U71_2_0 , I1 => N226 , O => N263 ) ;
    U75_N262_2_0 : X_OR2 
      port map ( I0 => N226 , I1 => N261 , O => U75_2_0 ) ;
    U75_N262 : X_OR2 
      port map ( I0 => U75_2_0 , I1 => N260 , O => U75_N262_2_INV ) ;
    U69_2_INV_1 : X_INV 
      port map ( I => U69_2_INV , O => N258 ) ;
    U73_2_INV_2 : X_INV 
      port map ( I => U73_2_INV , O => N260 ) ;
    U74_2_INV_3 : X_INV 
      port map ( I => U74_2_INV , O => N261 ) ;
    U75_N262_2_INV_4 : X_INV 
      port map ( I => U75_N262_2_INV , O => N262 ) ;
    U66_1I20_GTS_TRI_2_INV_5 : X_INV 
      port map ( I => GTS , O => U66_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

