----------------------------------------------------
-- CLOCK_ENABLE.VHD Version 1.0                   --
-- Code showing use of the clock enable of the FF --
-- HDL Synthesis Design Guide for FPGAs           --
-- May 1997                                       --
----------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity clock_enable is
    port (IN1,IN2,DATA,CLOCK,LOAD: in STD_LOGIC;
	  DOUT: out STD_LOGIC);
end clock_enable;

architecture BEHAV of clock_enable is
signal ENABLE: STD_LOGIC;
begin

    ENABLE <= IN1 and IN2 and LOAD;

    EN_PR: process (ENABLE,DATA,CLOCK)
    begin
        if (CLOCK'event and CLOCK='1') then
	    if (ENABLE='1') then
	        DOUT <= DATA;
            end if;
        end if;
    end process; -- End EN_PR

end BEHAV;
