-------------------------------------------------
-- MUX_TBUF16.VHD Version 1.0                  --
-- 16-to-1 Mux Implemented in 3-State Buffers  --
-- Xilinx HDL Synthesis Design Guide for FPGAs -- 
-- May 1997                                    --
-------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_tbuf16 is
port (	SEL: in STD_LOGIC_VECTOR (15 downto 0);
	A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P: in STD_LOGIC;
        SIG: out STD_LOGIC);
end mux_tbuf16;

architecture RTL of mux_tbuf16 is
begin

    SIG <= A when (SEL(0)='0') else 'Z';
    SIG <= B when (SEL(1)='0') else 'Z';
    SIG <= C when (SEL(2)='0') else 'Z';
    SIG <= D when (SEL(3)='0') else 'Z';
    SIG <= E when (SEL(4)='0') else 'Z';
    SIG <= F when (SEL(5)='0') else 'Z';
    SIG <= G when (SEL(6)='0') else 'Z';
    SIG <= H when (SEL(7)='0') else 'Z';
    SIG <= I when (SEL(8)='0') else 'Z';
    SIG <= J when (SEL(9)='0') else 'Z';
    SIG <= K when (SEL(10)='0') else 'Z';
    SIG <= L when (SEL(11)='0') else 'Z';
    SIG <= M when (SEL(12)='0') else 'Z';
    SIG <= N when (SEL(13)='0') else 'Z';
    SIG <= O when (SEL(14)='0') else 'Z';
    SIG <= P when (SEL(15)='0') else 'Z';

end RTL;
