-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:34:11 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity LOGIBLOX_DP_RAM is
  port (
    WE : in STD_LOGIC := 'X' ;
    CLOCK : in STD_LOGIC := 'X' ;
    DATA_IN : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    WRITE_ADDR : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    READ_ADDR : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    DATA_OUT : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end LOGIBLOX_DP_RAM ;

architecture STRUCTURE of LOGIBLOX_DP_RAM is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N40 , N41 , N42 , N43 , N36 , N37 , N38 , N39 , N48 , N49 , N44 , N45 
  , N46 , N47 , N111 , N112 , N113 , N114 , DPRAM16X4_SPO0_0 , DPRAM16X4_SPO0_1 
  , DPRAM16X4_SPO0_2 , DPRAM16X4_SPO0_3 , U88_1I20_GTS_TRI , U89_1I20_GTS_TRI , 
  U90_1I20_GTS_TRI , U91_1I20_GTS_TRI , U87_CLKIO_BUFSIG , 
  U88_1I20_GTS_TRI_2_INV , U89_1I20_GTS_TRI_2_INV , U90_1I20_GTS_TRI_2_INV , 
  U91_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U74 : X_BUF 
      port map ( I => DATA_IN(3) , O => N36 ) ;
    U75 : X_BUF 
      port map ( I => DATA_IN(2) , O => N37 ) ;
    U76 : X_BUF 
      port map ( I => DATA_IN(1) , O => N38 ) ;
    U77 : X_BUF 
      port map ( I => DATA_IN(0) , O => N39 ) ;
    U78 : X_BUF 
      port map ( I => WRITE_ADDR(3) , O => N40 ) ;
    U79 : X_BUF 
      port map ( I => WRITE_ADDR(2) , O => N41 ) ;
    U80 : X_BUF 
      port map ( I => WRITE_ADDR(1) , O => N42 ) ;
    U81 : X_BUF 
      port map ( I => WRITE_ADDR(0) , O => N43 ) ;
    U82 : X_BUF 
      port map ( I => READ_ADDR(3) , O => N44 ) ;
    U83 : X_BUF 
      port map ( I => READ_ADDR(2) , O => N45 ) ;
    U84 : X_BUF 
      port map ( I => READ_ADDR(1) , O => N46 ) ;
    U85 : X_BUF 
      port map ( I => READ_ADDR(0) , O => N47 ) ;
    U86 : X_BUF 
      port map ( I => WE , O => N48 ) ;
    DPRAM16X4_MEM0_0_X_RAMS16 : X_RAMS16 
      generic map ( INIT => "F982" ) 
      port map ( ADR0 => N43 , ADR1 => N42 , ADR2 => N41 , ADR3 => N40 , 
      I => N39 , CLK => N49 , WE => N48 , O => DPRAM16X4_SPO0_0 ) ;
    DPRAM16X4_MEM0_0_X_RAMD16 : X_RAMD16 
      generic map ( INIT => "F982" ) 
      port map ( RADR0 => N47 , RADR1 => N46 , RADR2 => N45 , RADR3 => N44 , 
      WADR0 => N43 , WADR1 => N42 , WADR2 => N41 , WADR3 => N40 , I => N39 , 
      CLK => N49 , WE => N48 , O => N114 ) ;
    DPRAM16X4_MEM1_0_X_RAMS16 : X_RAMS16 
      generic map ( INIT => "C244" ) 
      port map ( ADR0 => N43 , ADR1 => N42 , ADR2 => N41 , ADR3 => N40 , 
      I => N38 , CLK => N49 , WE => N48 , O => DPRAM16X4_SPO0_1 ) ;
    DPRAM16X4_MEM1_0_X_RAMD16 : X_RAMD16 
      generic map ( INIT => "C244" ) 
      port map ( RADR0 => N47 , RADR1 => N46 , RADR2 => N45 , RADR3 => N44 , 
      WADR0 => N43 , WADR1 => N42 , WADR2 => N41 , WADR3 => N40 , I => N38 , 
      CLK => N49 , WE => N48 , O => N113 ) ;
    DPRAM16X4_MEM2_0_X_RAMS16 : X_RAMS16 
      generic map ( INIT => "A428" ) 
      port map ( ADR0 => N43 , ADR1 => N42 , ADR2 => N41 , ADR3 => N40 , 
      I => N37 , CLK => N49 , WE => N48 , O => DPRAM16X4_SPO0_2 ) ;
    DPRAM16X4_MEM2_0_X_RAMD16 : X_RAMD16 
      generic map ( INIT => "A428" ) 
      port map ( RADR0 => N47 , RADR1 => N46 , RADR2 => N45 , RADR3 => N44 , 
      WADR0 => N43 , WADR1 => N42 , WADR2 => N41 , WADR3 => N40 , I => N37 , 
      CLK => N49 , WE => N48 , O => N112 ) ;
    DPRAM16X4_MEM3_0_X_RAMS16 : X_RAMS16 
      generic map ( INIT => "FFF0" ) 
      port map ( ADR0 => N43 , ADR1 => N42 , ADR2 => N41 , ADR3 => N40 , 
      I => N36 , CLK => N49 , WE => N48 , O => DPRAM16X4_SPO0_3 ) ;
    DPRAM16X4_MEM3_0_X_RAMD16 : X_RAMD16 
      generic map ( INIT => "FFF0" ) 
      port map ( RADR0 => N47 , RADR1 => N46 , RADR2 => N45 , RADR3 => N44 , 
      WADR0 => N43 , WADR1 => N42 , WADR2 => N41 , WADR3 => N40 , I => N36 , 
      CLK => N49 , WE => N48 , O => N111 ) ;
    U88_1I20 : X_BUF 
      port map ( I => N111 , O => U88_1I20_GTS_TRI ) ;
    U88_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U88_1I20_GTS_TRI , O => DATA_OUT(3) , 
      CTL => U88_1I20_GTS_TRI_2_INV ) ;
    U89_1I20 : X_BUF 
      port map ( I => N112 , O => U89_1I20_GTS_TRI ) ;
    U89_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U89_1I20_GTS_TRI , O => DATA_OUT(2) , 
      CTL => U89_1I20_GTS_TRI_2_INV ) ;
    U90_1I20 : X_BUF 
      port map ( I => N113 , O => U90_1I20_GTS_TRI ) ;
    U90_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U90_1I20_GTS_TRI , O => DATA_OUT(1) , 
      CTL => U90_1I20_GTS_TRI_2_INV ) ;
    U91_1I20 : X_BUF 
      port map ( I => N114 , O => U91_1I20_GTS_TRI ) ;
    U91_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U91_1I20_GTS_TRI , O => DATA_OUT(0) , 
      CTL => U91_1I20_GTS_TRI_2_INV ) ;
    U87_CLKBUF : X_CKBUF 
      port map ( I => U87_CLKIO_BUFSIG , O => N49 ) ;
    U87_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U87_CLKIO_BUFSIG ) ;
    U88_1I20_GTS_TRI_2_INV_4 : X_INV 
      port map ( I => GTS , O => U88_1I20_GTS_TRI_2_INV ) ;
    U89_1I20_GTS_TRI_2_INV_5 : X_INV 
      port map ( I => GTS , O => U89_1I20_GTS_TRI_2_INV ) ;
    U90_1I20_GTS_TRI_2_INV_6 : X_INV 
      port map ( I => GTS , O => U90_1I20_GTS_TRI_2_INV ) ;
    U91_1I20_GTS_TRI_2_INV_7 : X_INV 
      port map ( I => GTS , O => U91_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

