-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:13:26 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity CONSTANT_EX is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    OP_OUT : out STD_LOGIC ;
    OPCODE : in  STD_LOGIC_VECTOR ( 1 downto 0 )
  ) ;
end CONSTANT_EX ;

architecture STRUCTURE of CONSTANT_EX is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N191 , N192 , N193 , N194 , N216 , N215 , N213 , N214 , 
  U49_1I20_GTS_TRI , U51_2_0 , U52_2_0 , U50_2_INV , U53_2_INV , U51_N214_2_INV 
  , U49_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U45 : X_BUF 
      port map ( I => OPCODE(1) , O => N191 ) ;
    U46 : X_BUF 
      port map ( I => OPCODE(0) , O => N192 ) ;
    U47 : X_BUF 
      port map ( I => A , O => N193 ) ;
    U48 : X_BUF 
      port map ( I => B , O => N194 ) ;
    U50 : X_AND2 
      port map ( I0 => N213 , I1 => N191 , O => U50_2_INV ) ;
    U53 : X_AND2 
      port map ( I0 => N214 , I1 => N215 , O => U53_2_INV ) ;
    U49_1I20 : X_BUF 
      port map ( I => N216 , O => U49_1I20_GTS_TRI ) ;
    U49_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U49_1I20_GTS_TRI , O => OP_OUT , 
      CTL => U49_1I20_GTS_TRI_2_INV ) ;
    U51_N214_2_0 : X_AND2 
      port map ( I0 => N193 , I1 => N194 , O => U51_2_0 ) ;
    U51_N214 : X_AND2 
      port map ( I0 => U51_2_0 , I1 => N192 , O => U51_N214_2_INV ) ;
    U52_N213_2_0 : X_OR2 
      port map ( I0 => N193 , I1 => N194 , O => U52_2_0 ) ;
    U52_N213 : X_OR2 
      port map ( I0 => U52_2_0 , I1 => N192 , O => N213 ) ;
    U50_2_INV_1 : X_INV 
      port map ( I => U50_2_INV , O => N215 ) ;
    U53_2_INV_2 : X_INV 
      port map ( I => U53_2_INV , O => N216 ) ;
    U51_N214_2_INV_3 : X_INV 
      port map ( I => U51_N214_2_INV , O => N214 ) ;
    U49_1I20_GTS_TRI_2_INV_4 : X_INV 
      port map ( I => GTS , O => U49_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

