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-- XOR_SIG.VHD Version 1.0           --
-- Xilinx HDL Synthesis Design Guide --
-- Comparing Signals and Variables   --
-- May 1997                          --
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Library IEEE;
use IEEE.std_logic_1164.all;

entity xor_sig is
    port (A, B, C: in  STD_LOGIC;
	  X, Y: out STD_LOGIC);
end xor_sig;

architecture SIG_ARCH of xor_sig is
    signal D: STD_LOGIC;
begin
    SIG:process (A,B,C)
    begin
	D <= A; -- ignored !!
	X <= C xor D;
	D <= B; -- overrides !!
	Y <= C xor D;
    end process;
end SIG_ARCH;
