----------------------------------------------------
-- ACTIVE_LOW_GR.VHD Version 1.0                  --
-- Xilinx HDL Synthesis Design Guide              --
-- The signal RESET is inverted before being      --
-- connected to the GSRIN pin of the STARTBUF     --
-- The inverter will be absorbed by the STARTBUF  --
-- September 1997                                 --
----------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity active_low_gr is
    port ( CLOCK: in STD_LOGIC;
           RESET: in STD_LOGIC;
           UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
           DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end active_low_gr;

architecture XILINX of active_low_gr is

    component INV
        port (I: in  STD_LOGIC;
              O: out STD_LOGIC);
    end component;

    component STARTBUF
        port (GSRIN:  in  STD_LOGIC;
              GSROUT: out STD_LOGIC);
    end component;

    signal RESET_NOT:     STD_LOGIC;
    signal RESET_NOT_INT: STD_LOGIC;
    signal UP_CNT:        STD_LOGIC_VECTOR (3 downto 0);
    signal DN_CNT:        STD_LOGIC_VECTOR (3 downto 0);

    begin

    U1: INV port map(I => RESET, O => RESET_NOT);

    U2: STARTBUF port map(GSRIN=>RESET_NOT, 
                          GSROUT=>RESET_NOT_INT);
 
    UP_COUNTER: process(CLOCK, RESET_NOT_INT)
    begin
        if (RESET_NOT_INT = '1') then
            UP_CNT <= "0000";
        elsif (CLOCK'event and CLOCK = '1') then
            UP_CNT <= UP_CNT + 1;
        end if;
    end process;
 
    DN_COUNTER: process(CLOCK, RESET_NOT_INT) 
    begin
        if (RESET_NOT_INT = '1') then
            DN_CNT <= "1111";
        elsif (CLOCK'event and CLOCK = '1') then
            DN_CNT <= DN_CNT - 1;
        end if;
    end process;
 
    UPCNT <= UP_CNT;
    DNCNT <= DN_CNT;

end XILINX;
