-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:55:50 1998
-- Design file: time_sim.nga
-- Device: 5202pc84-4
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity PRESET_5K is
  port (
    Q : out STD_LOGIC ;
    PRESET : in STD_LOGIC := 'X' ;
    DATA : in STD_LOGIC := 'X' ;
    CLK : in STD_LOGIC := 'X' 
  ) ;
end PRESET_5K ;

architecture STRUCTURE of PRESET_5K is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N52 , N46 , N45 , N44 , U22_1I20_GTS_TRI , Q_REG_D_IN , Q_REG_Q_OUT , 
  Q_REG_1I13_GR_OR , U25_CLKIO_BUFSIG , U22_1I20_GTS_TRI_2_INV , GND , GR , VCC 
  , GTS : STD_LOGIC ;
  begin
    U23 : X_BUF 
      port map ( I => PRESET , O => N46 ) ;
    U24 : X_BUF 
      port map ( I => DATA , O => N45 ) ;
    U22_1I20 : X_BUF 
      port map ( I => N52 , O => U22_1I20_GTS_TRI ) ;
    U22_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U22_1I20_GTS_TRI , O => Q , CTL => U22_1I20_GTS_TRI_2_INV 
      ) ;
    Q_REG_SYM1 : X_INV 
      port map ( I => N45 , O => Q_REG_D_IN ) ;
    Q_REG_SYM2 : X_INV 
      port map ( I => Q_REG_Q_OUT , O => N52 ) ;
    Q_REG_1I13 : X_FF 
      port map ( I => Q_REG_D_IN , CLK => N44 , CE => VCC , SET => GND , 
      RST => Q_REG_1I13_GR_OR , O => Q_REG_Q_OUT ) ;
    Q_REG_1I13_GR_OR_1 : X_OR2 
      port map ( I0 => N46 , I1 => GR , O => Q_REG_1I13_GR_OR ) ;
    U25_CLKBUF : X_CKBUF 
      port map ( I => U25_CLKIO_BUFSIG , O => N44 ) ;
    U25_CLKIO_BUF : X_BUF 
      port map ( I => CLK , O => U25_CLKIO_BUFSIG ) ;
    U22_1I20_GTS_TRI_2_INV_2 : X_INV 
      port map ( I => GTS , O => U22_1I20_GTS_TRI_2_INV ) ;
    VCC_3 : X_ONE 
      port map ( O => VCC ) ;
    GND_4 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

