-----------------------------------------------
-- CLOCK_MUX.VHD Version 1.0                 --
-- This is an example of an instantiation of --
-- global buffer (BUFGS) from an internally  --
-- driven signal, a multiplexed clock.       --
-- July 1997                                 --
-----------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity clock_mux is
    port (DATA, SEL:              in  STD_LOGIC;
          SLOW_CLOCK, FAST_CLOCK: in  STD_LOGIC;
	  DOUT:                   out STD_LOGIC);
end clock_mux;

architecture XILINX of clock_mux is

signal CLOCK:      STD_LOGIC;
signal CLOCK_GBUF: STD_LOGIC;

component BUFGS 
    port (I: in  STD_LOGIC; 
          O: out STD_LOGIC);
end component;

begin

Clock_MUX: process (SEL)
    begin
        if (SEL = '1') then
   	    CLOCK <= FAST_CLOCK;
        else
            CLOCK <= SLOW_CLOCK;
	end if;
    end process;

GBUF_FOR_MUX_CLOCK: BUFGS 
    port map (I => CLOCK, 
              O => CLOCK_GBUF);

Data_Path: process (CLOCK_GBUF, DATA)
    begin
        if (CLOCK_GBUF'event and CLOCK_GBUF='1') then
            DOUT <= DATA;
        end if;
    end process;

end XILINX;
