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-- LogiBLOX BIDI Module "bidir_io_from_lb"
-- Created by LogiBLOX version M1.3.7
--    on Mon Sep  8 13:14:02 1997
-- Attributes 
--    MODTYPE = BIDI
--    BUS_WIDTH = 2
--    IN_TYPE = LATCH
--    OUT_TYPE = TRI
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;

ENTITY bidir_io_from_lb IS
  PORT(
    O: IN std_logic_vector(1 DOWNTO 0);
    OE: IN std_logic;
    IGATE: IN std_logic;
    IQ: OUT std_logic_vector(1 DOWNTO 0);
    P: INOUT std_logic_vector(1 DOWNTO 0));
END bidir_io_from_lb;

ARCHITECTURE sim OF bidir_io_from_lb IS
  SIGNAL D : std_logic_vector(1 DOWNTO 0);
  SIGNAL GSR: std_logic := '1';
BEGIN
  PROCESS
  BEGIN
    IF (
       (stdbit2mvl(IGATE)='1' )
       OR ( stdbit2mvl(GSR)='1')
      ) THEN
      IF (GSR = '1') THEN
        IQ <= ('0','0');
      ELSE
        IQ <= stdvec2mvl(P);
      END IF;
    ELSIF (
       (stdbit2mvl(IGATE) = 'X')
      ) THEN
      IQ <= ('X','X');
    END IF;
      WAIT ON O, OE, P, IGATE, GSR;
  END PROCESS;

  PROCESS
  BEGIN
      IF (GSR='1') THEN
        GSR <= '0' AFTER 1 ns;
      END IF;
    WAIT ON GSR;
  END PROCESS;

  PROCESS(D,OE)
  BEGIN
  CASE stdbit2mvl(OE) IS
   WHEN '0' =>
     P <= stdvec2mvl(D);
   WHEN '1' =>
     P <= ('Z','Z');
   WHEN OTHERS =>
     P <= ('X','X');
  END CASE;
  END PROCESS;

  D <= O;
END sim;
