----------------------------------------
--  BIDIR_INSTANTIATE.VHD Version 1.0 --
--  Example of  an instantiation      --
--  of a bi-directional pin           --
--  August 1997                       --
----------------------------------------

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity bidir_instantiate is

    port (DATA :       inout STD_LOGIC_VECTOR(1 downto 0);
	  READ_WRITE : in    STD_LOGIC);

end bidir_instantiate;

architecture XILINX of bidir_instantiate is

    signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0);
    signal DATA_OUT :  STD_LOGIC_VECTOR(1 downto 0);
    signal GATE :      STD_LOGIC;

    component ILD_1
        port (D, G : in  STD_LOGIC;
              Q    : out STD_LOGIC);
    end component;

    component OBUFT_S
        port (I, T : in  STD_LOGIC;
              O :    out STD_LOGIC);
    end component;

    begin
		
    DATA_OUT(0) <= LATCH_OUT(0) and LATCH_OUT(1);
    DATA_OUT(1) <= LATCH_OUT(0) or LATCH_OUT(1);

    GATE <= not READ_WRITE;

    INPUT_PATH_0 : ILD_1
        port map (D => DATA(0), G => GATE,
                  Q => LATCH_OUT(0));

    INPUT_PATH_1 : ILD_1
        port map (D => DATA(1), G => GATE,
                  Q => LATCH_OUT(1));

    OUPUT_PATH_0 : OBUFT_S
        port map (I => DATA_OUT(0), T => READ_WRITE,
                  O => DATA(0));

    OUPUT_PATH_1 : OBUFT_S
        port map (I => DATA_OUT(1), T => READ_WRITE,
                  O => DATA(1));

end XILINX;
