-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:29:00 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity MUX_GATE is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    C : in STD_LOGIC := 'X' ;
    D : in STD_LOGIC := 'X' ;
    E : in STD_LOGIC := 'X' ;
    SIG : out STD_LOGIC ;
    SEL : in  STD_LOGIC_VECTOR ( 2 downto 0 )
  ) ;
end MUX_GATE ;

architecture STRUCTURE of MUX_GATE is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N27 , N28 , N29 , N30 , N31 , N32 , N33 , N34 , N77 , N70 , N68 , N69 
  , N56 , N57 , N71 , N73 , N72 , N74 , N75 , N76 , U58_1I20_GTS_TRI , U66_2_0 
  , U70_2_0 , U60_2_INV , U61_2_INV , U62_2_INV , U64_2_INV , U68_2_INV , 
  U69_2_INV , U70_N56_2_INV , U58_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U50 : X_BUF 
      port map ( I => SEL(2) , O => N27 ) ;
    U51 : X_BUF 
      port map ( I => SEL(1) , O => N28 ) ;
    U52 : X_BUF 
      port map ( I => SEL(0) , O => N29 ) ;
    U53 : X_BUF 
      port map ( I => A , O => N30 ) ;
    U54 : X_BUF 
      port map ( I => B , O => N31 ) ;
    U55 : X_BUF 
      port map ( I => C , O => N32 ) ;
    U56 : X_BUF 
      port map ( I => D , O => N33 ) ;
    U57 : X_BUF 
      port map ( I => E , O => N34 ) ;
    U59 : X_OR2 
      port map ( I0 => N27 , I1 => N68 , O => N70 ) ;
    U60 : X_AND2 
      port map ( I0 => N27 , I1 => N34 , O => U60_2_INV ) ;
    U61 : X_OR2 
      port map ( I0 => N56 , I1 => N57 , O => U61_2_INV ) ;
    U62 : X_AND2 
      port map ( I0 => N69 , I1 => N70 , O => U62_2_INV ) ;
    U63 : X_INV 
      port map ( I => N33 , O => N71 ) ;
    U64 : X_AND2 
      port map ( I0 => N29 , I1 => N71 , O => U64_2_INV ) ;
    U65 : X_OR2 
      port map ( I0 => N32 , I1 => N29 , O => N72 ) ;
    U67 : X_INV 
      port map ( I => N29 , O => N74 ) ;
    U68 : X_OR2 
      port map ( I0 => N74 , I1 => N31 , O => U68_2_INV ) ;
    U69 : X_OR2 
      port map ( I0 => N30 , I1 => N29 , O => U69_2_INV ) ;
    U58_1I20 : X_BUF 
      port map ( I => N77 , O => U58_1I20_GTS_TRI ) ;
    U58_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U58_1I20_GTS_TRI , O => SIG , 
      CTL => U58_1I20_GTS_TRI_2_INV ) ;
    U66_N57_2_0 : X_AND2 
      port map ( I0 => N73 , I1 => N72 , O => U66_2_0 ) ;
    U66_N57 : X_AND2 
      port map ( I0 => U66_2_0 , I1 => N28 , O => N57 ) ;
    U70_N56_2_0 : X_OR2 
      port map ( I0 => N28 , I1 => N76 , O => U70_2_0 ) ;
    U70_N56 : X_OR2 
      port map ( I0 => U70_2_0 , I1 => N75 , O => U70_N56_2_INV ) ;
    U60_2_INV_1 : X_INV 
      port map ( I => U60_2_INV , O => N69 ) ;
    U61_2_INV_2 : X_INV 
      port map ( I => U61_2_INV , O => N68 ) ;
    U62_2_INV_3 : X_INV 
      port map ( I => U62_2_INV , O => N77 ) ;
    U64_2_INV_4 : X_INV 
      port map ( I => U64_2_INV , O => N73 ) ;
    U68_2_INV_5 : X_INV 
      port map ( I => U68_2_INV , O => N75 ) ;
    U69_2_INV_6 : X_INV 
      port map ( I => U69_2_INV , O => N76 ) ;
    U70_N56_2_INV_7 : X_INV 
      port map ( I => U70_N56_2_INV , O => N56 ) ;
    U58_1I20_GTS_TRI_2_INV_8 : X_INV 
      port map ( I => GTS , O => U58_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

