----------------------------------------------
-- CONSTANT_EX.VHD Version 1.0              --
-- Xilinx HDL Synthesis Design Guide        --
-- Example of specifying constants to make  --
-- for more readable code.                  --
-- May 1997                                 --
----------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity constant_ex is
    port (OPCODE : in  STD_LOGIC_VECTOR(1 downto 0);
          A, B   : in  STD_LOGIC;
	  OP_OUT    : out STD_LOGIC);
end constant_ex;

architecture BEHAV of constant_ex is

    constant ZERO   : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant A_AND_B: STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant A_OR_B : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ONE    : STD_LOGIC_VECTOR (1 downto 0) := "11";

begin

    process (OPCODE, A, B) 
    begin
        if    (OPCODE = A_AND_B) then OP_OUT <= A and B;
        elsif (OPCODE = A_OR_B) then  OP_OUT <= A or B;
        elsif (OPCODE = ONE) then     OP_OUT <= '1';
        else                          OP_OUT <= '0';
        end if;
    end process;

end BEHAV;
