-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:15:52 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity CLOCK_MUX is
  port (
    DATA : in STD_LOGIC := 'X' ;
    SEL : in STD_LOGIC := 'X' ;
    SLOW_CLOCK : in STD_LOGIC := 'X' ;
    FAST_CLOCK : in STD_LOGIC := 'X' ;
    DOUT : out STD_LOGIC 
  ) ;
end CLOCK_MUX ;

architecture STRUCTURE of CLOCK_MUX is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal CLOCK_GBUF , CLOCK , N27 , N28 , N29 , N30 , N54 , N45 , N51 , N53 , 
  N52 , DOUT_REG_1I11_QINT , DOUT_REG_1I11_OBUF_GTS_TRI , U41_2_INV , U42_2_INV 
  , DOUT_REG_1I11_OBUF_GTS_TRI_2_INV , GND , GTS , VCC , GSR : STD_LOGIC ;
  begin
    GBUF_FOR_MUX_CLOCK : X_CKBUF 
      port map ( I => CLOCK , O => CLOCK_GBUF ) ;
    U34 : X_BUF 
      port map ( I => DATA , O => N27 ) ;
    U35 : X_BUF 
      port map ( I => SEL , O => N28 ) ;
    U36 : X_BUF 
      port map ( I => SLOW_CLOCK , O => N29 ) ;
    U37 : X_BUF 
      port map ( I => FAST_CLOCK , O => N30 ) ;
    U38 : X_INV 
      port map ( I => CLOCK_GBUF , O => N45 ) ;
    U39 : X_INV 
      port map ( I => N29 , O => N51 ) ;
    U40 : X_OR2 
      port map ( I0 => N28 , I1 => N51 , O => N53 ) ;
    U41 : X_AND2 
      port map ( I0 => N28 , I1 => N30 , O => U41_2_INV ) ;
    U42 : X_AND2 
      port map ( I0 => N52 , I1 => N53 , O => U42_2_INV ) ;
    U43 : X_INV 
      port map ( I => N45 , O => N54 ) ;
    DOUT_REG_1I11_FF : X_FF 
      port map ( I => N27 , CLK => N54 , CE => VCC , SET => GND , RST => GSR , 
      O => DOUT_REG_1I11_QINT ) ;
    DOUT_REG_1I11_OBUF : X_BUF 
      port map ( I => DOUT_REG_1I11_QINT , O => DOUT_REG_1I11_OBUF_GTS_TRI ) ;
    DOUT_REG_1I11_OBUF_GTS_TRI_0 : X_TRI 
      port map ( I => DOUT_REG_1I11_OBUF_GTS_TRI , O => DOUT , 
      CTL => DOUT_REG_1I11_OBUF_GTS_TRI_2_INV ) ;
    U41_2_INV_1 : X_INV 
      port map ( I => U41_2_INV , O => N52 ) ;
    U42_2_INV_2 : X_INV 
      port map ( I => U42_2_INV , O => CLOCK ) ;
    DOUT_REG_1I11_OBUF_GTS_TRI_2_INV_3 : X_INV 
      port map ( I => GTS , O => DOUT_REG_1I11_OBUF_GTS_TRI_2_INV ) ;
    VCC_4 : X_ONE 
      port map ( O => VCC ) ;
    GND_5 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

