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-- RES_SHARING.VHD Version 1.0                      --
-- Xilinx HDL Synthesis Design Guide for FPGAs      --
-- Resource Sharing Example                         --
-- The VHDL code for these examples are the same    --
-- but the libraries are changed to show the        --
-- effects of using diffent libraries for synthesis --
-- May 1997                                         --
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity res_sharing is
    port (A1,B1,C1,D1: in STD_LOGIC_VECTOR (7 downto 0);
	  COND_1: in STD_LOGIC;
	  Z1: out STD_LOGIC_VECTOR (7 downto 0));
end res_sharing;

architecture BEHAV of res_sharing is
begin
P1: process (A1,B1,C1,D1,COND_1)   
    begin
	if (COND_1='1') then
	    Z1 <= A1 + B1;
	else
	    Z1 <= C1 + D1;
        end if;
    end process; -- end P1

end BEHAV;
