-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 15:54:15 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity UNBONDED_IO is
  port (
    A : in STD_LOGIC := 'X' ;
    B : in STD_LOGIC := 'X' ;
    CLK : in STD_LOGIC := 'X' ;
    Q_OUT : out STD_LOGIC 
  ) ;
end UNBONDED_IO ;

architecture STRUCTURE of UNBONDED_IO is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal U_D , N10 , N26 , N8 , N9 , U2_VCC , U0_VCC , U27_1I20_GTS_TRI , 
  U26_CLKIO_BUFSIG , U_Q_3_OUTBLOCK_OQ , U_Q_3_INBLOCK_I , U_Q_3_INBLOCK_DELAY 
  , U_Q_1_OUTBLOCK_OQ , U_Q_1_INBLOCK_I , U_Q_1_INBLOCK_DELAY , 
  U27_1I20_GTS_TRI_2_INV , U_Q_3_OUTBLOCK_OUT_BUF_2_INV , 
  U_Q_1_OUTBLOCK_OUT_BUF_2_INV , GND , VCC , GSR , GTS : STD_LOGIC ;
  signal U_Q : STD_LOGIC_VECTOR ( 3 downto 1 );
  begin
    U24 : X_BUF 
      port map ( I => A , O => N8 ) ;
    U25 : X_BUF 
      port map ( I => B , O => N9 ) ;
    U28 : X_AND2 
      port map ( I0 => N9 , I1 => N8 , O => U_D ) ;
    U2_VCC_ONE : X_ONE 
      port map ( O => U2_VCC ) ;
    U0_VCC_ONE : X_ONE 
      port map ( O => U0_VCC ) ;
    U27_1I20 : X_BUF 
      port map ( I => N26 , O => U27_1I20_GTS_TRI ) ;
    U27_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U27_1I20_GTS_TRI , O => Q_OUT , 
      CTL => U27_1I20_GTS_TRI_2_INV ) ;
    U26_CLKBUF : X_CKBUF 
      port map ( I => U26_CLKIO_BUFSIG , O => N10 ) ;
    U26_CLKIO_BUF : X_BUF 
      port map ( I => CLK , O => U26_CLKIO_BUFSIG ) ;
    U_Q_3_OUTBLOCK_OUT_BUF : X_TRI 
      port map ( I => U_Q_3_OUTBLOCK_OQ , O => U_Q(3) , 
      CTL => U_Q_3_OUTBLOCK_OUT_BUF_2_INV ) ;
    U_Q_3_OUTBLOCK_OUTFF : X_FF 
      port map ( I => U_D , CLK => N10 , CE => VCC , SET => GND , RST => GSR , 
      O => U_Q_3_OUTBLOCK_OQ ) ;
    U_Q_3_INBLOCK_INBUF : X_BUF 
      port map ( I => U_Q(3) , O => U_Q_3_INBLOCK_I ) ;
    U_Q_3_INBLOCK_INFF : X_FF 
      port map ( I => U_Q_3_INBLOCK_DELAY , CLK => N10 , CE => VCC , SET => GSR 
      , RST => GND , O => U_Q(2) ) ;
    U_Q_3_INBLOCK_DELAYBUF : X_BUF 
      port map ( I => U_Q_3_INBLOCK_I , O => U_Q_3_INBLOCK_DELAY ) ;
    U_Q_1_OUTBLOCK_OUT_BUF : X_TRI 
      port map ( I => U_Q_1_OUTBLOCK_OQ , O => U_Q(1) , 
      CTL => U_Q_1_OUTBLOCK_OUT_BUF_2_INV ) ;
    U_Q_1_OUTBLOCK_OUTFF : X_FF 
      port map ( I => U_Q(2) , CLK => N10 , CE => VCC , SET => GSR , RST => GND 
      , O => U_Q_1_OUTBLOCK_OQ ) ;
    U_Q_1_INBLOCK_INBUF : X_BUF 
      port map ( I => U_Q(1) , O => U_Q_1_INBLOCK_I ) ;
    U_Q_1_INBLOCK_INFF : X_FF 
      port map ( I => U_Q_1_INBLOCK_DELAY , CLK => N10 , CE => VCC , SET => GND 
      , RST => GSR , O => N26 ) ;
    U_Q_1_INBLOCK_DELAYBUF : X_BUF 
      port map ( I => U_Q_1_INBLOCK_I , O => U_Q_1_INBLOCK_DELAY ) ;
    U27_1I20_GTS_TRI_2_INV_1 : X_INV 
      port map ( I => GTS , O => U27_1I20_GTS_TRI_2_INV ) ;
    U_Q_3_OUTBLOCK_OUT_BUF_2_INV_2 : X_INV 
      port map ( I => GTS , O => U_Q_3_OUTBLOCK_OUT_BUF_2_INV ) ;
    U_Q_1_OUTBLOCK_OUT_BUF_2_INV_3 : X_INV 
      port map ( I => GTS , O => U_Q_1_OUTBLOCK_OUT_BUF_2_INV ) ;
    VCC_4 : X_ONE 
      port map ( O => VCC ) ;
    GND_5 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

