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-- SET_AND_RESET.VHD Version 1.0                    --
-- Xilinx HDL Synthesis Design Guide                --
-- Code describing an asynchronous set and RESET FF --
-- Do not use this code for Xilinx FPGA FFs         --
-- May 1997                                         --
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library IEEE;
use IEEE.std_logic_1164.all;

entity set_and_reset is
    port (CLK, DATA, PRESET, RESET: in STD_LOGIC;
	  Q: out STD_LOGIC);
end set_and_reset;

architecture BEHAV of set_and_reset is
begin
SR_FLOP: process (CLK, PRESET, RESET)
    begin
        if (RESET='1') then
   	    Q <= '0';
        elsif (PRESET='1') then
   	    Q <= '1';
        elsif (CLK'event and CLK='1') then
   	    Q <= DATA;
	end if;
    end process; -- End SR_FLOP
end BEHAV;
