-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:12:18 1998
-- Design file: time_sim.nga
-- Device: 4013xlpq160-1
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity OMUX_EXAMPLE is
  port (
    SEL : in STD_LOGIC := 'X' ;
    DATA_OUT : out STD_LOGIC ;
    DATA_IN : in  STD_LOGIC_VECTOR ( 1 downto 0 )
  ) ;
end OMUX_EXAMPLE ;

architecture STRUCTURE of OMUX_EXAMPLE is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N26 , N10 , N9 , N11 , DUEL_OUT_D0_AND_OUT , DUEL_OUT_D1_AND_OUT , 
  DUEL_OUT_D_AND_OUT , DUEL_OUT_OUT , U23_1I20_GTS_TRI , DUEL_OUT_DO_AND_1_INV 
  , U23_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U20 : X_BUF 
      port map ( I => DATA_IN(1) , O => N9 ) ;
    U21 : X_BUF 
      port map ( I => DATA_IN(0) , O => N10 ) ;
    U22 : X_BUF 
      port map ( I => SEL , O => N11 ) ;
    DUEL_OUT_DO_AND : X_AND2 
      port map ( I0 => N10 , I1 => DUEL_OUT_DO_AND_1_INV , 
      O => DUEL_OUT_D0_AND_OUT ) ;
    DUEL_OUT_D1_AND : X_AND2 
      port map ( I0 => N9 , I1 => N11 , O => DUEL_OUT_D1_AND_OUT ) ;
    DUEL_OUT_A_AND : X_AND2 
      port map ( I0 => N10 , I1 => N9 , O => DUEL_OUT_D_AND_OUT ) ;
    DUEL_OUT_OUT_OR : X_OR3 
      port map ( I0 => DUEL_OUT_D0_AND_OUT , I1 => DUEL_OUT_D1_AND_OUT , 
      I2 => DUEL_OUT_D_AND_OUT , O => DUEL_OUT_OUT ) ;
    DUEL_OUT_X_BUF : X_BUF 
      port map ( I => DUEL_OUT_OUT , O => N26 ) ;
    U23_1I20 : X_BUF 
      port map ( I => N26 , O => U23_1I20_GTS_TRI ) ;
    U23_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U23_1I20_GTS_TRI , O => DATA_OUT , 
      CTL => U23_1I20_GTS_TRI_2_INV ) ;
    DUEL_OUT_DO_AND_1_INV_1 : X_INV 
      port map ( I => N11 , O => DUEL_OUT_DO_AND_1_INV ) ;
    U23_1I20_GTS_TRI_2_INV_2 : X_INV 
      port map ( I => GTS , O => U23_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

