------------------------------------------
-- LOGIBLOX_SR.VHD Version 1.0          --
-- Xilinx HDL Synthesis Design Guide    --
-- Example of a LogiBLOX                --
-- Shift Register instantiation         --
-- August 1997                          --
------------------------------------------

------------------------------------------------------
-- LogiBLOX SHIFT Module "shifter_16"
-- Created by LogiBLOX version M1.3.7
--    on Wed Aug 13 17:35:39 1997
-- Attributes 
--    MODTYPE = SHIFT
--    BUS_WIDTH = 16
--    ENCODING = UNSIGNED
--    OPTYPE = RIGHT
--    SHIFT_TYPE = LOGICAL
--    SYNC_VAL = 0
------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity logiblox_sr is
port (	DATA_IN:  in STD_LOGIC;  -- Serial input data
      	CLOCK:    in STD_LOGIC;  -- System clock
      	ENABLE:   in STD_LOGIC;  -- Shifter Enable
      	RESET:    in STD_LOGIC;  -- Synchronous Reset
	DATA_OUT: out STD_LOGIC_VECTOR(15 downto 0));
                              -- Parallel Ouput Data
end logiblox_sr;

architecture XILINX of logiblox_sr is

----------------------------------------------------
-- Component Declaration 
----------------------------------------------------
component shifter_16
  PORT(
    MS_IN: IN std_logic;
    SYNC_CTRL: IN std_logic;
    CLK_EN: IN std_logic;
    CLOCK: IN std_logic;
    Q_OUT: OUT std_logic_vector(15 DOWNTO 0));
end component;
 

begin

----------------------------------------------------
-- Component Instantiation 
----------------------------------------------------
LB_EXAMPLE : shifter_16 port map
(MS_IN => DATA_IN,
 SYNC_CTRL => RESET,
 CLK_EN => ENABLE,
 CLOCK => CLOCK,
 Q_OUT => DATA_OUT);


end XILINX;
