-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:06:18 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity ROM_RTL is
  port (
    ADDR : in  STD_LOGIC_VECTOR ( 3 downto 0 );
    DATA : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end ROM_RTL ;

architecture STRUCTURE of ROM_RTL is
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N234 , N235 , N236 , N237 , N295 , N296 , N297 , N298 , N275 , N273 , 
  N274 , N277 , N280 , N276 , N279 , N278 , N281 , N283 , N287 , N286 , N282 , 
  N285 , N284 , N289 , N292 , N293 , N288 , N291 , N290 , N294 , 
  U63_1I20_GTS_TRI , U64_1I20_GTS_TRI , U65_1I20_GTS_TRI , U66_1I20_GTS_TRI , 
  U71_2_0 , U78_2_0 , U81_2_0 , U87_2_0 , U87_2_1 , U68_2_INV , U69_2_INV , 
  U70_2_INV , U72_2_INV , U75_2_INV , U79_2_INV , U80_2_INV , U82_2_INV , 
  U83_2_INV , U88_2_INV , U89_2_INV , U90_2_INV , U91_2_INV , U71_N279_2_INV , 
  U78_N287_2_INV , U63_1I20_GTS_TRI_2_INV , U64_1I20_GTS_TRI_2_INV , 
  U65_1I20_GTS_TRI_2_INV , U66_1I20_GTS_TRI_2_INV , GTS : STD_LOGIC ;
  begin
    U59 : X_BUF 
      port map ( I => ADDR(3) , O => N234 ) ;
    U60 : X_BUF 
      port map ( I => ADDR(2) , O => N235 ) ;
    U61 : X_BUF 
      port map ( I => ADDR(1) , O => N236 ) ;
    U62 : X_BUF 
      port map ( I => ADDR(0) , O => N237 ) ;
    U67 : X_OR2 
      port map ( I0 => N236 , I1 => N273 , O => N275 ) ;
    U68 : X_AND2 
      port map ( I0 => N277 , I1 => N236 , O => U68_2_INV ) ;
    U69 : X_OR2 
      port map ( I0 => N235 , I1 => N234 , O => U69_2_INV ) ;
    U70 : X_AND2 
      port map ( I0 => N276 , I1 => N234 , O => U70_2_INV ) ;
    U72 : X_AND2 
      port map ( I0 => N277 , I1 => N278 , O => U72_2_INV ) ;
    U73 : X_INV 
      port map ( I => N235 , O => N277 ) ;
    U74 : X_XOR2 
      port map ( I0 => N236 , I1 => N237 , O => N278 ) ;
    U75 : X_AND2 
      port map ( I0 => N279 , I1 => N280 , O => U75_2_INV ) ;
    U76 : X_INV 
      port map ( I => N234 , O => N281 ) ;
    U77 : X_INV 
      port map ( I => N237 , O => N283 ) ;
    U79 : X_AND2 
      port map ( I0 => N282 , I1 => N234 , O => U79_2_INV ) ;
    U80 : X_AND2 
      port map ( I0 => N285 , I1 => N284 , O => U80_2_INV ) ;
    U82 : X_AND2 
      port map ( I0 => N236 , I1 => N235 , O => U82_2_INV ) ;
    U83 : X_AND2 
      port map ( I0 => N286 , I1 => N287 , O => U83_2_INV ) ;
    U84 : X_INV 
      port map ( I => N292 , O => N289 ) ;
    U85 : X_INV 
      port map ( I => N236 , O => N293 ) ;
    U86 : X_INV 
      port map ( I => N234 , O => N288 ) ;
    U88 : X_AND2 
      port map ( I0 => N237 , I1 => N289 , O => U88_2_INV ) ;
    U89 : X_AND2 
      port map ( I0 => N290 , I1 => N291 , O => U89_2_INV ) ;
    U90 : X_XOR2 
      port map ( I0 => N294 , I1 => N235 , O => U90_2_INV ) ;
    U91 : X_OR2 
      port map ( I0 => N293 , I1 => N234 , O => U91_2_INV ) ;
    U92 : X_OR2 
      port map ( I0 => N234 , I1 => N235 , O => N295 ) ;
    U63_1I20 : X_BUF 
      port map ( I => N295 , O => U63_1I20_GTS_TRI ) ;
    U63_1I20_GTS_TRI_0 : X_TRI 
      port map ( I => U63_1I20_GTS_TRI , O => DATA(3) , 
      CTL => U63_1I20_GTS_TRI_2_INV ) ;
    U64_1I20 : X_BUF 
      port map ( I => N296 , O => U64_1I20_GTS_TRI ) ;
    U64_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U64_1I20_GTS_TRI , O => DATA(2) , 
      CTL => U64_1I20_GTS_TRI_2_INV ) ;
    U65_1I20 : X_BUF 
      port map ( I => N297 , O => U65_1I20_GTS_TRI ) ;
    U65_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U65_1I20_GTS_TRI , O => DATA(1) , 
      CTL => U65_1I20_GTS_TRI_2_INV ) ;
    U66_1I20 : X_BUF 
      port map ( I => N298 , O => U66_1I20_GTS_TRI ) ;
    U66_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U66_1I20_GTS_TRI , O => DATA(0) , 
      CTL => U66_1I20_GTS_TRI_2_INV ) ;
    U71_N279_2_0 : X_AND2 
      port map ( I0 => N275 , I1 => N274 , O => U71_2_0 ) ;
    U71_N279 : X_AND2 
      port map ( I0 => U71_2_0 , I1 => N237 , O => U71_N279_2_INV ) ;
    U78_N287_2_0 : X_AND2 
      port map ( I0 => N236 , I1 => N283 , O => U78_2_0 ) ;
    U78_N287 : X_AND2 
      port map ( I0 => U78_2_0 , I1 => N281 , O => U78_N287_2_INV ) ;
    U81_N284_2_0 : X_OR2 
      port map ( I0 => N283 , I1 => N236 , O => U81_2_0 ) ;
    U81_N284 : X_OR2 
      port map ( I0 => U81_2_0 , I1 => N235 , O => N284 ) ;
    U87_N291_2_0 : X_OR2 
      port map ( I0 => N293 , I1 => N235 , O => U87_2_0 ) ;
    U87_N291_2_1 : X_OR2 
      port map ( I0 => N288 , I1 => N237 , O => U87_2_1 ) ;
    U87_N291 : X_OR2 
      port map ( I0 => U87_2_0 , I1 => U87_2_1 , O => N291 ) ;
    U68_2_INV_4 : X_INV 
      port map ( I => U68_2_INV , O => N274 ) ;
    U69_2_INV_5 : X_INV 
      port map ( I => U69_2_INV , O => N273 ) ;
    U70_2_INV_6 : X_INV 
      port map ( I => U70_2_INV , O => N280 ) ;
    U72_2_INV_7 : X_INV 
      port map ( I => U72_2_INV , O => N276 ) ;
    U75_2_INV_8 : X_INV 
      port map ( I => U75_2_INV , O => N298 ) ;
    U79_2_INV_9 : X_INV 
      port map ( I => U79_2_INV , O => N286 ) ;
    U80_2_INV_10 : X_INV 
      port map ( I => U80_2_INV , O => N282 ) ;
    U82_2_INV_11 : X_INV 
      port map ( I => U82_2_INV , O => N285 ) ;
    U83_2_INV_12 : X_INV 
      port map ( I => U83_2_INV , O => N297 ) ;
    U88_2_INV_13 : X_INV 
      port map ( I => U88_2_INV , O => N290 ) ;
    U89_2_INV_14 : X_INV 
      port map ( I => U89_2_INV , O => N296 ) ;
    U90_2_INV_15 : X_INV 
      port map ( I => U90_2_INV , O => N292 ) ;
    U91_2_INV_16 : X_INV 
      port map ( I => U91_2_INV , O => N294 ) ;
    U71_N279_2_INV_17 : X_INV 
      port map ( I => U71_N279_2_INV , O => N279 ) ;
    U78_N287_2_INV_18 : X_INV 
      port map ( I => U78_N287_2_INV , O => N287 ) ;
    U63_1I20_GTS_TRI_2_INV_19 : X_INV 
      port map ( I => GTS , O => U63_1I20_GTS_TRI_2_INV ) ;
    U64_1I20_GTS_TRI_2_INV_20 : X_INV 
      port map ( I => GTS , O => U64_1I20_GTS_TRI_2_INV ) ;
    U65_1I20_GTS_TRI_2_INV_21 : X_INV 
      port map ( I => GTS , O => U65_1I20_GTS_TRI_2_INV ) ;
    U66_1I20_GTS_TRI_2_INV_22 : X_INV 
      port map ( I => GTS , O => U66_1I20_GTS_TRI_2_INV ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

