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-- XOR_VAR.VHD Version 1.0           --
-- Xilinx HDL Synthesis Design Guide --
-- Comparing Signals and Variables   --
-- May 1997                          --
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity xor_var is
    port (A, B, C: in  STD_LOGIC;
	  X, Y:    out STD_LOGIC);
end xor_var;

architecture VAR_ARCH of xor_var is
begin

    VAR:process (A,B,C)
   	variable D: STD_LOGIC;
    begin
	D := A;
	X <= C xor D;
	D := B; 
	Y <= C xor D;
    end process;
end VAR_ARCH;
