-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 16:57:12 1998
-- Design file: time_sim.nga
-- Device: 4005epc84-2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity ACTIVE_LOW_GSR is
  port (
    CLOCK : in STD_LOGIC := 'X' ;
    RESET : in STD_LOGIC := 'X' ;
    UPCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 );
    DNCNT : out  STD_LOGIC_VECTOR ( 3 downto 0 )
  ) ;
end ACTIVE_LOW_GSR ;

architecture STRUCTURE of ACTIVE_LOW_GSR is
  signal RESET_NOT , N198 , RESET_NOT_INT , NET12 , NET13 , N197 , N254 , N255 
  , N256 , N257 , N258 , N259 , N260 , N261 , ADD_50_PLUS_PLUS_N19 , 
  SUB_59_MINUS_MINUS_N20 , ADD_50_PLUS_PLUS_U6_S0_1_CO_4 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CO_3 , ADD_50_PLUS_PLUS_U6_S0_1_CO_2 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CO_4 , SUB_59_MINUS_MINUS_U6_S0_1_CO_3 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CO_2 , U2_U2_STARTUP_1_INV , U93_1I20_GTS_TRI , 
  U94_1I20_GTS_TRI , U95_1I20_GTS_TRI , U96_1I20_GTS_TRI , U97_1I20_GTS_TRI , 
  U98_1I20_GTS_TRI , U99_1I20_GTS_TRI , U100_1I20_GTS_TRI , 
  UP_CNT_REG_2_1I13_GSR_OR , UP_CNT_REG_3_1I13_GSR_OR , 
  DN_CNT_REG_2_1I13_GSR_OR , DN_CNT_REG_3_1I13_GSR_OR , U91_CLKIO_BUFSIG , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 , ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C2 , ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 , ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , N257_F , N257_G , 
  N257_FGBLOCK_COUT0 , N257_FGBLOCK_1N8 , N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
  N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , N257_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
  N257_FGBLOCK_LUTRAM_CARRYBLK_AND5 , N257_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 , SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C1 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C2 , SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 , SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
  SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , 
  SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , N261_F , N261_G , 
  N261_FGBLOCK_COUT0 , N261_FGBLOCK_1N8 , N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
  N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , N261_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
  N261_FGBLOCK_LUTRAM_CARRYBLK_AND5 , N261_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV , 
  ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
  SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
  U93_1I20_GTS_TRI_2_INV , U94_1I20_GTS_TRI_2_INV , U95_1I20_GTS_TRI_2_INV , 
  U96_1I20_GTS_TRI_2_INV , U97_1I20_GTS_TRI_2_INV , U98_1I20_GTS_TRI_2_INV , 
  U99_1I20_GTS_TRI_2_INV , U100_1I20_GTS_TRI_2_INV , 
  N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , 
  N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV 
  , GND , GTS , VCC , GSR : STD_LOGIC ;
  signal ARG58 : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal ARG139 : STD_LOGIC_VECTOR ( 3 downto 2 );
  begin
    U1 : X_INV 
      port map ( I => N198 , O => RESET_NOT ) ;
    U92 : X_BUF 
      port map ( I => RESET , O => N198 ) ;
    NET12_ZERO : X_ZERO 
      port map ( O => NET12 ) ;
    NET13_ZERO : X_ZERO 
      port map ( O => NET13 ) ;
    ADD_50_PLUS_PLUS_N19_ONE : X_ONE 
      port map ( O => ADD_50_PLUS_PLUS_N19 ) ;
    SUB_59_MINUS_MINUS_N20_ZERO : X_ZERO 
      port map ( O => SUB_59_MINUS_MINUS_N20 ) ;
    U2_ROC : X_ZERO 
      port map ( O => RESET_NOT_INT ) ;
    U2_U2_STARTUP_1_INV_0 : X_INV 
      port map ( I => RESET_NOT , O => U2_U2_STARTUP_1_INV ) ;
    U2_STARTUP_GSR_BUF : X_INV 
      port map ( I => U2_U2_STARTUP_1_INV , O => GSR ) ;
    U2_STARTUP_GTS_BUF : X_BUF 
      port map ( I => NET12 , O => GTS ) ;
    U93_1I20 : X_BUF 
      port map ( I => N254 , O => U93_1I20_GTS_TRI ) ;
    U93_1I20_GTS_TRI_1 : X_TRI 
      port map ( I => U93_1I20_GTS_TRI , O => UPCNT(3) , 
      CTL => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20 : X_BUF 
      port map ( I => N255 , O => U94_1I20_GTS_TRI ) ;
    U94_1I20_GTS_TRI_2 : X_TRI 
      port map ( I => U94_1I20_GTS_TRI , O => UPCNT(2) , 
      CTL => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20 : X_BUF 
      port map ( I => N256 , O => U95_1I20_GTS_TRI ) ;
    U95_1I20_GTS_TRI_3 : X_TRI 
      port map ( I => U95_1I20_GTS_TRI , O => UPCNT(1) , 
      CTL => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20 : X_BUF 
      port map ( I => N257 , O => U96_1I20_GTS_TRI ) ;
    U96_1I20_GTS_TRI_4 : X_TRI 
      port map ( I => U96_1I20_GTS_TRI , O => UPCNT(0) , 
      CTL => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20 : X_BUF 
      port map ( I => N258 , O => U97_1I20_GTS_TRI ) ;
    U97_1I20_GTS_TRI_5 : X_TRI 
      port map ( I => U97_1I20_GTS_TRI , O => DNCNT(3) , 
      CTL => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20 : X_BUF 
      port map ( I => N259 , O => U98_1I20_GTS_TRI ) ;
    U98_1I20_GTS_TRI_6 : X_TRI 
      port map ( I => U98_1I20_GTS_TRI , O => DNCNT(2) , 
      CTL => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20 : X_BUF 
      port map ( I => N260 , O => U99_1I20_GTS_TRI ) ;
    U99_1I20_GTS_TRI_7 : X_TRI 
      port map ( I => U99_1I20_GTS_TRI , O => DNCNT(1) , 
      CTL => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20 : X_BUF 
      port map ( I => N261 , O => U100_1I20_GTS_TRI ) ;
    U100_1I20_GTS_TRI_8 : X_TRI 
      port map ( I => U100_1I20_GTS_TRI , O => DNCNT(0) , 
      CTL => U100_1I20_GTS_TRI_2_INV ) ;
    UP_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG58(2) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_2_1I13_GSR_OR , O => N255 ) ;
    UP_CNT_REG_2_1I13_GSR_OR_9 : X_OR2 
      port map ( I0 => RESET_NOT_INT , I1 => GSR , 
      O => UP_CNT_REG_2_1I13_GSR_OR ) ;
    UP_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG58(3) , CLK => N197 , CE => VCC , SET => GND , 
      RST => UP_CNT_REG_3_1I13_GSR_OR , O => N254 ) ;
    UP_CNT_REG_3_1I13_GSR_OR_10 : X_OR2 
      port map ( I0 => RESET_NOT_INT , I1 => GSR , 
      O => UP_CNT_REG_3_1I13_GSR_OR ) ;
    DN_CNT_REG_2_1I13 : X_FF 
      port map ( I => ARG139(2) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_2_1I13_GSR_OR , RST => GND , O => N259 ) ;
    DN_CNT_REG_2_1I13_GSR_OR_11 : X_OR2 
      port map ( I0 => RESET_NOT_INT , I1 => GSR , 
      O => DN_CNT_REG_2_1I13_GSR_OR ) ;
    DN_CNT_REG_3_1I13 : X_FF 
      port map ( I => ARG139(3) , CLK => N197 , CE => VCC , 
      SET => DN_CNT_REG_3_1I13_GSR_OR , RST => GND , O => N258 ) ;
    DN_CNT_REG_3_1I13_GSR_OR_12 : X_OR2 
      port map ( I0 => RESET_NOT_INT , I1 => GSR , 
      O => DN_CNT_REG_3_1I13_GSR_OR ) ;
    U91_CLKBUF : X_CKBUF 
      port map ( I => U91_CLKIO_BUFSIG , O => N197 ) ;
    U91_CLKIO_BUF : X_BUF 
      port map ( I => CLOCK , O => U91_CLKIO_BUFSIG ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_13 : X_AND3 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_14 : X_AND3 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C_15 : X_AND3 
      port map ( I0 => N255 , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_16 : X_OR3 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_17 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C1 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND_18 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      I1 => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_19 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND_20 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR_21 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR_22 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N255 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_23 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C2 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND_24 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_25 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND_26 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_27 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND_28 : X_AND2 
      port map ( I0 => VCC , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR_29 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR_30 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N254 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND_31 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_32 : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND_33 : X_AND2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_34 : X_AND2 
      port map ( I0 => N254 , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_4 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C1 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C2 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C7 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV 
      , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CO_3 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_Q : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N254 , 
      O => ARG58(3) ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0 : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV 
      , I1 => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_Q : X_XOR2 
      port map ( I0 => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N255 , 
      O => ARG58(2) ) ;
    N257_DFF_OUT_FFX : X_FF 
      port map ( I => N257_F , CLK => N197 , CE => VCC , SET => GND , 
      RST => GSR , O => N257 ) ;
    N257_DFF_OUT_FFY : X_FF 
      port map ( I => N257_G , CLK => N197 , CE => VCC , SET => GND , 
      RST => GSR , O => N256 ) ;
    N257_FGBLOCK_G2MUX : X_BUF 
      port map ( I => N257_FGBLOCK_COUT0 , O => N257_FGBLOCK_1N8 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_A0BUF : X_BUF 
      port map ( I => N257 , O => N257_FGBLOCK_COUT0 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF_35 : X_BUF 
      port map ( I => N256 , O => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CO_2 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND4_36 : X_AND2 
      port map ( I0 => N257_FGBLOCK_COUT0 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND4 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_INV1_37 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_INV1 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_38 : X_AND2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5 ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3_39 : X_XOR2 
      port map ( I0 => N257_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
      I1 => N257_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 ) ;
    N257_FGBLOCK_LUTRAM_FLUT_OBUF : X_INV 
      port map ( I => N257 , O => N257_F ) ;
    N257_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
      port map ( I0 => N257_FGBLOCK_1N8 , I1 => N256 , O => N257_G ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_40 : X_AND3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_41 : X_AND3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C_42 : X_AND3 
      port map ( I0 => N259 , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT_43 : X_OR3 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B , 
      I2 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_C , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_44 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C1 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND_45 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      I1 => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_46 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C0_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND_47 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR_48 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR_49 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F2_XOR , I1 => N259 
      , O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_50 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C2 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND_51 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_F1_XOR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT_52 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C3_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND_53 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_54 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_OUT , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_CIN_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND_55 : X_AND2 
      port map ( I0 => VCC , I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR_56 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR_57 : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G1_XOR , I1 => N258 
      , O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND_58 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_XOR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_59 : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND_60 : X_AND2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_61 : X_AND2 
      port map ( I0 => N258 , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT : X_OR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_COUT0_AND , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_4 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C0BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C1BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C1 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C2BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C2 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C3BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C4BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C5BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C6BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_C7BUF : X_BUF 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C7 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ZERO : X_ZERO 
      port map ( O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ZERO ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_X_ONE : X_ONE 
      port map ( O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_32_ONE ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CO_3 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_Q : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_2_0 , I1 => N258 
      , O => ARG139(3) ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0 : X_XOR2 
      port map ( 
      I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV , 
      I1 => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_Q : X_XOR2 
      port map ( I0 => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_2_0 , I1 => N259 
      , O => ARG139(2) ) ;
    N261_DFF_OUT_FFX : X_FF 
      port map ( I => N261_F , CLK => N197 , CE => VCC , SET => GSR , 
      RST => GND , O => N261 ) ;
    N261_DFF_OUT_FFY : X_FF 
      port map ( I => N261_G , CLK => N197 , CE => VCC , SET => GSR , 
      RST => GND , O => N260 ) ;
    N261_FGBLOCK_G2MUX : X_BUF 
      port map ( I => N261_FGBLOCK_COUT0 , O => N261_FGBLOCK_1N8 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_A0BUF : X_BUF 
      port map ( I => N261 , O => N261_FGBLOCK_COUT0 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF_62 : X_BUF 
      port map ( I => N260 , O => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_OR1 : X_OR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND4 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CO_2 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND4_63 : X_AND2 
      port map ( I0 => N261_FGBLOCK_COUT0 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND4 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_INV1_64 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_INV1 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_65 : X_AND2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5 ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3_66 : X_XOR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_CARRYBLK_INV1 , 
      I1 => N261_FGBLOCK_LUTRAM_CARRYBLK_A1BUF , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 ) ;
    N261_FGBLOCK_LUTRAM_FLUT_OBUF : X_INV 
      port map ( I => N261 , O => N261_F ) ;
    N261_FGBLOCK_LUTRAM_GLUT_XOR0 : X_XOR2 
      port map ( I0 => N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV , I1 => N260 , 
      O => N261_G ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_67 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C5 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_68 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_69 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_70 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C4 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_71 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C0 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_72 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_73 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C3 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_74 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_75 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_C6 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_76 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV_77 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C5 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV_78 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_A_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV_79 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV_80 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C4 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_AND3_B_2_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV_81 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C0 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C1_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV_82 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT_2_INV , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXA_OUT ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV_83 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C3 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C2_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV_84 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXB_OUT , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_MUXC_AND_1_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV_85 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_C6 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV_86 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_C6_OR , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_CY4_1_CY4_G4_AND_1_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV_87 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR3_G_SUM_1_ARG58_3_2_0_0_INV ) ;
    ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV_88 : X_INV 
      port map ( I => ADD_50_PLUS_PLUS_N19 , 
      O => ADD_50_PLUS_PLUS_U6_S0_1_XOR2_F_SUM_1_ARG58_2_2_0_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV_89 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR3_G_SUM_1_ARG139_3_2_0_0_INV ) ;
    SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV_90 : X_INV 
      port map ( I => SUB_59_MINUS_MINUS_N20 , 
      O => SUB_59_MINUS_MINUS_U6_S0_1_XOR2_F_SUM_1_ARG139_2_2_0_0_INV ) ;
    U93_1I20_GTS_TRI_2_INV_91 : X_INV 
      port map ( I => GTS , O => U93_1I20_GTS_TRI_2_INV ) ;
    U94_1I20_GTS_TRI_2_INV_92 : X_INV 
      port map ( I => GTS , O => U94_1I20_GTS_TRI_2_INV ) ;
    U95_1I20_GTS_TRI_2_INV_93 : X_INV 
      port map ( I => GTS , O => U95_1I20_GTS_TRI_2_INV ) ;
    U96_1I20_GTS_TRI_2_INV_94 : X_INV 
      port map ( I => GTS , O => U96_1I20_GTS_TRI_2_INV ) ;
    U97_1I20_GTS_TRI_2_INV_95 : X_INV 
      port map ( I => GTS , O => U97_1I20_GTS_TRI_2_INV ) ;
    U98_1I20_GTS_TRI_2_INV_96 : X_INV 
      port map ( I => GTS , O => U98_1I20_GTS_TRI_2_INV ) ;
    U99_1I20_GTS_TRI_2_INV_97 : X_INV 
      port map ( I => GTS , O => U99_1I20_GTS_TRI_2_INV ) ;
    U100_1I20_GTS_TRI_2_INV_98 : X_INV 
      port map ( I => GTS , O => U100_1I20_GTS_TRI_2_INV ) ;
    N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_99 : X_INV 
      port map ( I => N257_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N257_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV ) ;
    N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV_100 : X_INV 
      port map ( I => N261_FGBLOCK_LUTRAM_CARRYBLK_XOR3 , 
      O => N261_FGBLOCK_LUTRAM_CARRYBLK_AND5_0_INV ) ;
    N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV_101 : X_INV 
      port map ( I => N261_FGBLOCK_1N8 , 
      O => N261_FGBLOCK_LUTRAM_GLUT_XOR0_0_INV ) ;
    VCC_102 : X_ONE 
      port map ( O => VCC ) ;
    GND_103 : X_ZERO 
      port map ( O => GND ) ;
end STRUCTURE ;

