-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:39:08 1998
-- Design file: time_sim.nga
-- Device: 4013xlpq160-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity BIDIR_INFER is
  port (
    READ_WRITE : in STD_LOGIC := 'X' ;
    DATA : inout  STD_LOGIC_VECTOR ( 1 downto 0 )
  ) ;
end BIDIR_INFER ;

architecture STRUCTURE of BIDIR_INFER is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N65 , N66 , LATCH_OUT_REG_1_G_OUT , LATCH_OUT_REG_0_G_OUT , 
  N47_0_13_INV , U34_B_GTS_AND , U35_B_GTS_AND , U36_CLKIO_BUFSIG , N47_0_DIN , 
  N47_0_F , N47_0_G , N47_0_H1 , N47_0_H , N47_0_DFF_OUT_QYLATCH , 
  N47_0_DFF_OUT_QXLATCH , N47_0_FGBLOCK_1N8 , N47_0_FGBLOCK_1N7 , 
  U34_B_GTS_AND_0_INV , U34_B_GTS_AND_1_INV , U35_B_GTS_AND_0_INV , 
  U35_B_GTS_AND_1_INV , GTS , GND , GSR , VCC : STD_LOGIC ;
  signal LATCH_OUT : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal DATA_TRI_ENABLE : STD_LOGIC_VECTOR ( 1 downto 1 );
  signal N47 : STD_LOGIC_VECTOR ( 0 downto 0 );
  signal DATA45 : STD_LOGIC_VECTOR ( 0 downto 0 );
  begin
    VCC_ONE : X_ONE 
      port map ( O => VCC ) ;
    GND_ZERO : X_ZERO 
      port map ( O => GND ) ;
    LATCH_OUT_REG_1_SYM1 : X_INV 
      port map ( I => DATA_TRI_ENABLE(1) , O => LATCH_OUT_REG_1_G_OUT ) ;
    LATCH_OUT_REG_0_SYM1 : X_INV 
      port map ( I => DATA_TRI_ENABLE(1) , O => LATCH_OUT_REG_0_G_OUT ) ;
    N47_0_13_INV_0 : X_INV 
      port map ( I => LATCH_OUT_REG_1_G_OUT , O => N47_0_13_INV ) ;
    U34_I : X_BUF 
      port map ( I => DATA(1) , O => N65 ) ;
    U34_B : X_TRI 
      port map ( I => N47(0) , O => DATA(1) , CTL => U34_B_GTS_AND ) ;
    U34_B_GTS_AND_1 : X_AND2 
      port map ( I0 => U34_B_GTS_AND_0_INV , I1 => U34_B_GTS_AND_1_INV , 
      O => U34_B_GTS_AND ) ;
    U35_I : X_BUF 
      port map ( I => DATA(0) , O => N66 ) ;
    U35_B : X_TRI 
      port map ( I => DATA45(0) , O => DATA(0) , CTL => U35_B_GTS_AND ) ;
    U35_B_GTS_AND_2 : X_AND2 
      port map ( I0 => U35_B_GTS_AND_0_INV , I1 => U35_B_GTS_AND_1_INV , 
      O => U35_B_GTS_AND ) ;
    U36_CLKBUF : X_CKBUF 
      port map ( I => U36_CLKIO_BUFSIG , O => DATA_TRI_ENABLE(1) ) ;
    U36_CLKIO_BUF : X_BUF 
      port map ( I => READ_WRITE , O => U36_CLKIO_BUFSIG ) ;
    N47_0_DIN_3 : X_BUF 
      port map ( I => N65 , O => N47_0_DIN ) ;
    N47_0_H1_4 : X_BUF 
      port map ( I => N66 , O => N47_0_H1 ) ;
    N47_0_DFF_OUT_YMUX : X_BUF 
      port map ( I => N47_0_G , O => DATA45(0) ) ;
    N47_0_DFF_OUT_XQMUX : X_BUF 
      port map ( I => N47_0_DFF_OUT_QXLATCH , O => LATCH_OUT(0) ) ;
    N47_0_DFF_OUT_YQMUX : X_BUF 
      port map ( I => N47_0_DFF_OUT_QYLATCH , O => LATCH_OUT(1) ) ;
    N47_0_DFF_OUT_XMUX : X_BUF 
      port map ( I => N47_0_F , O => N47(0) ) ;
    N47_0_DFF_OUT_LATCHX_LATCH : X_LATCH 
      port map ( I => N47_0_H , CLK => N47_0_13_INV , SET => GND , RST => GSR , 
      O => N47_0_DFF_OUT_QXLATCH ) ;
    N47_0_DFF_OUT_LATCHY_LATCH : X_LATCH 
      port map ( I => N47_0_DIN , CLK => N47_0_13_INV , SET => GND , RST => GSR 
      , O => N47_0_DFF_OUT_QYLATCH ) ;
    N47_0_FGBLOCK_G2MUX : X_BUF 
      port map ( I => LATCH_OUT(0) , O => N47_0_FGBLOCK_1N8 ) ;
    N47_0_FGBLOCK_G3MUX : X_BUF 
      port map ( I => LATCH_OUT(1) , O => N47_0_FGBLOCK_1N7 ) ;
    N47_0_FGBLOCK_LUTRAM_FLUT_OR0 : X_OR2 
      port map ( I0 => LATCH_OUT(0) , I1 => LATCH_OUT(1) , O => N47_0_F ) ;
    N47_0_FGBLOCK_LUTRAM_GLUT_AND0 : X_AND2 
      port map ( I0 => N47_0_FGBLOCK_1N7 , I1 => N47_0_FGBLOCK_1N8 , 
      O => N47_0_G ) ;
    N47_0_HLUT_OBUF : X_BUF 
      port map ( I => N47_0_H1 , O => N47_0_H ) ;
    U34_B_GTS_AND_0_INV_5 : X_INV 
      port map ( I => DATA_TRI_ENABLE(1) , O => U34_B_GTS_AND_0_INV ) ;
    U34_B_GTS_AND_1_INV_6 : X_INV 
      port map ( I => GTS , O => U34_B_GTS_AND_1_INV ) ;
    U35_B_GTS_AND_0_INV_7 : X_INV 
      port map ( I => DATA_TRI_ENABLE(1) , O => U35_B_GTS_AND_0_INV ) ;
    U35_B_GTS_AND_1_INV_8 : X_INV 
      port map ( I => GTS , O => U35_B_GTS_AND_1_INV ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

