-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12
-- Date: Tue Jan  6 17:43:01 1998
-- Design file: time_sim.nga
-- Device: 4013xlpq160-2
----- CELL ROC -----
-- Model for  Reset-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity ROC is
    generic ( InstancePath: STRING := "*";
              WIDTH : Time := 0 ns) ;
    port( O : out std_ulogic := '1' ) ;
    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;
end ROC ;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      if (WIDTH <= 0 ns) then
         assert FALSE report
         "*** Error: a positive value of WIDTH must be specified ***"
         severity failure;
      else
         wait for WIDTH;
         O <= '0' ;
      end if;
      wait;
    end process ONE_SHOT ;
end ROC_V ;

configuration CFG_ROC_V of ROC is
    for ROC_V
    end for ;
end CFG_ROC_V ;
----- CELL TOC -----
-- Model for  Tristate-On-Configuration Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;

entity TOC is
    generic ( InstancePath: STRING := "*");
    port( O : out std_ulogic := '0' ) ;
    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;
end TOC ;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;
begin
    ONE_SHOT: process
    begin
      wait;
    end process ONE_SHOT ;
end TOC_V ;

configuration CFG_TOC_V of TOC is
    for TOC_V
    end for ;
end CFG_TOC_V ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity BIDIR_LOGIBLOX is
  port (
    READ_WRITE : in STD_LOGIC := 'X' ;
    DATA : inout  STD_LOGIC_VECTOR ( 1 downto 0 )
  ) ;
end BIDIR_LOGIBLOX ;

architecture STRUCTURE of BIDIR_LOGIBLOX is
  component ROC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  component TOC
       port ( O : out STD_ULOGIC ) ;
  end component ;
  signal N3 , BIDIR_BUSSED_PORT_INV_FF_I0_OUT , BIDIR_BUSSED_PORT_INV_FF_I1_OUT 
  , BIDIR_BUSSED_PORT_TRI_1_GTS_AND , BIDIR_BUSSED_PORT_TRI_0_GTS_AND , 
  BIDIR_BUSSED_PORT_FF_I0_D_BUF , BIDIR_BUSSED_PORT_FF_I0_G_INV , 
  BIDIR_BUSSED_PORT_FF_I1_D_BUF , BIDIR_BUSSED_PORT_FF_I1_G_INV , 
  BIDIR_BUSSED_PORT_TRI_1_GTS_AND_0_INV , BIDIR_BUSSED_PORT_TRI_1_GTS_AND_1_INV 
  , BIDIR_BUSSED_PORT_TRI_0_GTS_AND_0_INV , 
  BIDIR_BUSSED_PORT_TRI_0_GTS_AND_1_INV , GND , GSR , GTS : STD_LOGIC ;
  signal DATA_OUT : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal LATCH_OUT : STD_LOGIC_VECTOR ( 1 downto 0 );
  begin
    U12 : X_BUF 
      port map ( I => READ_WRITE , O => N3 ) ;
    U13 : X_OR2 
      port map ( I0 => LATCH_OUT(0) , I1 => LATCH_OUT(1) , O => DATA_OUT(1) ) ;
    U14 : X_AND2 
      port map ( I0 => LATCH_OUT(1) , I1 => LATCH_OUT(0) , O => DATA_OUT(0) ) ;
    BIDIR_BUSSED_PORT_INV_FF_I0 : X_INV 
      port map ( I => N3 , O => BIDIR_BUSSED_PORT_INV_FF_I0_OUT ) ;
    BIDIR_BUSSED_PORT_INV_FF_I1 : X_INV 
      port map ( I => N3 , O => BIDIR_BUSSED_PORT_INV_FF_I1_OUT ) ;
    BIDIR_BUSSED_PORT_TRI_0 : X_TRI 
      port map ( I => DATA_OUT(0) , O => DATA(0) , 
      CTL => BIDIR_BUSSED_PORT_TRI_0_GTS_AND ) ;
    BIDIR_BUSSED_PORT_TRI_1 : X_TRI 
      port map ( I => DATA_OUT(1) , O => DATA(1) , 
      CTL => BIDIR_BUSSED_PORT_TRI_1_GTS_AND ) ;
    BIDIR_BUSSED_PORT_TRI_1_GTS_AND_0 : X_AND2 
      port map ( I0 => BIDIR_BUSSED_PORT_TRI_1_GTS_AND_0_INV , 
      I1 => BIDIR_BUSSED_PORT_TRI_1_GTS_AND_1_INV , 
      O => BIDIR_BUSSED_PORT_TRI_1_GTS_AND ) ;
    BIDIR_BUSSED_PORT_TRI_0_GTS_AND_1 : X_AND2 
      port map ( I0 => BIDIR_BUSSED_PORT_TRI_0_GTS_AND_0_INV , 
      I1 => BIDIR_BUSSED_PORT_TRI_0_GTS_AND_1_INV , 
      O => BIDIR_BUSSED_PORT_TRI_0_GTS_AND ) ;
    BIDIR_BUSSED_PORT_FF_I0_D_BUF_2 : X_BUF 
      port map ( I => DATA(0) , O => BIDIR_BUSSED_PORT_FF_I0_D_BUF ) ;
    BIDIR_BUSSED_PORT_FF_I0_G_INV_3 : X_INV 
      port map ( I => BIDIR_BUSSED_PORT_INV_FF_I0_OUT , 
      O => BIDIR_BUSSED_PORT_FF_I0_G_INV ) ;
    BIDIR_BUSSED_PORT_FF_I0_INLATCH : X_LATCH 
      port map ( I => BIDIR_BUSSED_PORT_FF_I0_D_BUF , 
      CLK => BIDIR_BUSSED_PORT_FF_I0_G_INV , SET => GND , RST => GSR , 
      O => LATCH_OUT(0) ) ;
    BIDIR_BUSSED_PORT_FF_I1_D_BUF_4 : X_BUF 
      port map ( I => DATA(1) , O => BIDIR_BUSSED_PORT_FF_I1_D_BUF ) ;
    BIDIR_BUSSED_PORT_FF_I1_G_INV_5 : X_INV 
      port map ( I => BIDIR_BUSSED_PORT_INV_FF_I1_OUT , 
      O => BIDIR_BUSSED_PORT_FF_I1_G_INV ) ;
    BIDIR_BUSSED_PORT_FF_I1_INLATCH : X_LATCH 
      port map ( I => BIDIR_BUSSED_PORT_FF_I1_D_BUF , 
      CLK => BIDIR_BUSSED_PORT_FF_I1_G_INV , SET => GND , RST => GSR , 
      O => LATCH_OUT(1) ) ;
    BIDIR_BUSSED_PORT_TRI_1_GTS_AND_0_INV_6 : X_INV 
      port map ( I => N3 , O => BIDIR_BUSSED_PORT_TRI_1_GTS_AND_0_INV ) ;
    BIDIR_BUSSED_PORT_TRI_1_GTS_AND_1_INV_7 : X_INV 
      port map ( I => GTS , O => BIDIR_BUSSED_PORT_TRI_1_GTS_AND_1_INV ) ;
    BIDIR_BUSSED_PORT_TRI_0_GTS_AND_0_INV_8 : X_INV 
      port map ( I => N3 , O => BIDIR_BUSSED_PORT_TRI_0_GTS_AND_0_INV ) ;
    BIDIR_BUSSED_PORT_TRI_0_GTS_AND_1_INV_9 : X_INV 
      port map ( I => GTS , O => BIDIR_BUSSED_PORT_TRI_0_GTS_AND_1_INV ) ;
    GND_10 : X_ZERO 
      port map ( O => GND ) ;
    ROC_NGD2VHDL : ROC 
      port map ( O => GSR ) ;
    TOC_NGD2VHDL : TOC 
      port map ( O => GTS ) ;
end STRUCTURE ;

