------------------------------------------------------
-- LogiBLOX DP_RAM Module "lb_dp_ram"
-- Created by LogiBLOX version M1.3.7
--    on Wed Sep  3 07:59:50 1997
-- Attributes 
--    MODTYPE = DP_RAM
--    BUS_WIDTH = 4
--    DEPTH = 16
--    MEMFILE = lb_memfile
------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;

ENTITY lb_dp_ram IS
  PORT(
    A: IN std_logic_vector(3 DOWNTO 0);
    DI: IN std_logic_vector(3 DOWNTO 0);
    WR_EN: IN std_logic;
    WR_CLK: IN std_logic;
    DPRA: IN std_logic_vector(3 DOWNTO 0);
    SPO: OUT std_logic_vector(3 DOWNTO 0);
    DPO: OUT std_logic_vector(3 DOWNTO 0));
END lb_dp_ram;

ARCHITECTURE sim OF lb_dp_ram IS
  SIGNAL GSR: std_logic := '1';
  TYPE mem_data IS ARRAY (15 DOWNTO 0) OF std_logic_vector(3 DOWNTO 0);
BEGIN
  PROCESS
  VARIABLE VD: mem_data;
  VARIABLE first_time: BOOLEAN := TRUE;
  BEGIN
    IF (first_time) THEN
      VD(0) := ('0','0','0','0');
      VD(1) := ('0','0','0','1');
      VD(2) := ('0','0','1','0');
      VD(3) := ('0','1','0','0');
      VD(4) := ('1','0','0','0');
      VD(5) := ('1','1','0','0');
      VD(6) := ('1','0','1','0');
      VD(7) := ('1','0','0','1');
      VD(8) := ('1','0','0','1');
      VD(9) := ('1','0','1','0');
      VD(10) := ('1','1','0','0');
      VD(11) := ('1','0','0','1');
      VD(12) := ('1','0','0','1');
      VD(13) := ('1','1','0','1');
      VD(14) := ('1','0','1','1');
      VD(15) := ('1','1','1','1');
      first_time := FALSE;
    END IF;
    IF (WR_CLK'EVENT AND stdbit2mvl(WR_CLK)='1' AND stdbit2mvl(WR_CLK'LAST_VALUE)='0')
    AND (WR_EN='1') AND (NOT mvlvec_not01(A)) THEN
      VD(mvlvec2int(A)) := stdvec2mvl(DI);
    END IF;
    IF (mvlvec_not01(A) OR
       (stdbit2mvl(WR_CLK) = 'X')
       OR (WR_CLK'EVENT AND stdbit2mvl(WR_CLK)='1' AND stdbit2mvl(WR_CLK'LAST_VALUE)='0'
           AND stdbit2mvl(WR_EN) = 'X' )
      ) THEN
      SPO <= ('X','X','X','X');
    ELSE
      SPO <= VD(mvlvec2int(A));
    END IF;
    IF (mvlvec_not01(DPRA)) THEN
      DPO <= ('X','X','X','X');
    ELSE
      DPO <= VD(mvlvec2int(DPRA));
    END IF;
      WAIT ON A, DI, WR_EN, WR_CLK, DPRA, GSR;
  END PROCESS;
END sim;
