------------------------------
-- COUNT4.VHD Version 1.0   --
-- Code for a 4-bit Counter --
-- September 1997           --
------------------------------

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity count4 is
    port (LOAD, CLOCK: in  STD_LOGIC;
          CE, RST:     in  STD_LOGIC;
          DATA:        in  STD_LOGIC_VECTOR (3 downto 0);
          COUT:        out STD_LOGIC_VECTOR (3 downto 0));
end count4;

architecture BEHAVIOR of count4 is

    signal QOUT: STD_LOGIC_VECTOR (3 downto 0);

    begin
    process (RST, CLOCK, LOAD, CE)
    begin
        if (RST = '1') then
            QOUT <= "0000";
            elsif (CE = '1') then
                if (CLOCK'event and CLOCK = '1') then
                    if (LOAD = '1') then
                        QOUT <=DATA;
                    else QOUT <= QOUT + 1;
                    end if;
                end if;
        end if;
    end process;

    COUT <= QOUT;

end BEHAVIOR; 
