Release Notes for Xilinx-ABEL Interface Version 1.5.0

The XABEL Interface translates ABEL-HDL language source files (.abl) into EDIF 
2.0.0 netlists compatible with the Xilinx Version 1.5 Design Implementation 
software. This document describes installation, known issues and design flows.

This Xilinx-ABEL Interface can be used in 2 ways:

1. To add ABEL design translation capability to Xilinx Alliance Version 1.5
   implementation software.

2. If you update the implementation software in an existing Foundation 1.4 
   installation with Alliance version 1.5 implementation software, you must
   also update the XABEL Interface to version 1.5.0 for compatibility.

Note: This XABEL Version 1.5.0 Interface should not be used in conjunction 
with any version of Xilinx Implementation software other than Version 1.5.

CAPABILITIES

· Runs on Windows-NT and Windows-95 PCs. (There are no UNIX-compatible versions 
  of XABEL available.)
· XABEL source files are developed using a text editor or the Xilinx Foundation 
  HDL Editor. 
· The XABEL Interface is based on the Synario ABEL Version 6 compiler and 
  supports ABEL6 hierarchical designs. 
· XABEL supports all Xilinx device families, including FPGAs and CPLDs. 
· XABEL supports compilation of macros for use in schematic-based designs and 
  stand-alone top-level ABEL designs for all device families.
· XABEL supports several "Xilinx Properties" for controlling design 
  implementation (see details below).
· This version of XABEL Interface also supports translation into the obsolete 
  Plusasm equation file format (.PLD) for existing CPLD designs. (See details 
  at the end of this Release Note.)

Note: Xilinx does not provide any software tools for automatically generating 
a symbol for an ABEL module for use in any schematic capture tool other than 
the Xilinx Foundation schematic tool.

INSTALLATION AND CONFIGURATION

This XABEL interface contains an InstallShield-based installer (Setup.exe). 
The following requirements apply:

· XABEL must be installed into the same directory as Xilinx Design 
  Implementation software, version 1.5 (either Alliance or Foundation), 
  as specified by your XILINX environment variable.
· The XABEL installer automatically updates your Windows registry with the 
  required directory locations of the XABEL compiler. 
· If you are not using Xilinx Foundation software, you can download the 
  Foundation on-line help files that include useful information about 
  the ABEL-HDL language and CPLD ABEL design techniques, from the Xilinx 
  web site (www.xilinx.com) in the Support -> File Download -> Software 
  Help -> Foundation area, filename fnd_help.zip.
· You can also look for the latest Xilinx Application Note on using XABEL 
  on the Xilinx web site (www.xilinx.com) in the Support ->
  Application Notes -> All XAPP Application Notes area.

KNOWN ISSUES

· The XABEL Interface may not run if installed to a network drive on some 
  networks. You may need to install both the XABEL Interface and the Xilinx 
  Implementation software onto your local PC hard drive.

· Large equations containing comparators/decoders may cause ABEL to fail.
    Reference #101032
  Comparators and decoders of the form A==B or A==constant could cause very 
  large logic tables to be generated, especially when combined with other logic
  in the same equation. As a result, the BLIFOPT step may run for a very long 
  time and the BLIF2NET step may fail or just never finish. To remedy this 
  problem, insert the following ABEL directive at the top of your declaration
  section or before the problematic equation:

    @carry 2;

  This will cause the ABEL compiler to break up the large equation into a 
  number of smaller intermediate nodes, which can then be translated into
  EDIF more efficiently. The Xilinx Implementation software will optimize the
  logic across the intermediate nodes.

IMPROVEMENTS IN XABEL VERSION 1.5.0

The following have been improved since the XABEL Version 1.4 release:

· A problem occurred when XABEL Version 1.4 (or earlier) and an ABEL compiler 
  from another vendor's software product were installed on the same PC. Either
  XABEL or the other ABEL compiler would fail due to conflicts between the
  products in the Windows registry or the OLE communications server. XABEL
  Version 1.5.0 can now be installed on the same PC with other ABEL compilers.
  (This was Xilinx reference #100262.)

· The OLE communication server used in XABEL Version 1.4 caused failures or
  crashes on some Windows 95 systems. XABEL Version 1.5.0 no longer invokes
  or depends on the OLE server.

· The BLIF2NET step in XABEL Version 1.4 failed with an internal error message
  for some ABEL designs. These internal errors have been resolved in XABEL
  Version 1.5.0. (This was Xilinx reference #100795.)

· Some registers in CPLD designs initialize to the opposite power-on state.
  In a CPLD design, flip-flops with asynchronous preset (.AP equations) and 
  without asynchronous reset (.AR) powered-up to the opposite state than 
  specified. This has been fixed. (This was Xilinx reference #17742.)

DESIGN FLOW

If you are using Xilinx Foundation software, follow the standard procedures 
described in the Foundation on-line help for running ABEL designs. 
If you are using Xilinx Alliance software (version 1.5), use the following 
procedure to prepare an XABEL macro or top-level design, translate it to an 
EDIF netlist and run the Implementation software:

· The module name specified in each ABEL file must match the name of the file. 
  For example, if your file is named myfile.abl, it must contain 
  "module myfile" at the top.
· Open a DOS window and CD to the directory containing your ABEL source file.
· Execute the abl2edif command as follows:
    abl2edif -s <level> <module_name>
  where <level> is "top" for top-level ABEL design, or "mod" (default) for 
  module to use in a schematic. The abl2edif program generates the following 
  output files:
    abl2edif.log: log file of program execution
    <module_name>.edn: output EDIF netlist
    <module_name>.err: error log from program execution
    <module_name>.smx: simulation output file (if the design contains test 
      vectors)
    <module_name>.tmv: test vector file for XC9500 functional test (if the 
      design contains test vectors)
· If you are preparing a module for a schematic design, your schematic must 
  contain a symbol with the attribute "FILE=<module_name>.edn". When you run 
  the implementation software, the translate step will automatically read in 
  the EDIF module as part of your design.
· If you are preparing a top-level ABEL design, open a new project in the 
  Xilinx Design Manager and enter (or Browse for) the <module_name>.edn file in 
  the Input Design box.
· If you included test vectors in your top-level ABEL source design, you can 
  embed those test vectors into your XC9500 JEDEC programming file for 
  functionally testing the device. Enter (or Browse for) the file
  <design_name>.tmv in the JEDEC Test Vector File box in the Programming tab
  of the XC9500 Implementation Options template.

XILINX PROPERTIES AVAILABLE IN XABEL

You can specify the following attributes in your XABEL source file using the 
"XILINX PROPERTY" statement:

· XILINX PROPERTY '{FAST | SLOW} output_pin...';
    Selects output slew rate for output pins in top-level XABEL designs.
· XILINX PROPERTY 'BUFG={CLK | OE | SR} input_pin...';
    Assigns global buffers to input pins in top-level XABEL CPLD designs.
· XILINX PROPERTY 'INIT={R | S} reg_signal...';
    Defines initial state of registers for CPLD designs.
· XILINX PROPERTY 'PWR_MODE={LOW | STD} signal_name...';
    Selects macrocell power mode for nodes or outputs in CPLD designs.
· XILINX PROPERTY 'TNM=string signal_name...';
    Tags signals with a Timing-group Name to be used in a Timespec.
· XILINX PROPERTY 'BLOCK {reg_signal | state_name} attrib_name[=attrib_value]';
    Assigns arbitrary Xilinx-compatible attributes to registers in the design.
· XILINX PROPERTY 'BLOCK signal_name LOC=FBnn';
    Assigns signal to function block nn to use XC9500 local feedback routing.
· XILINX PROPERTY 'OPTIMIZE {AREA | SPEED | BALANCE | OFF}';
    Selects OPTX optimization strategy for FPGA XABEL modules (default=BALANCE).
· XILINX PROPERTY 'OPT_EFFORT {NORMAL | HIGH}';
    Selects OPTX optimization effort for FPGA XABEL modules.

The following ABEL attributes are automatically forwarded to the Implementation 
software via the EDIF netlist:

· ISTYPE 'KEEP'
    Preserves internal nodes in both ABEL compiler and design implementation.
· ISTYPE 'RETAIN'
    Preserves redundant logic terms in both ABEL and CPLD design 
    implementation. Also identifies the output node of a combinatorial
    feedback loop.

In addition, pin numbers specified in top-level XABEL designs are written to 
the EDIF netlist as pin location (LOC) constraints for design implementation.

XABEL PLUSASM FLOW FOR CPLD DESIGNS

If you have an existing XABEL CPLD design that contains XEPLD PROPERTY or 
PLUSASM PROPERTY statements, you must either replace these properties with the 
supported EDIF-compatible properties listed above or you must use the 
Plusasm flow described below. If your existing design does not contain Plusasm 
based properties, you should be able to use the new EDIF-based flow described 
earlier. If you are developing a new XABEL CPLD design, DO NOT USE Plusasm 
based properties. If you use the Plusasm flow, you cannot use any of the 
XILINX PROPERTY statements described above.

   PLUSASM LANGUAGE WILL NO LONGER BE ACCEPTED FOR DESIGN ENTRY IN LATER 
   RELEASES OF XILINX DESIGN IMPLEMENTATION SOFTWARE.

If you are using Xilinx Foundation software (version 1.5) to prepare an XABEL 
top-level design containing Plusasm properties, follow the special procedure 
for the Plusasm XABEL Flow described in the Foundation Release Document. If you 
are using Xilinx Alliance software (version 1.5), use the following procedure 
to prepare an XABEL macro or top-level design, translate it to a Plusasm 
equation file (.pld) and run the Implementation software: 

· The module name specified in each ABEL file must match the name of the file.
  For example, if your file is named myfile.abl, it must contain 
  "module myfile" at the top.
· Open a DOS window and CD to the directory containing your ABEL source file.
· Execute the abl2pld command as follows:
    abl2pld -s <level> <module_name>
  where <level> is "top" for top-level ABEL design, or "mod" (default) for 
  module to use in a schematic. The abl2pld program generates the following 
  output files:
    abl2pld.log: log file of program execution
    <module_name>.pld: output Plusasm equation file
    <module_name>.err: error log from program execution
    <module_name>.smx: simulation output file (if the design contains test 
      vectors)
    <module_name>.tmv: test vector file for XC9500 functional test (if the 
      design contains test vectors)
· If you are preparing a module for a schematic design, your schematic must 
  contain a symbol with the attribute "FILE=<module_name>.pld". When you run 
  the implementation software, the translate step will automatically read the 
  Plusasm equation file in as part of your design.
· If you are preparing a top-level ABEL design, open a new project in the 
  Xilinx Design Manager and enter (or Browse for) the <module_name>.pld file in 
  the Input Design box.
· If you included test vectors in your top-level ABEL source design, you can 
  embed those test vectors into your XC9500 JEDEC programming file for 
  functionally testing the device. Enter (or Browse for) the file
  <design_name>.tmv in the JEDEC Test Vector File box in the Programming tab
  of the XC9500 Implementation Options template.
