Xilinx at Work - HDLC Controllers
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Xilinx Solution SummaryThe acceptance of the Internet has led to a dramatic rise in data traffic. To successfully transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in layer 2 of the industry standard communication reference model called OSI (Open Systems Interconnection). HDLC is the most commonly used layer 2 protocol and is a bit-oriented synchronous data link layer protocol developed by the International Standards Organization (ISO). The HDLC is based on IBM Corporation's Synchronous Data Link Control (SDLC) protocol and specifies a data encapsulation method on synchronous serial links using frame characters and checksums. The HDLC Controllers operation includes handling the bit oriented protocol structure and formatting data as per packet switching protocol defined in the X.25 recommendations of the CCITT. It includes transmitting and receiving the packeted data serially, while providing the data transparency through zero insertion and deletion. These controllers generate and detect flags that indicate the HDLC status. They provide 16-/32-bit CRC on data packets using the CCITT defined polynomial, and recognize the single byte address in the received frame. Using SpartanTM-II FPGAs, and the HDLC AllianceCORETM solutions from Memec Design Services and CoreEl MicroSystems, Xilinx is able to provide a highly flexible and lower cost solution than equivalent ASSPs (Application Specific Standard Products). The chart below shows a comparison of a Spartan-II based HDLC solution versus a traditional ASSP HDLC solution. Two HDLC Controllers are available for immediate use through the AllianceCORE program.
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Xilinx at Work |