Floorplanner II: Effective Layout (2.1i)

Audience
Intermediate VHDL, Verilog, Xilinx design, and basic design. Customer could have completed one small slow design in VHDL or Verilog using Foundation or Alliance. Alternatively, students may have completed a class on VHDL or Verilog.

Prerequisites
Floorplanner I: Viewing Your Design

What is the level of the material?
Level III - Advanced 

Training Duration
1 hour

Content Description
Focuses on solutions to common layout problems experienced by designers of fast, large circuits. A fast circuit has a system clock frequency of 40 MHz. 

Objectives
After completing this training, student will be able to:

• Layout pins to promote high speed and reduce ground bounce
• Improve timing delays and routability
• Work around some specific limitations of the MAP and PAR programs 

Topics or Training Outline

Overview
Layout Tips for Input/Output Blocks
Layout Tips for Internal Logic
MAP & PAR Limitations
Summary

References:
Flooplanner Reference guide has excellent example of interleaved data path
Solution records (answers database)

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