SAN Jose, Calif., June 28, 1999––Xilinx, Inc. (NASDAQ: XLNX) announced today the availability of the WebPACK suite—a new, integrated design environment specifically tailored for the XC9500 CPLD series. This suite of tools, is a collection of three free, downloadable modules: (1) VHDL, Verilog, and ABEL synthesis, (2) device fitter tools, and (3) device programming. Each module may be used separately with existing EDA tools or used in combination to create an integrated CPLD environment. This approach offers engineers complete flexibility when designing with Xilinx. 

In addition, Xilinx also announced a new release of its groundbreaking WebFITTER product. This on-line CPLD evaluation system now includes a new release of ABEL, version 7.1, additional synthesis technology, and on-line price quotes. Both of these solutions strengthen the Silicon Xpresso initiative launched by Xilinx last year. 

"Xilinx is the first programmable logic supplier in the industry to offer full VHDL, Verilog, and ABEL synthesis downloadable from the web," said Evert Wolsheimer, vice president and general manager of the CPLD Business Unit. "The combination of WebFITTER and WebPACK tools enables Xilinx to further penetrate the CPLD market by leveraging the Internet and an existing ABEL installed base." 

Putting new technology to work

Both the WebFITTER and the WebPACK tools incorporate technology acquired from MINC+Synario. Xilinx has made several key updates to both the project navigator and ABEL and has introduced Xilinx Synthesis Technology product specifically for the XC9500 CPLD series. Enhancements to the ABEL language focused on improved design flows and overall reliability. 

"Acquiring these key technologies from MINC+Synario has allowed us to focus the Xilinx Synthesis Technology team to deliver significant optimization improvements in both utilization and performance," said Rich Sevcik, senior vice president and general manager of software, cores and support. 

Xilinx is also working with third parties to allow EDA and other programmable logic suppliers to license the latest version of ABEL, v7.1 via the OEM channel. The ABEL language is still a widely used HDL for CPLDs and simple PLDs such as PALs and GALs. With respect to that, Xilinx is creating an OpenABEL consortium that will govern the direction and enhancement of the ABEL language. Xilinx will place ABEL into the OEM channel and create the OpenABEL consortium later this year. 

The WebPACK suite: modular CPLD design

Xilinx offers three distinct downloadable modules. The XC9500 HDL-ABEL Synthesis Tools module, enhanced specifically for the XC9500 series, incorporates the industry’s most widely used project navigation system with the updated version of ABEL, coupled with VHDL and Verilog synthesis (XST). The XC9500 Device Fitter Tools module includes the Xilinx implementation tools for CPLD device optimization and timing driven fitting. This set of tools can run with existing synthesis and schematic capture tools or can be implemented from within the WebPACK synthesis and ABEL environment. This module also includes the Constraints Editor, Interactive Timing Analyzer, and new CPLD ChipViewer tools. The Device Programming Tools module contains programming software that allows for full IEEE 1149.1 JTAG programming on any Xilinx CPLD or FPGA. Together, the WebPACK suite presents an integrated flow allowing designers to go from entry, synthesis, and optimization to device fitting and programming all from within a single environment. 

The WebFITTER road test for designing over the Internet

The WebFITTER tool allows designers to submit any VHDL, Verilog, ABEL, EDIF or XNF file for an evaluation within minutes. The WebFITTER tool will also accept input from other programmable logic vendors. Users can target their design specifically by density, package, speed, and voltage or choose automatic device selection. Users can peruse the utilization and timing reports, view data sheets, and get instant price quotes—all on-line. For further verification, the WebFITTER tool provides HDL timing simulation models as well as a JEDEC programming file. All of the reports, timing models, and device and programming files are available for immediate download. 

Availability

The WebFITTER tool is available on-line at www.xilinx.com/sxpresso/webfitter.htm. The WebPACK suite is available for immediate download at www.xilinx.com/sxpresso/webpack.htm. 

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and commands more than half of the world market for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

Xilinx is a registered trademark. All XC-prefix, WebFITTER, WebPACK, Constraints Editor, ChipViewer, OpenABEL, and Xilinx Synthesis Technology are trademarks of Xilinx, Inc. Other brands or product names are trademarks or registered trademarks of their respective owners.
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Editorial contact:	Marketing Contact:
Ann Duft	David Grace
Xilinx, Inc.	Xilinx, Inc.
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