FOR IMMEDIATE RELEASE
SAN JOSE, Calif., January 19, 1999 –Anticipating market requirements for lower power and higher performance, Xilinx, Inc., (NASDAQ:XLNX), today announced the new XC9500XV family, the industry's first 2.5-volt complex programmable logic devices (CPLDs). The XC9500XV family provides power savings of 75 percent over current 5-volt CPLDs. The new XC9500XV lower power devices also will be available in miniature 48-pin and 144-pin chip-scale packages that are ideal for small form factor, high volume applications such as handsets and PCMCIA cards. High Performance Through Advanced Process Technology Manufactured on the latest generation FastFLASH process, the new XC9500XV CPLDs provide the same advanced architectural features and densities as the popular 3.3-volt XC9500XL family introduced last year, with device offerings of 36, 72, 144 and 288 macrocells. High performance versions offering pin-to-pin delays as low as 3.5 nanoseconds and system frequencies as fast as 225 MHz will be available later this year. The 2.5-volt XC9500XV devices are optimized for in-system programming (ISP), featuring the industry's most extensive IEEE 1149.1 JTAG support. This capability streamlines the manufacturing, testing and programming of CPLD-based electronic products. The new XC9500XV family will also be supported by the soon-to-be released Java API for Boundary Scan programming standard. “The introduction of the XC9500XV family once again demonstrates our commitment to lead the market,” said Evert Wolsheimer, vice president and general manager of the Xilinx CPLD Business Unit. “We now offer a complete 2.5-volt programmable logic solution to our customers, from the 36-macrocell XC9536XV CPLD to the one-million gate Virtex XCV1000 FPGA.” First CPLD for System Designers The advanced architecture of the XC9500XV family allows for easy design implementation, permitting designers to concentrate on system design rather than on chip-level details. Unique features of the XC9500XV family include a 54-input block fan-in which contributes to superior pin-locking capability; built-in input hysteresis for improved noise margin; bus-hold circuitry for better I/O control; hot plugging to eliminate the need for power sequencing; and local/global clock control to provide maximum flexibility to each individual macrocell. The XC9500XV family is fully supported by Xilinx Foundation Series and Alliance Series software packages as well as the recently announced Xilinx WebFITTER tool. Pricing and availability Engineering samples of the XC95144XV devices are available now. The XC9536XV, XC9572XV and XC95288XV devices are planned to be available in the second quarter of 1999. The XC9500XV family will be aggressively priced up to 20 percent lower than the 3.3-volt XC9500XL family.
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