Frankie Borison
Oak Ridge Public Relations
(408) 253-5042
frankie@oakridge.com

FOR IMMEDIATE RELEASE

 
SAN JOSE, Calif.—October 20, 1997—Xilinx, Inc., (NASDAQ:XLNX), the world leader in CMOS programmable logic devices, today announced a new family of HardWire devices, the Xilinx XH3 HardWire ASIC series. The industry’s first FPGA-specific ASIC family (FpgASIC) provides the fastest way to a high-volume, low-cost ASIC solution with a turnkey, guaranteed conversion process.

The XH3 architecture consists of an area-efficient, high performance sea-of-gates core, the Xilinx specific I/O ring, JTAG support, and logic to emulate the FPGA configuration modes built into the base silicon. It also supports the unique features of the popular Xilinx XC4000 and XC5000 FPGA families. The XH3 family is based on advanced 0.5 micron 5-volt CMOS technology and is fully PCI-compatible. The initial XH3 family consists of six devices ranging in density from 15,000 to 225,000 gates allowing designers to convert the highest density XC4000EX designs even with large amounts of user RAM.

"Xilinx is the only FPGA supplier offering ASIC solutions specifically for FPGA conversions," said Chuck Fox, vice president and general manager of the Xilinx HardWire business unit. "We’ve developed the FpgASIC family to specifically match the characteristics of Xilinx FPGA devices. This allows the combined advantage of FPGA design flexibility and no-risk, turnkey ASIC conversion for the fastest time-to-market and lowest silicon cost."

The XH3 series solves incompatibility problems associated with conventional ASICs. By providing a seamless path from Xilinx FPGAs, the XH3 ASIC family eliminates the need for customer logic redesign, re-verification, and test vector generation normally required for ASIC re-targeting. With HardWire, customers benefit from having an exact feature and technology match in converting FPGAs to ASICs. Silicon overhead is reduced by having circuitry already built into the base silicon, such as JTAG and configuration control, instead of circuitry that is traditionally "added in" to the design. This provides an optimally small die size and lowest cost.

"Xilinx FPGAs are at the very core of some of Tellabs’ most successful T1 and E1 products," said Bruce Bina, senior design engineer at Tellabs Operations, Inc., a leading supplier in telecommunications equipment. "Our last design was converted to a Xilinx HardWire device without any intervention on our part, as advertised by Xilinx, with first-pass success. Our engineering resources were freed up to continue further product development and Tellabs was able to take advantage of the significant cost savings. I have every confidence in the newest HardWire technology enhancement from Xilinx."

"Research shows that verification is one of the biggest concerns for the ASIC user considering the use of IP cores for system-on-a-chip designs," said Rich Sevcik, senior vice president of software at Xilinx. "As use of larger and faster FPGAs becomes more pervasive, designers can now fully verify their designs in silicon using the FPGA and move to production with the new XH3 family. Designers can then focus on the next-generation product while Xilinx manages the conversion for them. Xilinx is the only supplier that can offer this solution."

The new family also offers full support of Xilinx LogiCORE functions, including PCI.

Xilinx HardWire ASICs and the associated conversion process were developed and patented by Xilinx to provide customers with a rapid, turnkey solution for mask-programmed conversion. The HardWire DesignLock™ Conversion Process is an automatically mapped and verified process provided by Xilinx—the only programmable logic supplier with an in-house ASIC capability with Xilinx. No third-party ASIC redesign is required.

Pricing and Availability

Xilinx HardWire ASIC family now provides this unique mask-programmed conversion capabilities with chip costs that are competitive with present high-volume 0.5 and 0.35 micron gate-arrays from the leading manufacturers. For example, a 50,000-gate equivalent XH304 device is priced at $6.50 in quantities of 250,000 units per year. Non-recurring engineering (NRE) charges start at $19,000. The XH304 devices can be used for XC4036EX FPGA design conversions. Lead-times for conversion and prototype build are five to six weeks for typical designs.

Since 1986, Xilinx has performed almost 800 conversions and is the market leader in FPGA–to–ASIC conversions. Xilinx maintains multiple design centers staffed with expert Xilinx application engineers. Xilinx is committed to providing the only total life-cycle solution by continuing to invest in a state-of-the-art in-house HardWire program.

Founded in 1984, Xilinx is the world’s largest supplier of programmable logic solutions producing industry–leading device architectures and world class design software. Headquartered in San Jose, Calif., the company pioneered the market for field programmable gate array (FPGA) semiconductor devices that provide high integration and quick time-to-market for electronic equipment manufacturers in the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer electronics markets. For more information on Xilinx, access the worldwide web site at www.xilinx.com.

Note to editors: Xilinx is a registered trademark of Xilinx, Inc. All XC-prefix product designations, HardWire, DesignLock, and LogiCORE are trademarks of Xilinx, Inc. Other brands or product names are trademarks or registered trademarks of their respective owners.
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