HDL Synthesis & Simulation

Application Notes

Title	Size	Design Files
XAPP164: Using Xilinx and Synplify for Incremental Designing (ECO)	40 KB	PC UNIX
XAPP165: Using Xilinx and Exemplar for Incremental Designing (ECO)	70 KB	PC UNIX
XAPP166: TAU/BLAST Support in 2.1i	25 KB	-
XAPP107: Synopsys/Xilinx High Density Design Methodology Using FPGA Compiler	240 KB	-
Synplify Guide for Model Technology - ModelSim	110 KB	-
Xilinx/Exemplar Large Device Design Methodology	400 KB	-
Xilinx/Synplicity High Density Methodology	140 KB	-
Synthesis and Simulation Design Guide	1.7 MB	Verilog VHDL Both Source WS 50 KB 50 KB 100 KB PC 60 KB 60 KB 120 KB
Synopsys (XSI) Synthesis and Simulation Design Guide	1.8 MB	Verilog VHDL Both Source WS 50 KB 50 KB 100 KB PC 60 KB 60 KB 120 KB Source + Implementation WS 5 MB 6 MB 11 MB PC 3 MB 4 MB 7 MB
XAPP108: Chip-Level HDL Simulation Using the Xilinx Alliance Series	200 KB	-
CPLD Synthesis Design Guide	310 KB	-
XAPP105: A CPLD VHDL Introduction	60 KB	-
Xilinx/Concept-HDL Interface Guide	320 KB	-

Tutorials 

Title	Size
Exemplar/ModelSim Tutorial for CPLDs	300 KB
Mentor Schematic Design Tutorial	1 MB
OrCAD/ModelSim Tutorial for CPLDs	200 KB
Synopsys Design Compiler/FPGA Compiler/ModelSim Tutorial for CPLDs	200 KB
Synplify/ModelSim Tutorial for CPLDs	200 KB
Workstation Flow for Xilinx CoolRunner CPLDs	50 KB
Download associated PC design files for VHDL and Verilog

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Xcell Articles

Title	Issue
HDL Advisor: Questions and Comments from Our Readers	Q2 '99
FPGA Synthesis with Exemplar: Where We've Been, Where We're Going	Q2 '99
FPGA Technology Drives Design Software Revolution - VeriBest	Q2 '99
Integrate FPGA & System Design Using Concept HDL	Q2 '99
Prototyping ASICs Using Xilinx FPGAs and Certify	Q2 '99
The Increasing Importance of HDL Verification	Q2 '99
Using Relative Location Constraints in Synplify	Q2 '99
Inferring Virtex Block RAM with Leonardo Spectrum	Q2 '99
Verilog CBT - New Computer-Based Training	Q2 '99
HDL Advisor: Creating the Most Efficient Comparators	Q1 '99
Concept HDL - A New Standard	Q1 '99
Hierarchy Management in Synplify	Q1 '99
Using the Xilinx Verilog Flow for Efficient High Speed Design	Q1 '99
HDL Advisor: Using Nested If Statements	Q4 '98
Inferring RAM in Synplify	Q4 '98
Upgraded PLSynthesizer Supports High Density Xilinx FPGAs	Q4 '98
Special XCell 29 Section: HDL Verification	Q3 '98
Synplify Extends Timing Constraint Control for Mixed Entry	Q3 '98
Looking for the Best HDL Design Flow?	Q3 '98
HDL Advisor: How to Use the Clock Enable Pin Instead of Gated Clocks in HDL Designs	Q3 '98
HDL State Machine Technique	Q3 '98
High Level Design Tips for Synopsys FPGA Express	Q2 '98
Reduce Compile Times Using Timing Constraints in Foundation Express	Q2 '98
HDL Analyst - A Unique Tool for Visualizing Synthesis Results	Q2 '98
RAM Inference Using Exemplar Logic's Leonardo	Q2 '98
Synplify - Achieving Optimal Results	Q1 '98
New UNISIM Libraries for Functional VHDL and Verilog Simulations	Q1 '98
HDL Synthesis and Built-In Clock Enables	Q2 '96

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