Coding Tips for Spartan Devices I v2.1i

Software & Version
Independent

Audience
Beginning level HDL designers. FPGA design experience is not needed, familiarity with FPGA components is recommended.

Prerequisites
Students should have completed a design in an FPGA OR Spartan/XC4000 architecture-training course. Familiarity with HDL; student needs to be able to read VHDL or Verilog code.

What is the level of the material?
Level I - Beginning

Training Duration
1 hour

Content Description
This module focuses on coding issues that greatly affect Spartan designs. Tips for coding combinatorial logic, I/O, and memory using Foundation Express or FPGA Express synthesizers.

Objectives
After completing this training, student will be able to:

Use Foundation Express or Synopsys' FPGA Express to:

• Effectively infer combinatorial logic , I/O, and memory
• Infer or instantiate logic based on your applications

Topics or Training Outline

Cross -reference to HDL Coding Styles Manual
Combinatorial Logic
Case vs. If statements
Tri-States
RAM
Input/Output synthesis or instantiation
IOs

Supporting Files
Paper exercise labs, regular labs, lab files, HDL Coding Styles (online doc). www.support.xilinx.com may also be needed.

References
HDL Coding Style Guide
Search of www.support.xilinx.com
Other modules
Tutorials
Xcell articles

Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s)
Demo
Review questions x
Test x