Coding Tips for Spartan
Devices II v2.1i
Software & Version
Independent
Audience
Beginning level HDL designers. FPGA design experience is not needed, familiarity
with Spartan FPGA architecture is recommended. Familiarity with timing
constraints is recommended.
Prerequisites
Prior simple, slow design in and FPGA OR basic Spartan/XC4000 architecture
training course. Familiarity with HDL; student needs to be able to read
VHDL or Verilog code. Attendance at the FPGA Tools class or similar class
is recommended.
What is the level of the
material?
Level I - Beginning
Training Duration
1 hour
Content Description
HDL Coding part I focuses on coding issues that greatly affect Xilinx
designs. Xilinx tools such as HDL Editor, and Xilinx Reports are used
to illustrate the coding issues. Xilinx Tools should be maintained in
separate sections within the module. Covers common user problems.
Objectives
After completing this training, student will be able to:
Use Foundation Express or FPGA
Express to:
- Infer simple registered
logic in design
- Effectively create state
machines and counters
Topics or Training Outline
Internal Spartan Register
Resources
Tips for Registered functions including state machines and counters
Note that some topics
may cross over to advanced section
Supporting Files
Paper exercise labs, regular labs, lab files, HDL Coding Styles (online
doc). www.support.xilinx.com may also be needed
References
HDL Coding Style Guide
Search of www.xupport.xilinx.com
Other modules
Tutorials
Xcell articles
Teaching Activities
Structured Discussion x
Paper exercise(s) x
Lab exercise(s)
Demo
Review questions x
Test x
Lecture to introduce a topic
and define basic code. Paper Exercises so participants will work though
common situations. Example: VHDL and Verilog unintended latch code
is given. Customer will sketch resulting circuit. Then he/she will fix
the code. (Did not include based on timing tests; unnecessary latches
are an advanced issue only for area critical designs only).
Labs to show how to debug a
problem from reports, fix design and then re-implement. Demo/paper exercise
can be completed in place of lab. Lab will be a separate module.
Comments
Please review the Focus Group definition of the 2 HDL classes. Topics
including tool usage should be kept in together, if possible.
|
