Timing Constraints I v2.1i

Audience
Audience has no FPGA design experience.

Prerequisites
Audience needs to understand basic FPGA architecture.

What is the level of the material?
Level I - Beginning

Training Duration
1 hour

Content Description
This training material focuses on placing basic timing constraints on an FPGA design using the Constraints Editor.

Objectives
After completing this training, student will be able to:
Apply basic timing constraints to a simple synchronous design,
Specify basic timing requirements and pin assignments with the Constraints Editor. 

Topics or Training Outline

• Basic Timing Constraints
• The value of Basic Timing Constraints
• The Period, Offset, and Pad-to-Pad Constraints
• Pin Assignments
• Pin Assignment guidelines
• Making Pin Assignments in the Constraints Editor
• Using the Constraints Editor for making Timing Constraints
• Making a Period, Offset, and Pad-to-Pad Constraint