Timing Constraints II
v2.1i
Software & Version:
Foundation 1.5I and Alliance 1.5i
Audience
Audience has no FPGA experience, but has completed the Timing Constraints
I module.
Prerequisites
Audience needs to understand basic FPGA architecture and completed the
Timing Constraints I module.
What is the level of the
material?
Level II - Intermediate
Training Duration
1 hour
Content Description
This module focuses on placing path specific timing constraints on an
FPGA design using the Constraints Editor. Applications such as grouping
logic, constraining multi-clock domains, and grouping Offset In/Out constraints
are covered.
Objectives
After completing this training, student will be able to:
- Apply path specific timing
constraints to specific design applications.
- Specify path specific timing
requirements with the Constraints Editor.
Topics or Training Outline
Introduction
Creating Groups
Creating Offset In/Out Groups
Inter-Clock Domain Constraining
Summary
Supporting Files
Const2.ppt
References
Refer to the Timing Presentation on the web or on the DataSource CD. Use
the command: Library tab -> Technical Tips -> Timing & Constraints
at http://www.support.xilinx.com.
Teaching Activities
Structured Discussion x
Paper exercise(s)
Lab exercise(s)
Demo
Review questions x
Test x
Instructor-led presentation
of the Timing Constraints II module that contains several examples.
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