Timing Constraints Ill v2.1i

Audience:
Audience has some FPGA experience or has attended the Getting Started class.  Students should have seen the Timing Constraints I module either in the Getting Started class or in Distance Learning.

Prerequisites:
Audience needs to understand basic FPGA architecture and have completed the Timing Constraints I  module.  Attendance in the Getting Started class meets these requirements.  

What is the level of the material?
Level II - Intermediate 

Training Duration:
1 Hour

Content Description:  This module focuses on placing path specific timing constraints on an FPGA design using the Constraints Editor.  Applications that contain multi-cycle paths or that could benefit from the use of False Paths are covered.  Information regarding constraint hierarchy is also provided.

Objectives
After completing this training, student will be able to:

• Apply path specific timing constraints to specific design applications and make path specific timing constraints with the Constraints Editor.
   

Topics or Training Outline

Introduction
Constraining Multi-Cycle Paths
False Paths
Constraint Priority
Summary

References
FPGA Editor Users Guide

Teaching Activities
Structured Discussion  
Paper exercise(s) x
Lab exercise(s) 
Demo 
Review questions x
Test   x