Introduction to FPGA Design v2.1i 

Software & Version:
N/A 

Audience:
Audience is new to Xilinx design. No prior knowledge of FPGAs is required.

Prerequisites:
None

What is the level of the material?
Level I - Beginning

Training Duration:
1 hour

Content Description:
The FPGA Design module provides a basic knowledge of Xilinx FPGA architecture, and then focuses on how and when to use general design techniques and specific Xilinx features to improve design reliability and performance. 

Objectives:
After completing this training, student will be able to:

• Describe the benefits of hierarchical design
• Improve the reliability and performance of a Xilinx FPGA design by applying synchronous design techniques 
   

Topics or Training Outline:

Proper use of hierarchy
Basic FPGA Architecture
Synchronous Design Techniques
Avoiding glitches on clock and reset signals
Clock dividers
Using Global Set/Reset 
State machine encoding schemes
Accessing Carry Logic
Building efficient counters 

References:
Main reference is XAPP Application Notes, covering many topics such as fast counters and FIFOs. Also Development System Reference Guide, Chapter 3, "FPGA Design Techniques" section.