Software & Version:
This module is generally software and hardware independent.

Audience:
Audience has some knowledge of FPGA architecture

Prerequisites:
Introduction to FPGA Design and an FPGA architecture module

What is the level of the material?
Level II - Intermediate

Training Duration:
1 hour

Content Description:
FPGA Design 2 continues with more design techniques to obtain maximum performance with Xilinx FPGAs. 

Objectives:
After completing this training, student will be able to:

• Increase overall design performance by duplicating logic, pipelining logic and using IOB registers.
• Build circuits that reliably synchronize inputs and resynchronize signals when changing clock domains.  

Topics or Training Outline:

Logic duplication
Pipelining
IOB registers
Synchronizing inputs
Resynchronizing signals 

References:
App note on metastable recovery