Software & Version:
Independent

Audience:
Beginning level HDL designers. FPGA design experience is not needed, familiarity with Virtex FPGA architecture is recommended. Familiarity with timing constraints is recommended. 

Prerequisites:
Prior simple, slow design in and FPGA OR basic Virtex architecture training course. Familiarity with HDL; student needs to be able to read VHDL or Verilog code. Attendance at the FPGA Tools class or similar class is recommended. 

What is the level of the material?
Level I - Beginning

Training Duration:
1 hour

Content Description:
This module focuses on coding styles that are recommended for use with Virtex designs. Topics include inferred registers, counters and state machines. 

Objectives:
After completing this training, student will be able to:

Use Foundation Express or FPGA Express to:

• Infer simple registered logic in design
• Effectively create state machines and counters

Topics or Training Outline:

Virtex register resources
Tips for registered functions including state machines and counters

References:
HDL Coding Style Guide
support.xilinx.com
Other modules
Tutorials