Multilinx, Parallel Cable IIIand XChecker Cables |
MultiLINX
Parallel Cable III (HW-JTAG) XChecker Cable (HW-XCHCBL) Cable Software To order stand alone cables contact the local distributor or international rep in your area. |
to view the
PDF files below.
MultilinxThe new MultiLINX TM cable takes advantage of the USB port found on newer PCs. MultiLINX delivers the ultimate in download performance: Up to 12 Mbits/second throughput. MultiLINX features an adjustable voltage interface that enables it to talk to systems and I/Os operating at 5, 3.3, or 2.5 volts.Software support for the MultiLINX cable is provided in version 2.1i
of the Alliance Series and Foundation Series software products.
Parallel Cable III (HW-JTAG-PC)The Parallel Download cable is a PC-only based cable that attaches to the parallel port of a designer's computer. The cable supports the following families:
Designs for FPGAs without the JTAG symbol inserted into their designs
can still use the "FPGA" row of wires for configuration of the FPGA.
XChecker Cable (HW-XCHCBL)The XChecker Download and Readback Cable is supported on PC and workstation platforms. The XChecker attaches to the host computer's RS232 serial port. The cable supports downloading and JTAG on the following families:
Internal logic nodes and signals can also be probed by taking a "snapshot" of the FPGA and uploading the data via XChecker. XChecker can control a user's system clock, allowing a design to be single-stepped and displayed for each clock cycle. HW-XCHCBL
Cable Drawing
Cable SoftwareThe Parallel and XChecker cables are supported by both the Xilinx Foundation and Alliance series development systems software packages. Although a complete installation is not necessary to use the features of the cables, the JTAG programmer software must be installed to use the Parallel cable with the on-chip JTAG port. The Hardware Debugger software must be installed in order to use the XChecker cable. The Hardware Debugger software must also be installed to use the Parallel cable for FPGAs using the FPGA download row of wires. |