backannotation
-
The process of creating timing simulation netlists. ngdanno
takes a mapped, placed, or routed NCD file and creates
an NGD type file. ngdanno uses the
NGM file to re-insert all of optimized logic and netnames
into the NGD file so that the original functional testbench
can be used for simulation. ngd2edif,
ndg2xnf, ngd2vhdl, or ngd2ver
can then convert the NGD type file to an
EDIF or XNF netlist that can be accepted by a simulator.
Backannotation is executed by the Flow Engine
GUI during the timing process. By default, backannotation
is turned off in the Flow Engine. To enable backannotation
in the Flow Engine, from the menu select
Setup->Options, and in the options dialog select Produce Timing
Simulation Data. In the options dialog also click on the Edit
Template button for Implementation and in the
template dialog, select the Interface tab. On the Interface
tab select the simulation netlist format: EDIF,
XNF, VHDL, or
Verilog, and select Correlate Simulation Data so all of the
optimized netnames and logic are inserted into the simulation netlist.
BEL (Basic ELement)
-
An object in an NCD file that refers to either a
LUT, flip flop, latch, or carry
logic element.
BELs accumulate to form COMPs.
If a COMP is edited in EPIC,
all of the internal BEL's are transformed into a
SuperBEL.
BIT
-
A binary configuration file that represents
a placed and routed FPGA design. A
BIT file can be downloaded directly to an FPGA using the Hardware Debugger and XChecker cable. A BIT
file can also be used as an input to the Prom
File Formatter or promgen, which create
configuration PROMs.
bitgen
-
A command line executable that translates a placed and routed NCD
file to a BIT file.
carry logic
-
Logic inside of a CLB that quickly performs arithmetic
carry functions.
CLB (Configurable Logic Block)
-
A physically co-located grouping of LUT's, flip flops,
and carry logic.
clock skew
-
The maximum delay between arrival times of a clock edge at clock pins of
multiple flip flops.
configuration
-
The process of programming an FPGA. Configuration occurs during
power up and can optionally occur if a reprogram has been initiated.
COMP
-
An object in an NCD file that refers to either a
CLB or IOB.
cost based cleanup passes
-
A feature in the place and route tools that tries to minimize routing
delays on a completely routed design by choosing routing that has smaller
cost values.
cost table
-
Each value (1 - 100) in the table initializes the placement algorithms
to a different starting state. Because the algorithms start in a different
state, the final results will be in a different state. By running multiple
place and routes with different cost table entries, some of the runs
will give improved results. On the command line, select a cost table entry
by using the -t <number> option with par. Through the
Design Manager, select a
version and from the menu select
Design->FPGA Multi-Pass Place
and Route.
critical path
-
The slowest path through asynchronous logic between a set of source flip
flops and a set of load flip flops that share a common clock signal. The
delay through critical path (including clock to out and setup time)
defines the minimum period the for the clock. A timing report on timing
constraints will list all of the paths for a failed timing constraint
from worst to best delay. The critical path for a timing constraint path
is the first path listed.
daisy chain
-
A set of FPGA's wired together with for configuration. The configuration
memory of the first device is loaded with its configuration data, then the
next device is filled, and so on. When all of the FPGA's have filled
their configuration memory, all of the
FPGA's transition to the operation state in unison.
delay based cleanup passes
-
A feature in the place and route tools that tries to minimize routing
delays on a completely routed design by choosing routing that has smaller
delays.
Design Manager (dsgnmgr)
-
The main graphical implementation tool. The Design Manager, mantains
versions of netlist files and revisions of implementation. files. It
provides access to the Flow Engine, Timing Analyzer, Prom
File Formatter, Hardware Debugger,
and EPIC editor tools.
-
Electronic Design Interchange Format. An industry-standard netlist format.
edif2ngd
-
Executable that translates an EDIF netlist file to
an NGD netlist file.
EPIC (Editor for Programmable Integrated Circuits)
-
A graphical editor that provides a view of the physical implementation
of your Xilinx design. EPIC features include:
- Ability to view CLB mapping,
placement, and
routing.
- Modification of CLB mapping, placement, and routing.
- Timing Anaylysis
- Ability to create custom physical macros to be incorporated
in your design.
feedthrough
-
A CLB that is used to route to a signal. Feedthroughs allow a dense
design to be more routable, although paths with feedthroughs have more
delay. Feedthroughs can be identified using EPIC: CLB's show routing
through them.
flexlm
-
Software that can distribute licenses to machines across a network.
-
Flow Engine
-
A graphical tool for executing the implementation flow on a design netlist.
The Flow Engine performs the following processes: Netlist translation
NGD, Map, Place
and Route, and BIT file generation.
functional simulation
-
Simulation of a logical netlist using unit delays.
GUI (Graphical User Interface)
-
A graphical program used for accessing the implementation tools.
guide
-
When implementing a design, using the the map, place, and route results
of unchanged logic from a previous implementation. Guiding an implementation
can significantly reduce the implementation time, since the tools only
need to spend time processing the parts of the design that have changed.
There are two guide modes available with the FPGA implemenatation software: Exact
and Leveraged. With exact mode, the unchanged logic can not be modified in the
current implemenation. With leveraged mode, the unchanged logic is used as a
starting point and can be modified by the current implementation.
Hardware Debugger
-
A graphical tool for configuring an FPGA or
a daisy chain of FPGA's directly from a computer.
The Hardware Debugger can take a BIT file or
PROM file as an input.
IOB (Input Output Block)
-
A physically co-located group of buffers, latches, flip flops, and
input/output pads used for sending signals off of the FPGA
and receiving signals onto the FPGA.
IEEE (pronounced "I triple-E")
-
Institute of Electrical and Electronics Engineers.
LogiBLOX
-
A graphical tool for creating digital logic macros that are optimized for
Xilinx FPGA's.
LUT (Look Up Table)
-
A block of logic in a CLB that uses SRAM technology to implement asychronous
digital logic.
map
-
An executable that takes an NGD netlist and groups the
logical elements into CLBs and IOB's.
Map outputs the data into an NCD file.
multi-pass place and route
-
A place and route option that runs multiple
place and route iterations on a design. Each iteration is executed
with a different cost table values, so the
results of each iteration are different. Each iteration is scored, and
the best iterations are saved.
NGA (Native Generic Annotation)
-
An FPGA logic netlist file that is equivalent to an NGD
file, but is produced by ngdanno during
the backannotation process.
NCD (Native Circuit Database)
-
An FPGA file that holds mapping, placement, and routing data about a design
implemenation. A valid NCD can hold mapping information, or mapping/routing
information, or mapping/placement/routing information.
NGD (Native Generic Database)
-
An FPGA file that holds logical netlist information about a design.
NGM (Native Generic Mapping)
-
An FPGA file that holds information about optimized logic and netlists.
An NGM file is used by the backannotation
process to reconstruct the original netlist from the optimized
NCD netlist for timing simulation. This enables you
to use the functional simulation
testbench in timing
simulation.
ngdanno
Command line executable that performs backannotation.
ngd2edif
-
Command line executable that translates an NGD or
NGA netlist to and EDIF netlist
for simulation purposes.
ngd2ver
-
Command line executable that translates an NGD or
NGA netlist to a verilog netlist
for simulation purposes. If there is timing information in the NGD file
then an SDF file will also be produced.
ngd2vhdl
-
Command line executable that translates an NGD or
NGA netlist to a vhdl netlist
for simulation purposes.
ngd2xnf
-
Command line executable that translates an NGD or
NGA netlist to a xnf netlist for
simulation purposes.
offset
-
A timing constraint keyword for specifying the off chip delay of a signal
with respect to a clock.
par (Place And Route)
-
A command line executable for placing and
routing a mapped NCD file.
PCF (Physical Constraints File)
-
A file generated by map that contains timing and location
constraints of the logic in the physical domain. Map reads the constraints
in the NGD file, which originally came from the netlist
or the UCF file, and translates them into physical
constraints.
place and route
-
The process of taking logic that has already been mapped to
CLB's and IOB's, and determining which
locations they occupy and what routing is used to connnect them. This
process is performed by par.
post map simulation
-
Simulating a design after the mapping. The timing values for the logic are
based on real block delays and estimates for the routing delays. Useful
in performing a preliminary timing analysis before executing place and route.
post ngdbuild simulation
-
Functionally simulating a design after ngdbuild using unit delay timing.
Useful for verifying synthesis results and verifying designs with
components from varying front end tools.
post route simulation
-
Complete timing simulation after route that uses real block and real route
delays. Useful for verifying that FPGA implementation meets all functional
and timing requirements.
project
-
A data structure used by the Design Manager
to hold information related to the implementation of your design:
versions, revisions,
implementation state, options used, etc.
PROM (Programmable Read Only Memory)
-
A chip used to store configuration data for
an FPGA or a daisy chain of FPGA's.
PROM File Formatter
-
A graphical tool used for generating a PROM file from
a configuration bit file.
promgen
A command line executable used to generate a PROM file
from a configuration bit
file.
readback
-
The process of reading data from an FPGA while it is executing a design.
The data describes the FPGA configuration and the state of the flip flops
in the design. Useful for performing verifying the correctness of the FPGA
configuration and in performing an in circuit
debug using the Hardware Debugger.
re-entrant route
-
The process of taking a partially routed design and continuing to route
it using new options.
revision
-
A data structure in the Design Manager that refers to a complete or partial
implemenation of a design. Multiple revisions can exist under a
version, where each revision uses the same netlist
but different implementation options.
RTL simulation
- Pre-synthesis simulation of behavioral code.
SDF (Standard Delay Format)
-
A file that holds timing information for verilog
simulation.
SuperBEL (Super Basic ELement)
-
A data structure in an NCD file that is created from
a set of BEL's within a COMP that
are editted using EPIC.
templates
-
A data structure used by the Design Manager and Flow Engine to hold option
settings. There are two types of templates: Implementation and
Configuration.
timing constraints
-
User directives to the map, and
place and route tools indicating the desired speed for sections of the design.
Specified in the input netlist or the UCF file.
timing simulation
-
Simulation after route that uses real block and real route delays.
Useful for verifying that FPGA implementation meets all functional and
timing requirements.
Timing Analyzer
-
A graphical tool for examing the speed of your FPGA implementation.
You can examine delays on specific nets, performance of timespecs, and
clock speeds.
trce
-
A command line tool for examing the speed of your FPGA implementation.
You can examine delays on specific nets, performance of timespecs, and
clock speeds.
Turns Engine
-
A feature that allow you to execute multi-pass
place and route on simultaneously on UNIX machines.
UCF (User Constraints File)
-
A user created ASCII file for storing timing
constraints and location contraints for a design implementation.
Verilog
-
An industry-standard hardware description language developed by
Cadence
Design Systems. Recognizable as a file with a .v extension.
version
-
A data structure in the Design Manager that refers to an input netlist.
Multiple versions can exist under a project, where each version refers to
the design netlist in various states of completion.
VHDL
-
VHSIC Hardware Description Language. An industry-standard
(IEEE 1076.1) hardware description language. Recognizable
as a file with a .vhd or .vhdl extension.
VHSIC
Very High Speed Integrated Circuit.
VITAL
-
VHDL Initiative Toward ASIC Libraries. A VHDL-library
standard (IEEE 1076.4) that defines standard constructs
for simulation modeling, accelerating and improving the performance of
VHDL simulators.
X-BLOX
-
Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool
where generic bus-width-independent symbols such as counters, adders, and
data registers are used to implement architecture-optimized functions.
XNF
-
Xilinx Netlist Format.
xnf2ngd
-
Executable that translates an XNF netlist file to an
NGD netlist file.
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