FPGA Configuration: Glossary
Bit-Stream
- The bit-stream is a binary representation of an implemented FPGA design. The bit-stream is generated by the Xilinx bit generation tools (bitgen and makebits) and is denoted with the extension <.bit>. For information on creating .bit files refer to the Hardware Debugger Reference/User Guide.
CCLK
- During configuration, the Configuration Clock (CCLK) is an output in Master
modes or in Asynchronous Peripheral mode, but is an input in Slave mode,
Synchronous Peripheral mode, Express mode, and SelectMAP/Slave Serial mode. After configuration, CCLK has a weak pull-up and can be selected as the Readback Clock. For further information on the CCLK Pin refer to The Programmable Logic Data Book.
Configuration
- The process of programming Xilinx SRAM based FPGAs with a Bit-Stream is referred to as configuration. For a more detailed description of the Configuration Modes refer to The Programmable Logic Data Book.
CS Pin
- The CS Pin is the Chip Enable Pin for Virtex/Spartan-II. It is only used in the
SelectMAP mode. When CS is asserted (low) the device will
examine the data on the Data bus. When CS is de-asserted, all CCLK transitions
are ignored. For a more detailed description of the CS Pin and its use, refer
to The Programmable Logic Data Book and Application Note
138.
DataFrame
- A DataFrame is a block of configuration data. A configuration bit-stream contains many such frames each with a start bit and stop bits. For a detailed description of DataFrame sizes and format refer to The Programmable Logic Data Book.
DIN
- During serial configuration, the DIN Pin is the serial configuration data input receiving data on the rising edge of CCLK. During parallel and peripheral configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O Pin. For further information on the DIN Pin refer to The Programmable Logic Data Book.
DONE Pin
- The DONE Pin on a Xilinx FPGA is a bidrectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a low level on DONE can be configured to delay the global logic initialization and the enabling of outputs. For further information on the DONE Pin refer to The Programmable Logic Data Book.
DOUT Pin
- During configuration in any mode except Express and SelectMAP, the DOUT Pin is the serial configuration data output that can drive the DIN Pin of daisy-chained slaves FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DIN Pin. For further information on the DOUT Pin refer to The Programmable Logic Data Book.
DOUT/BUSY Pin
- For Virtex/Spartan-II devices, the DOUT/BUSY pin has a dual purpose,
depending on the mode the device is in. If the device is in Serial mode, it
acts the same as the DOUT Pin. When the device is in
SelectMAP/Slave Parallel mode, the pin acts as a handshaking signal. If BUSY
is asserted (high) on a rising edge of CCLK, the data was not
seen on the data bus, and should be held until the data is accepted. For a more
detailed description of the DOUT/BUSY Pin and its use, refer to The Programmable
Logic Data Book and Application Note
138.
DataFrame
- A DataFrame is a block of configuration data. A configuration bit-stream contains many such frames each with a start bit and stop bits. For a detailed description of DataFrame sizes and format refer to The Programmable Logic Data Book.
FPGA
- Xilinx Field Programmable Gate Arrays (FPGA) are SRAM based Programmable
Logic Devices (PLD). FPGAs contain an array of programmable logic elements.
The configuration data for the array is stored in an internal SRAM bank called
the configuration memory. The configuration memory can be cleared
on-the-fly with the PROG Pin or every time power is
cycled. For more information on Xilinx SRAM based products refer to The Programmable Logic Data Book.
HDC Pin
- High During Configuration (HDC) is driven High until the I/O go active in the Startup sequence. It is available as a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O Pin. For more information on FPGA I/O refer to The Programmable Logic Data Book.
Header
- The Header is the first section of the Bit-Stream. This 40 bit section contains the 4 bit Preamble, a 24 bit LengthCount, and 12 dummy bits. For more information on the bit-stream format refer to The Programmable Logic Data Book.
INIT Pin
- The INIT Pin is a quadruple function signal. Before and during configuration, INIT is a bidirectional signal. A 1k - 10k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active in the Startup sequence, INIT is a user-programmable I/O. For more information on configuration specifications and timing refer to The Programmable Logic Data Book.
JTAG Cable
- See Parallel Cable III.
LDC Pin
- Low During Configuration (LDC) is driven Low until the I/O go active in the Startup sequence. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O
Pin. For more information on FPGA I/O refer to The Programmable Logic Data Book.
LengthCount
- The LengthCount is a 24 bit binary number embedded in the Header of the bit-stream. During configuration, the LengthCount is captured and stored in the Lengthcount Register. Every configuration data bit (one per CCLK period) is counted by the LengthCount Counter. When the LengthCount Register and the LengthCount Counter are equal, LengthCount Match is achieved. LengthCount Match is a requirement for entering the Startup sequence. For more information on the LengthCount and bit-stream format refer to The Programmable Logic Data Book.
Multilinx Cable
- The Mutilinx Cable is the newest cable offered by Xilinx. It is capable of
many complex functions, and can be reloaded with new firmware as it becomes
available. It can be connected to the host computer in two ways: via the
Serial port, or the USB port. The Multilinx cable is supported by the Hardware
Debugger for Slave Serial and SelectMAP/Slave Parallel programming (as
appropriate) as well as Readback Verify. It is also supported by the JTAG
programmer for JTAG programming of CPLD's and FPGA's. For more information on
using the Multilinx Cable refer to the Hardware Users Guide, the
Hardware Debugger Reference/Users Guide, and the JTAG
Programmer Guide.
Parallel Cable III
- The Xilinx Parallel Cable III (model DLC5) is a serial download cable. The Parallel cable uses a serial 25-pin interface to the parallel port of a host computer and two 6-pin headers for flying-wire connectors to a target board. The Parallel cable is supported by the Hardware Debugger software for performing Slave Serial configuration of FPGAs only. The Parallel cable is also supported by the JTAG Programmer software for performing Slave Serial and Boundary Scan configuration of FPGAs, and Boundary Scan programming of CPLDs. For more information on using the Parallel cable refer to the Hardware Users Guide, the Hardware Debugger Reference/Users Guide, and the JTAG Programmer Guide.
Preamble
- The Preamble is a 4 bit binary sentinel ("0010"b) used to indicate the beginning of the LengthCount in the Header portion of the Bit-Stream. At the beginning of configuration, the FPGA will ignore all data prior to the preamble, but will count the number of data bits preceding it. The LengthCount Counter will increment for every configuration data bit proceeding the preamble. For more information on configuration data refer to The Programmable Logic Data Book.
PROG Pin
- The PROG, or PROGRAM, Pin is an active-Low input that forces the FPGA to clear it's configuration memory, and is used to initiate a configuration cycle. While PROG is held Low, the FPGA will drive INIT Low and continue to clear the configuration memory. When PROG is transitioned High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it goes into a WAIT state and releases INIT. For more information on configuration specifications and timing refer to The Programmable Logic Data Book.
READBACK
- Initiating a Readback causes the configuration memory to become accessible
to be serially clocked out and read from the device, or byte-wide in the case
of SelectMAP/Slave Parallel. The configuration memory contains the configuration data, allowing for a Read-Verification of the configuration data, and can also contain the logic states of the CLB outputs allowing for a Read-Capture of the current design's internal logic states. The Read-Verification and Read-Capture are used by the Hardware Debugger for Hardware Verification. For information on the Readback specification and timing refer to The Programmable Logic Data Book. For information on using the Readback component in a design refer to the Libraries Guide. For information on enabling the Readback function in the Implementation Software refer to the Development System Reference Guide. For information on using the Hardware Debugger refer to the Hardware Debugger Reference/User Guide. For information on connecting the XChecker Cable for Readback refer to the Hardware Users Guide.
STARTUP
- The Startup sequence completes a configuration cycle by releasing the DONE Pin, activating the I/O, and de-asserting the Global-Set-Reset (GSR) which globally initializes all internal flip-flops. The sequence of these three steps are user-programmable during bit-stream generation. In order for the FPGA configuration cycle to enter the Startup sequence two conditions must be met: Firstly, the configuration memory must be FULL, and secondly, LengthCount Match must be achieved --in that order. For more information on the Startup sequence and FPGA configuration refer to The Programmable Logic Data Book.
WRITE Pin
- The WRITE Pin is an input to a Virtex/Spartan-II during SelectMAP/Slave
Parallel mode. It tells the device, which direction the data is flowing on the
Data bus. When WRITE is asserted (low), data will be going into the device,
which is the case for configuration. When WRITE is de-asserted (high), data
will be coming out of the device, which is the case for READBACK. When WRITE is asserted or de-asserted, when the device
doesn't expect it, an ABORT occurs. For more information on the WRITE pin,
refer to The Programmable Logic Data Book and Application
Note 138.
XChecker Cable
- The Xilinx XChecker Cable (model DLC4) is a serial download cable. The XChecker uses a serial 9-pin interface to the com port of a host computer and two 8-pin headers for flying-wire connectors to a target board. The XChecker is supported by the Hardware Debugger software for performing Slave Serial configuration and Readback of FPGAs. The XChecker is also supported by the JTAG Programmer software for performing Slave Serial and Boundary Scan configuration of FPGAs, and Boundary Scan programming of CPLDs. For more information on using the XChecker cable refer to the Hardware Users Guide and the Hardware Debugger Reference/Users Guide.
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