Timing & Constraints: Glossary 

BEL
carry logic
CLB
clock skew
COMP
connection
critical path
element
FPGA Editor
feedthrough
FROM:TO constraint
FROM:THRU:TO constraint
GUI
IOB
LogiBLOX
LUT
map
NCD
NGD
offset
par
path
Period constraint
PCF
place and route 
predefined group 
scope 
Slow Exception
SuperBel
TIG
Timegroup
timing constraints
Timing Analyzer
trce
UCF

 

BEL (Basic ELement)

An object in an NCD file that refers to either a LUT, flip flop, latch, or carry logic element. 
BELs accumulate to form COMPs.  If a COMP is edited in FPGA Editor, all of the internal BEL's
are transformed into a SuperBEL.

carry logic

Logic inside of a CLB that quickly performs arithmetic carry functions.

CLB (Configurable Logic Block)

A physically co-located grouping of LUT's, flip flops, and carry logic.

clock skew

The maximum delay between arrival times of a clock edge at clock pins of multiple flip flops.

COMP

An object in an NCD file that refers to either a CLB or IOB.

connection

A driver/load pin combination which is connected by a signal. 

critical path

The slowest path through asynchronous logic between a set of source flip flops and a set of load flip flops that share a common clock signal. The delay through critical path (including clock to out and setup time) defines the minimum period the for the clock. A timing report on timing constraints will list all of the paths for a failed timing constraint from worst to best delay. The critical path for a timing constraint path is the first path listed.

element

COMPs, BELs, MACROs, nets, or pins.

FPGA Editor

A graphical editor that provides a view of the physical implementation of your Xilinx design. FPGA Editor features include: 
  • Ability to view CLB mapping, placement, and routing.
  • Modification of CLB mapping, placement, and routing.
  • Timing Analysis
  • Ability to create custom physical macros to be incorporated in your design.

feedthrough

A CLB that is used to route to a signal. Feedthroughs allow a dense design to be more routable, although paths with feedthroughs have more delay. Feedthroughs can be identified using FPGA Editor: CLB's show routing through them.

FROM:TO constraint

A constraint used to specify the timing from a set of start points to a set of end points. The start and end points may be defined by using a TNM, TIMEGRP, or TPSYNC statement (Example 1), or they may be directly referenced inside the FROM:TO by indicating the output net (Example 2).
Example 1: 
INST $1I6/flop_instance  TNM = myflop;       #attach a TNM to a flop instance 
TIMEGRP myram = RAMS($1I45/ramout);  #group RAMs with given output 
TIMESPEC TS01 = FROM myflop TO myram 30; 
Example 2:
TIMESPEC TS02 = FROM FFS($1I6/flop_Qoutput) TO RAMS($1I45/ramout) 30; 

FROM:THRU:TO constraint

A constraint used to specify the timing from a set of start points to a set of end points, via a specified net or set of nets. The start and end points may be defined by using a TNM, TIMEGRP, or TPSYNC statement (Example 1), or they may be directly referenced inside the FROM:TO by indicating the output net (Example 2). The intermediate nets may be defined with the TPTHRU keyword.
Example 1: 
INST $1I6/flop_instance   TNM = myflop;     #attach a TNM to a flop instance 
TIMEGRP myram = RAMS($1I45/ramout); #group RAMs with given output
NET $1N3* TPTHRU = thrupoint;               #group intermediate nets
TIMESPEC TS01 = FROM myflop THRU thrupoint TO myram 30; 
Example 2: NET $1N3* TPTHRU = thrupoint;               #group intermediate nets
TIMESPEC TS02 = FROM FFS($1I6/flopQ) THRU thrupoint TO RAMS(ramout) 30;

GUI (Graphical User Interface)

A graphical program used for accessing the implementation tools.
 

IOB (Input Output Block)

A physically co-located group of buffers, latches, flip flops, and input/output pads used for sending signals off of the FPGA and receiving signals onto the FPGA.

LogiBLOX

A graphical tool for creating digital logic macros that are optimized for Xilinx FPGA's.

LUT (Look Up Table)

A block of logic in a CLB that uses SRAM technology to implement asychronous digital logic.

map

An executable that takes an NGD netlist and groups the logical elements into CLBs and IOB's. Map outputs the data into an NCD file.

NCD (Native Circuit Database)

An FPGA file that holds mapping, placement, and routing data about a design implementation. A valid NCD can hold mapping information, or mapping/routing information, or mapping/placement/routing information.

NGD (Native Generic Database)

An FPGA file that holds logical netlist information about a design.

offset

A timing constraint keyword for specifying the off chip delay of a signal with respect to a clock.

path

A source point, a destination point, and any elements in between through which a signal
passes.

par (Place And Route)

A command line executable for placing and routing a mapped NCD file.

PCF (Physical Constraints File)

A file generated by map that contains timing and location constraints of the logic in the physical domain. Map reads the constraints in the NGD file, which originally came from the netlist or the UCF file, and translates them into physical constraints.
 

Period constraint

A constraint placed on a clock net that defines the worst-case period for all paths starting
and ending at the  registers, synchronous rams, pads, and latches clocked or enabled by the 
specified clock net. The Period  constraint does not control paths that end at a pad; a 
FROM:TO spec or a OFFSET constraint is necessary for those paths. 
Example: NET myclocknet PERIOD = 20 ; 

place and route

The process of taking logic that has already been mapped to CLB's and IOB's, and determining which locations they occupy and what routing is used to connect them. This process is performed by par.

predefined group

A Timegroup that is defined by default. Predefined groups include FFS (for all flip-flops),
RAMS (for all ram), LATCHES (for all latches), and PADS (for all input and output pads).
Example: 
Timespec TS01 = FROM: FFS: TO : PADS: 30;    #Constrains all flip-flops to all pads

scope

The order of precedence used to determine which constraint will keep a set of paths when
two or more constraints cover them. The order of scope from highest to lowest priority is: 
    1. Path TIG (for path blocking) 
    2. FROM:THRU:TO type specs 
      • Neither source or destination are predefined groups 
      • Either source or destination is a predefined group 
      • Both source and destination are predefined groups 
    3. FROM:TO type specs 
      • Neither source or destination are predefined groups 
      • Either source or destination is a predefined group 
      • Both source and destination are predefined groups 
    4. PERIOD 

Slow Exception

A case in timing analysis where a subset of a path or Period constraint is allowed to run at a 
slower speed. One way to accomplish this is to place a Period constraint on the clock net to 
constrain the majority of the design, and then constrain a subset of the loads on that net to a 
slower speed.
Example: 
NET clocknet PERIOD = 25 ;
TIMESPEC TS_slow = FROM : FFS($1I3/slowflop) : TO:RAMS($1I3/slowram): 30;

SuperBEL (Super Basic ELement)

A data structure in an NCD file that is created from a set of BEL's within a COMP that are edited using FPGA Editor.

TIG

A timing constraint used to indicate a path or element should be ignored for the purposes of
timing analysis. A TIG on a path will remove the entire path from path analysis. A TIG on an
element will stop the tracing of a path at that point. TIG can be applied on a specific
timespec or globally to all timespecs.
Example 1:  NET slownet TIG ;
Example 2:  NET slownet TIG = TS04;   #ignore paths thru net only for TS04 constraint


Timegroup

A collection of design elements or other Timegroups for use in defining constraints for a 
design. 


timing constraints

User directives to the map, and place and route tools indicating the desired speed for 
sections of the design. Specified in the input netlist or the UCF file.


Timing Analyzer

A graphical tool for examining the speed of your FPGA implementation. You can examine
delays on specific nets, performance of timespecs, and clock speeds.

trce (TRACE)

A command line tool for examing the speed of your FPGA implementation. You can examine delays on specific nets, performance of timespecs, and clock speeds.

UCF (User Constraints File)

A user created ASCII file for storing timing constraints and location constraints for a design implementation.