Record #6905

Product Family: Software

Product Line: Timing

Problem Title:

How to apply a Period constraint on Virtex CLKDLL for 2.1i

Problem Description:

Keywords:  Virtex, Period, constraint, CLKDLL

Urgency: Standard

General Description:
How do I apply a PERIOD timing specifications in 2.1i when using a Virtex CLKDLL?

The rules regarding property tracing through the DLL have changed in 2.1i. When a TNM_NET property is traced into the CLKIN pin of a Virtex CLKDLL component, the TNM group and its usage will be examined. The TNM will be pushed through the CLKDLL only if the following conditions are met:
 
              
  • The TNM group name is used in exactly one PERIOD specification.
  • The TNM group name is not used in any FROM-TO or OFFSET specifications.
  • The TNM group name is not referenced in any user group definition.
    		•

    If any of the above conditions are not met, the TNM will not be pushed through the CLKDLL, and the following error message will be issued:

    ERROR:NgdHelpers:702 - The TNM "PAD_CLK" drives the CLKIN pin of CLKDLL "$I1".

    This TNM cannot be traced through the CLKDLL because it is not used in exactly one PERIOD specification. This TNM is used in the following user groups and/or specifications:
       TS_PAD_CLK=PERIOD PAD_CLK 20000.000000 pS HIGH 50.000000%
      TS_01=FROM PAD_CLK TO PADS 20000.000000 pS

    If the above conditions are met each clock output pin on the CLKDLL will be examined to see if it is connected to a net with at least one other connection (i.e. it is not a dangling net). If the output pin has a net, a new TNM group will be created on that net, and a new PERIOD specification will be created for that group. The new specification will be copied from the original PERIOD specification, and then modified as follows:
     
    Output Pin
    Modifications to PERIOD Specification
    CLK0
    		 If the DUTY_CYCLE_CORRECTION=TRUE property is found on or above the CLKDLL, the duty cycle will be adjusted to 50%. If DUTY_CYCLE_CORRECTION=FALSE is found, the duty cycle will be unchanged from the original PERIOD specification. If no DUTY_CYCLE_CORRECTION property is found, the default value of TRUE will be assumed.
    CLK90
    CLK180
    CLK270
    CLK2X
    		 The PERIOD value will be doubled (if originally expressed as a frequency) or divided in half (if originally expressed as a delay). The duty cycle will also be adjusted to 50%.
    CLKDV
    		 The PERIOD value will be divided (if a frequency) or multiplied (if a delay) by the value in the CLKDV_DIVIDE property. If no such property is found on or above the CLKDLL, the default value of 2.0 will be used. The duty cycle will also be adjusted to 50%.

    If the original TNM_NET property is pushed only into the CLKDLL CLKIN pin (i.e. it does not trace to any appropriate elements without going through the CLKDLL), the original TNM group and the original PERIOD specification will be eliminated from the design.

    If a newly-created TNM group is pushed forward from a CLKDLL output and encounters the CLKIN input of a second CLKDLL (such as in the 4X configuration), the above process will be repeated to further adjust the PERIOD specification(s) per the behavior of the second CLKDLL. If the group created for the first CLKDLL traces only into the second CLKDLL, that group and its PERIOD specification become unnecessary and will be eliminated.

    For further information regarding property tracing through the CLKDLL refer to the Developmental System Reference Guide Chapter 6.