Cadence Interface - Documentation

Concept-HDL Design Flow

• Concept-HDL - New Standard in Schematic Capture
• Integrate FPGA & System Design Using Concept HDL

Concept-SCALD Design Flow

• Cadence M1.x Design Conversion Guide, v1_5, 6/98 (62 kB)
  Design conversion application note hilighting the concepts necessary for re-targeting a Concept schematic design using the XACT release to the new M1 flow.

Verilog

• XAPP108: Chip-Level HDL Simulation Using the Xilinx Alliance Series, 5/98 (200 kB)
  Application Note describing the basic flow and issues to be aware of when performing a chip-level simulation of a Xilinx device using a Verilog or VHDL simulator and the Xilinx Alliance 1.4 release.
• Synthesis and Simulation Design Guide, 4/98 (1.3 MB)
  Manual providing a general overview for designing into FPGAs using VHDL and Verilog.