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API
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Applications Programming Interface. A set of software libraries, developed
by a particular software vendor, that allows 3rd party software programs
to interface with programs from that vendor.
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body
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A Concept symbol. The format of a body file name
is body.<version>.<sheet_number>. Example: body.1.1 is version 1,
sheet 1 of a Concept symbol.
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cds_action = "ignore"
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Verilog parameter definition that must be added to the Verilog .v file
generated for a LogiBLOX, or other non-schematic block to indicate to
Concept2xil
that there are no other underlying levels of hierarchy associated with
a given block.
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cds.lib
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A library mapping file pointing to the VAN-compiled
Verilog libraries used by Concept2xil and
Concept.
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chips_prt
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Concept parts file. Contains physical information
about a board level part
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CIW
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Command Interpreter Window. Startup window for Design Framework and Composer.
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Concept
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Cadence schematic editor used mainly by board level designers. Originally
from a company called Valid which was purchased by Cadence.
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Concept2xil
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Cadence's EDIF netlist writer which interfaces to Xilinx's Alliance flow.
Generates an EDIF netlist from Verilog netlist(s) generated by
HDL
Direct in Concept.
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Concept2XNF
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Cadence's XNF netlist writer which interfaces to Xilinx's XACT 5.x flow.
Generates an XNF netlist from a Concept schematic
using CAEVIEWS.
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Genview
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A program that ships with the Cadence Concept schematic
editor. Genview generates a symbol body from a
Concept
schematic, a Verilog netlist, or a user-specified
portlist.
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global.cmd
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Concept setup file containing aliases to the Xilinx
and Cadence libraries available for your design.
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HDL Direct
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Cadence Concept methodology for generating simulatable
Verilog and VHDL code directly from schematics. Required methodology for
Xilinx Alliance interface.
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hdlconfig
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Concept HDLConfig traverses a design's hierarchy
and generates a design configuration that points to the cellviews for all
the blocks in your design. In the 9604 release, HDLConfig reads the
global.cmd
and hdldirect.dat files.
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IEEE 1164
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The IEEE standard for Verilog HDL supported by
Open Verilog
International To order a copy of this standard, see:
http://standards.ieee.org/catalog/contents.html
 under
Information Technology, subcategory, "Design Automation".
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iterated instance
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Concept methodology for replicating bodies which
involves adding an index range to the value of the PATH property for a
given instance. Use this methodology to replicate bodies in M1.x instead
of the SIZE property.
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logic drawing
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A Concept schematic. The format of a logic drawing
file name is logic.<version>.<sheet_number>. Example: logic.1.2 is
version 1, sheet 2 of a Concept schematic.
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master.local
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A SCALD library mapping file which lists the explicit paths to user libraries.
Aliases to each user library are defined in this file. Libraries defined
in master.local are available to your design if you include a "master_library"
directive in your global.cmd pointing to master.local.
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OVI
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Open Verilog International is an organization that exists to promote and
support the use of Verilog HDL worldwide. OVI supports the IEEE
1364 standard for Verilog HDL.
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Rapidsim
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Cadence's discontinued schematic simulator. Also originally developed by
Valid . Tightly integrated with Logic Workbench and the
Concept
schematic editor.
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SIR2EDF
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SIR2EDF is Cadence's generic SIR (Structural Intermediate Representation)
to EDIF conversion tool. Concept2xil invokes
SIR2EDF after running HDLConfig and VAN.
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SIZE
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Concept property used for replicating symbols. Not
supported in Xilinx Alliance Concept and Verilog
libraries -- you must use Iterated Instance
methodology instead.
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SKILL
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Cadence's scripting language, used by Design Framework programs such as
Composer, and Verilog-XL.
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startup.concept
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Concept startup file. Contains commands that set
various modes of Concept operation. Commonly used
to activate HDL Direct and HDL Direct related
checks at startup.
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VAN
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Cadence's Verilog Analyzer. Concept2xil calls
VAN as well as HDLConfig and SIR2EDF when it processes a Concept
schematic.
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Verilog-XL
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Cadence's Verilog HDL simulator.
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VITAL
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VHDL Initiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4)
that defines standard constructs for simulation modeling, accelerating
and improving the performance of VHDL simulators.
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.wrk file
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SCALD library mapping file for you design. Lists the design blocks in the
project directory. Updated by Concept when a new
block is created.
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