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Eliminate False Clock Triggering

Sparty's Favorite Recipes 010 Kiss Your ASIC Good-bye!

Ingredients:

  • Any Spartan-II Device
  • 2.1i Development System
  • Nutritional Analysis:

  • Logic Cells: 1 per flip-flop
  • Instructions

    As FPGA flip-flops become faster, they can respond to very short clock pulses, even accidental glitches. Fast clock transitions often lead to reflections on long pc-board clock lines, and such reflections can result in overshoot, undershoot and ringing, which might lead to multiple crossings of the input thresholds. There are well-known methods to keep reflections under control, but they require an understanding of high-frequency and transmission-line effects, and they may be difficult and expensive to implement, and impossible to retrofit. In the past, FPGAs were slow enough to be forgiving, so that many high-frequency problems could be ignored. Now, double pulses separated by one or a few nanoseconds can cause double triggering and result in system failure.

    Here are two effective remedies against such problems. The description assumes rising-edge triggering, but can easily be modified for falling-edge triggering.

    1. Double clocking on the rising edge means that a reflection caused the internal clock signal to go L-H-L-H instead of a simple L-H transition. The second L-H transition might clock the flip-flops again, if they are fast enough to respond to two clock edges that are only one or a few nanoseconds apart. The simple solution is to add delay in front of the D-inputs, so that they cannot change in the short time between the two rising clock edges. Use redundant LUTs or additional routing to slow down the few flip-flops that are sensitive, such as the LSBs of a counter.

    2. Clocking on the wrong (falling) edge is always caused by a H-L-H-L sequence of clock transitions within a few nanoseconds. (Remember: No flip-flop will ever trigger on the falling edge, if configured to trigger on the rising edge. But no flip-flop will ever ignore the edge it is supposed to trigger on.) This false triggering “on the wrong edge” in the middle of the clock period cannot be cured by slowing down the flip-flop inputs. Instead, a slightly delayed and inverted version of the incoming clock signal must be used as Clock Enable to the flip-flops that are exposed to this type of wrong clocking. CE will be active (High) before and during the legitimate rising clock edge, but will be inactive (Low) before and during the unintended clock glitch, caused by a reflection of the falling clock edge.

    Note that the two problems on the rising and the falling edge, although caused by the same phenomenon, require two very different solutions. Luckily, both solutions are simple, and are not mutually exclusive. Clock reflections should be avoided by proper PC-board design, but the world is not perfect, and it is nice to have a fix available, especially one that is so easily applied in an FPGA, and so powerful and without any harmful side effects. And it can easily be added to old design that got in trouble when fitted with newer, faster parts.

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