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Self-Initiated Global Reset

Sparty's Favorite Recipes 012 Kiss Your ASIC Good-bye!

Ingredients:

  • Any Spartan-II Device
  • 2.1i Development System
  • Nutritional Analysis:

  • CLBs: 1
  • Instructions

    It is possible for an FPGA to initiate its own reset, but it takes a circuit trick to do it. When synchronous internal logic initiates a Global Reset (GSR), this signal affects every flip-flop on the chip, and thus terminates itself. For reliable operation, the GSR signal must be stretched in a latch (Q1), and this latch must later be reset with the help of the free-running clock and a second latch (Q2). This whole circuit - 4-input detector, flip-flop, and both latches - fits into a single CLB. Q1 drives the GSR with a duration of one clock period. This time can be extended another half clock period by ORing Q1 and Q2.

    Operation: The rising clock edge clocks the reset condition into Q0, which in turn sets latch Q1. Q1 drives GSR which resets (or sets) all flip-flops, including Q0. While Q1 is set, the subsequent clock Low signal sets Q2. While Q2 is set, the subsequent clock High signal resets Q1, and the following clock Low signal resets Q2. The operation is hazard-free and reliable, but may cause grief in certain simulators that cannot cope with combinatorial feedback loops.

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