Overview
Xilinx offers a number of reference designs in the form of application notes with
supporting design files. These designs represent good starting points for implementing
simple to complex functions in Xilinx programmable logic.
These designs are supplied free from Xilinx, and come without technical support
or warranty. For pre-implemented and verified functions that include technical support,
we suggest that you consider the Xilinx LogiCORE or AllianceCORE products.
Reference Designs
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Please read the complete Reference
Design License Agreement. All Reference Designs found on the Xilinx Website are
bound by this agreement. These designs are supplied free from Xilinx, and come without
technical support or warranty. |
Parameterizable SDRAM Controller for Virtex |
Download SDRAM
Contoller for Virtex |
View Data Sheet |
A synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM
controller in the Virtex FPGA family. A 32-bit wide data interace version can run
up to 125 MHz when automatically placed and routed in a Virtex -6 speed grade. Hand
placed versions of the design can run even faster. |
Constant Coefficient Multiplier (KCM) generator for Virtex |
Download Constant
Coefficient Multiplier |
View Data Sheet
& Read Me |
Constant Coefficient Multiplier (KCM) generator for Virtex. This DOS utility generates
RPM based cores for KCM multipliers. Supports 8, 12, 16 and 20 bit data, signed/unsigned,
and combinatorial/pipelined modules. |
Library of 19 Virtex Multipliers |
Download Virtex Multipliers |
View Data Sheet |
Library of 19 Virtex variable by variable multipliers. Includes signed or unsigned,
combinatorial or pipelined point solutions, RPMed and optimized for speed and area. |
Digital Signal Processing |
High Performance 16-point Complex FFT |
Download 16-point
complex FFT |
View Data Sheet |
Fully placed 16-point complex FFT for the XC4000 family. The core accepts 16-bit
Fully placed high-performance 16-point complex FFT. 16-bit complex input samples
(16 bits for both the real and imaginary components) are processed using a fixed-point
arithmetic FFT engine. Includes VHDL behavioral models, a VHDL testbench as well
as a bit-true C model. Matlab scripts demonstrating test vector generation and testbench
output qualification are also included.
- 2's complement arithmetic
- Parallel architecture provides a new output sample on every clock
- Naturally ordered input and output data
High performance and density guaranteed through Relational Placed Macro (RPM)
mapping and placement technology.
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High Performance 1024-Point Complex FFT |
Download 1024-point
complex FFT |
View Data
Sheet |
Fully placed 1024-point complex FFT for the XC4000 family. The core accepts 16-bit
complex input samples and produces a 16-bit precision result vector. |
Memory & Storage Elements |
170 MHz FIFOs Using the Virtex Block SelectRAM+ |
Download Virtex
HDL Block RAM FIFOs |
View Data Sheet |
Virtex HDL Block RAM FIFOs (XAPP131)
512x8 Asynchronous (independent clock) and synchronous (common clock) block RAM
based FIFOs for Virtex written in Verilog and VHDL. 170 MHz performance possible
in a Virtex -6 speed grade device.
Also included is a *parameterizable* version of a VHDL Asynchronous FIFO for Virtex
with associated testbench files.
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Parameterizable Distributed RAM for Virtex (VHDL) |
Download Parameterizable
VHDL RAMs for Virtex |
View Data
Sheet |
Parameterizable VHDL RAMs for Virtex
- Use SelectRAM(TM) for more efficient storage
- Support memory depths from 64 to 8192 in 16 bit increments
- Source files for Single Port / Dual Port versions
- Selectable registered inputs/outputs
- Selectable input/output clock enables
- Selectable multiplexing scheme for combining RAM primitives
Supports Synopsys FPGA Express and Synplicity synthesizers.
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