Answers Database MODELSIM (MTI): How to compile the 2.1 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries? Record #2561 Product Family: Software Product Line: Model Technology Product Part: Modelsim Product Version: 5.2 Problem Title: MODELSIM (MTI): How to compile the 2.1 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries? Problem Description: Urgency: Standard General Description: To perform timing or post-synthesis functional HDL simulation with the Xilinx Alliance 2.1 tools, the Verilog and/or VHDL (VITAL) simprim models must be compiled for use in the Model Technology simulator. If instantiated LogiBLOX, CORE Generator and/or Unified library components are to be behaviorally simulated, the LogiBLOX, CORE Generator and/or Unisim libraries must be compiled as well. Please see (Xilinx Solution 1923) on how to compile the HDL libraries for Xilinx Alliance 1.5. The Xilinx Alliance software contains 3 types of HDL simulation libraries and Coregen contains one: simprim - Library of generic simulation primitives LogiBLOX - Library of LogiBLOX simulation models (VHDL only) unisim - Library of Unified component simulation models (A1.4+) XilinxCoreLib - Coregen HDL Library. Please see (Xilinx Solution 7859) for instructions on extracting and compiling this library Note: Tested with Modelsim EE 5.2 and later. Solution 1: A Tcl script is available on Xilinx FTP site. Currently, this script can only be used with the Modelsim EE/PE edition. PC: ftp://ftp.xilinx.com/pub/utilities/3rdparty/xilinx_lib.zip UNIX: ftp://ftp.xilinx.com/pub/utilities/3rdparty/xilinx_lib.tar.Z FOR EE: Use the "source" command from the ModelSim prompt to load that Tcl/Tk code. At the Modelsim prompt, type        MODELSIM> source <path_to_script>/xilinx_lib.tcl FOR PE: The xilinx_lib.tcl file is used to run the GUI in Modelsim PE. Set the enviroment variable MODELSIM_TCL to the location of the script prior to invoking ModelSim. [Note: MODELSIM_TCL can be a ":" separated list of Tcl/Tk files to load]. MODELSIM_TCL <path_to_script>/xilinx_lib.tcl Where <path_to_script> is the pathname for the directory to where the script was saved. Solution 2: Modelsim has extended the Tcl language with some simulation commands, so Tcl can be used as a scripting language to run Modelsim. The instructions that follow reference the following variables: - Set access to the MODEL_TECH and XILINX environment variable. set MODEL_TECH $env(MODEL_TECH) set XILINX $env(XILINX) - VERILOG_DESTN - Location for compiled Verilog libraries set VERILOG_DESTN [file join $MODEL_TECH/xilinx/verilog] VHDL_DESTN - Location for compiled VHDL libraries set VHDL_DESTN [file join $MODEL_TECH/xilinx/vhdl] If you want logical library names to be available for all designs, set your MODELSIM environment variable to the location of your master .ini file, e.g.:     setenv MODELSIM $MODEL_TECH/Xilinx/modelsim.ini If MODELSIM is not set when vmap is run, the logical library mapping is done locally, and therefore all vmap commands would have to be run for each new HDL design. For Verilog users, the compilation commands that need to be executed are: SIMPRIM: vlib $VERILOG_DESTN/simprims vmap simprims_ver $VERILOG_DESTN/simprims vlog -work simprims_ver $XILINX/verilog/src/simprims/*.v LogiBLOX: Uses the SIMPRIMS-based library. UNISIM: vlib $VERILOG_DESTN/uni3000 vmap uni3000 $VERILOG_DESTN/uni3000 vlog -work uni3000 $XILINX/verilog/src/uni3000/*.v vlib $VERILOG_DESTN/unisims_ver vmap unisims_ver $VERILOG_DESTN/unisims_ver vlog -work unisims_ver $XILINX/verilog/src/unisims/*.v vlib $VERILOG_DESTN/uni5200 vmap uni5200 $VERILOG_DESTN/uni5200 vlog -work uni5200 $XILINX/verilog/src/uni5200/*.v vlib $VERILOG_DESTN/uni9000 vmap uni9000 $VERILOG_DESTN/uni9000 vlog -work uni9000 $XILINX/verilog/src/uni9000/*.v Note: To refernce these libraries during Verilog simulation, the -L switch must be specified during VSIM execution specifying library name given for the VMAP command. Example for Verilog timing simulation: vlog testbench.v time_sim.v glbl.v vsim -L simprims_ver testbench_module_name glbl For VHDL users, the commands are: SIMPRIM: vlib $VHDL_DESTN/simprim vmap simprim $VHDL_DESTN/simprim vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd vcom -87 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd LogiBLOX: vlib $VHDL_DESTN/logiblox vmap logiblox $VHDL_DESTN/logiblox vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlutil.vhd vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/mvlarith.vhd vcom -87 -work logiblox $XILINX/vhdl/src/logiblox/logiblox.vhd UNISIM (Versions A1.4 and later): vlib $VHDL_DESTN/unisim vmap unisim $VHDL_DESTN/unisim vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd vlib $VHDL_DESTN/unisim_5k vmap unisim_5k $VHDL_DESTN/unisim_5k vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VPKG.vhd vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCOMP52K.vhd vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL.vhd vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VITAL52K.vhd vcom -87 -work unisim_5k $XILINX/vhdl/src/unisims/unisim_VCFG52K.vhd Coregen (Coregen must be installed seperatly from M1): Please see (Xilinx Solution 6037) End of Record #2561 - Last Modified: 11/17/99 11:05

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