Answers Database
FPGA Configuration: DONE Doesn't Go High; General XC4000 Debugging Hints
Record #102
Product Family: Hardware
Product Line: 4000
Product Part: 4000
Problem Title:
FPGA Configuration: DONE Doesn't Go High; General XC4000 Debugging Hints
Problem Description:
Urgency: Standard
General XC4000 Configuration Debugging Hints.
This section assumes you have understanding of how
configuration works in our XC4000 devices, so before you read
the following it is strongly recommended to carefully read
the configuration section in our "Programmable Data Book."
Solution 1:
Two conditions have to be met in order for the DONE pin on an
xc4000 device to go high:
1. The FPGA's internal configuration memory must be full.
2. The configuration length count must be met, EXACTLY.
This is important because the counter that determines when the
length count is met begins counting with the very first cclk,
not the first one after the preamble.
This means if a stray bit is inserted before the preamble or
the data source is not ready at the time of the first cclk, the
internal counter that holds the number of cclks will be one
ahead of the actual number of data bits read. Thus, at the end
of configuration the second condition will not be met until the
24 bit counter can roll past terminal count and then back up to
the lengthcount number stored in the lengthcount register. This
causes the FPGA to wait for no more than [ 2^24 * cclk
frequency] seconds.
If it is not possible to have the data ready at the time of the
first cclk, the problem could be circumvented by adding a few
buffer bits to the number in the length count.
Other things to check:
Remember that the xchecker expects to DRAW power from the pwr
and ground connections, not provide it.
If using the download cable, is the LCA configured in Slave
mode (M0=M1=M2=High)?
Is the DONE pin configured with the internal pullup or pulled
up externally? Note that the download cable does not pull up
DONE.
Are the PROG and INIT pins pulled up?
The default MakeBits options are shown below.
CRC Disable (1)
Cfgosc F1Mhz
Donepin Nopullup (2)
Readcapture Disable
Startupclk CCLK
Synctodone No
Outputsactive State1
GSRactive State2
Doneactive State0
(1) With CRC enabled, the INIT pin is pulled Low during
configuration if a data frame error is detected.
(2) Activate Pullup if an external pullup is not used.
The sections in the back of The User Guide and Tutorials book
are a good source for further information.
End of Record #102 - Last Modified: 10/19/98 11:31 |
