Answers Database
FPGA Configuration: Done goes high but outputs never become active.
Record #158
Problem Title:
FPGA Configuration: Done goes high but outputs never become active.
Problem Description:
Urgency: Standard
General Description:
Device seems to complete configuration, but is not operating.
Solution 1:
If the user chooses options in makebits or BitGen such that the
activation of the chip is synchronized with a user clock
(uclk_sync and uclk_nosync) and no user clock is specified in
the design and/or attached to the device, the chip could reach
a point where the configuration of the device is done and the
done pin is asserted, but the outputs do not become active.
The solution is either to recreate the bitstream specifying the
startup clock as cclk, or supply the appropriate user clock.
In an XC4000 device, remember that by default the GSR is
released two CCLKs after the DONE pin goes high. If you do not
clock twice after DONE goes high in serial slave mode, your
outputs will forever stay in their initial state.
End of Record #158 - Last Modified: 11/10/98 10:32 |
