Answers Database
FPGA Configuration: Excessive loading on cclk may cause frame error.
Record #169
Problem Title:
FPGA Configuration: Excessive loading on cclk may cause frame error.
Problem Description:
Urgency: Standard
General Description:
It has been observed that having an exessive amout of loads
on the cclk output may create noise on the cclk line that will
cause frame errors during configuration.
Solution 1:
The cclk output is also fed back internally for use in shifting
configuration data. (One user who had this problem had 18
FPGAs daisy-chained together). To verify if this is the problem, attempt to configure a smaller num
ber of devices
with the same bitstream. If this fixes the errors, it may
be necessary to externally buffer cclk.
End of Record #169 - Last Modified: 11/10/98 16:25 |
