Answers Database
FPGA CONFIGURATION : Which pins are driven during clear/initialization? (master par)
Record #195
Problem Title:
FPGA CONFIGURATION : Which pins are driven during clear/initialization? (master par)
Problem Description:
Urgency: Standard
General Description:
Which configuration Pins are actively driven during the
Power-up and Clear and Initialization stages of configuration?
Solution 1:
When configuring an FPGA device in master parallel mode, the
address lines will remain tristated after power-up until after
the INIT has gone high and the Mode pins have been sampled.
This occurs after the clear and initialization stages in the
configuration process.
In fact all configuration mode-specific pins such as CCLK,
RDY/BUSY, etc. are tristated during the clear and
initialization stages. However the pins HDC,LDC, Done, Init,
and Dout will begin driving as soon as the chip reaches
threshold voltage.
End of Record #195 - Last Modified: 11/12/98 10:04 |
