Answers Database
FPGA Configuration: FAST CCLK causes dataframe error (INIT goes Low).
Record #212
Problem Title:
FPGA Configuration: FAST CCLK causes dataframe error (INIT goes Low).
Problem Description:
Urgency: Standard
General Description:
FPGAs have optionally controlled CCLK speeds. XC4000 devices
can generate a configuation clock (CCLK),used to clock
configuration data to the device when operating in master mode,
at two different speeds. In the default slow mode, frequency
ranges from 0.5MHz to 1.25MHz In FAST CCLK mode, the frequency
will range from 4MHz to 10MHz. The XC4000X family FPGAs can run
as fast as 15MHz when in fast mode.
If the PROM, or other memory device, cannot run at this speed
then setup time requirements for configuration could be
violated resulting in a failed configuration.
Solution 1:
Return the CCLK speed to the default SLOW speed to determine if
this is the cause. Consult the operating specifications for
the PROM or other memory device.
End of Record #212 - Last Modified: 11/11/98 14:26 |
