Answers Database
FPGA Configuration:Asynch Peripherial mode-Done goes high, ouputs not active.
Record #740
Problem Title:
FPGA Configuration:Asynch Peripherial mode-Done goes high, ouputs not active.
Problem Description:
The Makebits option "align to done" can often cause problems
when configuring with asynchrounous peripheral mode. It is
highly desireable that the complete change from configuration
to user operation occur as the result of one single byte-wide
input. The activation of ouputs and DONE, the de-activation
of the global reset, and the progression to the "finished"
state should all occur as a result of one common byte input.
Under normal circumstances, the software achieves this by
manipulating the length-count value appropriately, taking
into account the additional bits between devices, and
adjusting for the fact that byte-wdie interfaces always leave
the last bit sitting in the parrallel-to-serial converter,
shifting it out at the beginning of the next byte. This can
prevent a device from reaching the finished state.
Solution 1:
Choose the "align to length count" option in MAKEBITS. This
will ensure that the last write of the configuration will have
enough clocks to get all the way through the startup sequence.
NOTE: If you are using MAKEPROM, you need to set this option
in MAKEPROM. If you set the option in MAKEBITS, but not in
MAKEPROM, MAKEPROM could change the PROM file back to "align
to done".
End of Record #740 - Last Modified: 11/04/96 05:15 |
