Answers Database
JTAG - Consecutive readbacks via the JTAG interface in the XC4000/XC5200/Spartan devices
Record #941
Problem Title:
JTAG - Consecutive readbacks via the JTAG interface in the XC4000/XC5200/Spartan devices
Problem Description:
Urgency: standard
General Description:
The procedure for performing consecutive readbacks via the
JTAG interface for the XC4K/XC5K and Spartan devices.
Solution 1:
1. For the XC5200 Start Here:
To do Readback-Verify via the TAP in the
XC5200, skip down to step 3A.
1A. For the XC4000/E/XL/XLA/XV start here:
In your schematic, or top-level synthesis design, instantiate the BSCAN and READBACK symbols.
2.
Connect the BSCAN symbol pins TDI, TMS, TCK, and TDO to the
boundary scan pads TDI, TMS, TCK, and TDO, respectively.
3.
Next, connect the net between the TCK pad and TCK pin on the
BSCAN symbol to an IBUF. Take the output of the IBUF and
connect it to the CLK pin of the READBACK symbol. This
drawing can be obtained from the Xilinx hotline via fax.
Note: This is available in the CRC
3A.
Note, for the XC5200 family, drawing this connection in your
schematic or HDL code will not work, due to ppr. If you
want to do consecutive readbacks via the TAP in the XC5200
family, then you must connect the bscan symbol and readback
symbols by using XDE.
After placing and routing your design, load your .lca file
from ppr into XDE and enter the EditLCA program.
Next follow the procedures below (Note, <ENTER> points to the
enter/return key on your keyboard):
(a)
eb bscan <ENTER>
This will bring you into the editblock window for the bscan
symbol for the 5k.
(b)
In the editblock window, select the 'used' option, which is
in the upper left hand corner of the screen.
(c)
endb <ENTER>
This brings you back to the EditLCA screen.
(d)
addnet username tckpin.i rdbk.ck <ENTER>
,where tckpin is the pin number of your 5200 device. For
example, if you're design was a 5202PC84, then the above
command line would be:
addnet username p16.i rdbk.ck <ENTER>
(e)
At this point you should see a net go from the TCK pin
to the ck pin of the readback symbol.
(f)
Save your changes to the .lca file and exit XDE.
4.
After entering the above circuit, compile the design to an
.lca file.
5.
Make the .bit file for the .lca file by using the following
option with makebits:
-f readclk:rdbk
For example, at a unix prompt:
% makebits -f readclk:rdbk designame
6.
Now the FPGA is ready to perform consecutive readbacks.
READBACK is performed by loading the IR with the READBACK
instruction and then shifting out the captured data from the
shift-dr state in the TAP.
Perform the first readback by loading the IR with the
READBACK instruction. This first readback must be finished,
which means shifting out the *entire* readback bitstream. To
be safe, shift out the entire bitstream and then send three
additional TCK's.
7.
After performing the first readback, another readback can be
performed by going to the test-logic-reset state, and
re-loading the READBACK instruction and performing the
READBACK as described in the previous paragraph.
In summary, consecutive readbacks are performed by
starting from test-logic-reset, loading the IR with the
READBACK instruction, shifting out the readback bitstream
plus three additional TCK's, and then going back to the
test-logic-reset state.
Alternatively, if you do not want to go back to the
test-logic-reset state, realize that after shifting out
readback bitstream, a minimum of 3 additional clocks are
needed on the readback register. So, after doing a readback,
instead of going back to test-logic-reset, a user can opt to
execute some other JTAG instruction, and then perform another
readback.
Additional Notes:
A hard copy of the BSCAN to READBACK connection is available on request. It is available in the CRC
Also, this above procedure is only needed if you intend to do
more than 1 readback. If you intend only to do a readback
once, then connection between the BSCAN symbol and the
READBACK symbol is not needed. In that case, all that is
needed is the BSCAN symbol instantiated with the boundary
scan pads(TDI, TMS, TCK, & TDO) on the top-level of the
design.
End of Record #941 - Last Modified: 01/10/00 21:14 |
