Answers Database
JTAG - /PROGRAM held low in FPGA's limits boundary scan instruction set
Record #993
Product Family: Hardware
Product Line: 4000E
Product Part: 4000E
Problem Title:
JTAG - /PROGRAM held low in FPGA's limits boundary scan instruction set
Problem Description:
Urgency: standard
General Description:
Which TAP instructions are available in FPGAs if the /PROGRAM
pin is held low?
Solution 1:
If the /PROGRAM pin is pulled low at any time, it will disrupt all
boundary scan operations as it effectively resets the TAP controller
in all FPGA's.
In the XC4K/XC5K/Spartan families, the following Boundary Scan instructions
are still available with the /PROGRAM pin held low:
Sample/Preload
Bypass
For additional information please refer to the Boundary Scan application note at
http://www.xilinx.com/xapp/xapp017.pdf
Solution 2:
If /PROGRAM is held low in Virtex (and Virtex derivatives), the TAP
controller is held in reset, and no boundary scan instructions are available.
To delay configuration of Virtex and Virtex derivatives, you must use the /INIT pin.
For more information on JTAG in Virtex, see
http://support.xilinx.com/xapp/xapp139.pdf
End of Record #993 - Last Modified: 01/10/00 13:05 |
