Answers Database
Foundation Simulator: XC7300/XC9500 flip-flop outputs unknown (PRLD signal)
Record #1045
Product Family: Software
Product Line: Aldec
Product Part: Foundation Logic Simulator
Product Version: 1.17
Problem Title:
Foundation Simulator: XC7300/XC9500 flip-flop outputs unknown (PRLD signal)
Problem Description:
When performing a Timing Simulation on a CPLD design, you may
see the outputs of flip-flops go into undefined states, even
when the Functional Simulation worked.
The Foundation Simulator does not toggle the PRLD signal
during the Power-on/Reset initialization. The PRLD signal
is present in the post-fitted netlist, and therefore if this
signal is not toggled at the beginning of the simulation, the
flip-flops are not properly intialized.
Solution 1:
At the beginning of the simulation, toggle the PRLD signal.
Add the signal 'PRLD' to the Waveform Viewer Window.
PRLD is active-high, so drive it high, then low, at the
start of the simulation to initialize all the flip-flops.
End of Record #1045 - Last Modified: 11/30/98 15:35 |
