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CPLD: XC9500: Device Slew Rates (Rise/Fall times) with capacitive loadsRecord #1490
Product Family: Hardware Note: The numbers indicated below are based upon a single data point and are given solely as a service for our customers to estimate the effects of additional Capacitive loading. Xilinx does not guarantee these numbers. Method: Capacitance of the test fixture was measured on the HP 4284A Precision LCR meter. The capacitance of one I/O path in the speed board was approximately 35pF at 1MHz. Two XC95108 PC84 units were programmed to 16 bit counter pattern, one with SLOW slew rate and the other with FAST slew rate. The parts then were exercised at the clock rate of 5MHz to determine additional output delays with additional capacitive loads. Output rise/fall time was observed on the HP 54720D oscilloscope with HP 54701A Active Probe. Measurement Result: SLOW SLEW MODE: Low to High (rise time from 10 % to 90% of Vout) Added Load RISE TIME -0- 5.2ns 35pF 5.2ns 57pF 5.5ns 90pF 5.8ns 157pF 6.4ns 212pF 7.0nS FAST SLEW MODE: Low to High (rise time from 10 % to 90% of Vout) Added Load RISE TIME -0- 570ps 35pF 2.0ns 57pF 2.5ns 90pF 2.8ns 157pF 3.0ns 212pF 3.4ns SLOW SLEW MODE: High to Low (Fall time from 90 % to 10% of Vout) Added Load FALL TIME -0- 1.1ns 35pF 1.8ns 57pF 2.1ns 90pF 2.3ns 157pF 2.5ns 212pF 2.5ns FAST SLEW MODE: High to Low (Fall time from 90 % to 10% of Vout) Added Load FALL TIME -0- 640ps 35pF 1.6ns 57pF 1.8ns 90pF 1.9ns 157pF 2.0ns 212pF 2.0ns Note 1. Two units came from the assembly lot #A67562A PC84ASJ9641. (Note: FAST and SLOW SLEW rates are spec'd the same for the various speed grades of a given part.) 2. Measurement was done at Room temperature and Vcc = 5.0V. 3. HP 54720D oscilloscope bandwidth: 2.0GHz. 4. HP 54701A Active Probe bandwidth: 2.5GHz. 5. HP 54701A Active Probe Input impedance: 100k End of Record #1490 - Last Modified: 12/20/99 13:03 |
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