Answers Database
FPGA Configuration: Size of external pulldown needed to create a logic low.
Record #1579
Problem Title:
FPGA Configuration: Size of external pulldown needed to create a logic low.
Problem Description:
Urgency: Standard
General Description:
It may be necessary at times to attach an external
pull-down resistor to an FPGA user I/O to counter
the internal pull-up resistor and ensure a logic low
signal during configuation (internal pullup is active).
What size pulldown is necessary to ensure a logic low?
Solution 1:
For MODE pins a maximum resistance of 2.7Kohms is recommended. For I/Os there may be other consider
ations for the application. A typical value is 3.3Kohms as shown below.
Given that the minimum impedence of an internal pull-up resistor for the xc5200 and xc4000 families
is stated to be
20K, Vcc=5V, and V(IL) Max=0.8V : a simple voltage division
equation reviels :
V1 = V(R1/(R1+R2))
which is
0.8 = 5(R1/(R1+20000)
this results in
R1=3.8K
An external pulldown resistor impedence of 3.8K or less
should ensure a logic low during configuration.
End of Record #1579 - Last Modified: 11/11/98 14:45 |
