Answers Database


Constraints: How do I specify Timespec and Timegroup constraints in a UCF file


Record #1607

Product Family: Software

Product Line: FPGA Implementation

Product Part: ngdbuild

Product Version: 1.2.

Problem Title:
Constraints: How do I specify Timespec and Timegroup constraints in a UCF file


Problem Description:
Urgency: Hot

General Description:
The User Constraint File (UCF) is a user created ASCII file that holds user
timing and location constraints. It is read by ngdbuild, which also takes
a design netlist, like edif, and produces a .ngd file.


Solution 1:

Sample Timing Constraint Schematic
Sample Timing Constraint Schematic


-- User Constraint File (UCF) Below---
# This is a comment

# Period specifies minimum PERIOD of CLK net. Offset specifies
# that data on MAY, can arrive upto 6 ns before the clock edge arrives
# on CLK. NOTE: Period constraints do not apply to elements in
# ouput pads.
NET CLK PERIOD = 20ns;
NET MAY OFFSET = IN:6ns:BEFORE:CLK_PD;

# Groups all clocked loads of CLK2 into CLK2_LOADS timegroup
# Groups all clocked loads of VAL into VAL_LOADS timegroup
# TNM => Timegroup NaMe
NET CLK2 TNM=CLK2_LOADS;
NET VAL TNM=VAL_LOAD;

# Specifies worst case speed of path from IPAD to CLK2 loads.
# Includes pad, buffer, and net delays. TS01 is a timespec
# identifier; it can have names of the form TS<string>.
# PADS(CLK2_PD) is a timegroup name specified inside of a
# timespec.
TIMESPEC TS01=FROM:PADS(CLK2_PD):TO:CLK2_LOADS=15ns;

# Specifies the maximum frequency for all loads clocked by CLK2.
TIMESPEC TS02=FROM:CLK2_LOADS:TO:CLK2_LOADS=30Mhz;

# Specifies the minimum delay on the path from Synchronous
# RAM to OFD. Includes Clock to Out delay, net delay,
# and setup time.
TIMESPEC TS03=FROM:CLK2_LOADS:TO:VAL_LOAD=15000ps;




End of Record #1607 - Last Modified: 07/13/99 14:27

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!