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Configuring device I/Os as an open-drain (open-collector)


Record #1651

Problem Title:
Configuring device I/Os as an open-drain (open-collector)


Problem Description:
Urgency: Standard

Description

It is often useful to have open-drain or open-collector
outputs so that multiple outputs may be connected to a
single input, such as a reset line.
Can I configure my Xilinx device to have open-drain
outputs?


Solution 1:

With most all Xilinx devices, an open-drain type output may be
configured. Schematically, this type of output should look
like the following :

Open-Drain Output
Open-Drain Output


This sort of circuitry may also be described in HDL code.




End of Record #1651 - Last Modified: 09/14/99 14:30

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