Answers Database VERILOG-XL: SDFA Error: Type of INSTANCE xxxx does not match CELLTYPE <cell_name> Record #1895 Product Family: Software Product Line: Cadence Product Part: Verilog-XL Problem Title: VERILOG-XL: SDFA Error: Type of INSTANCE xxxx does not match CELLTYPE <cell_name> Problem Description: Urgency: standard General Description: The SDF Annotator issues an error message similar to the following: Error: Type of INSTANCE XXXX does not match CELLTYPE YYYY Solution 1: This may be seen when doing a board level simulation incorporating multiple Verilog netlists using the `uselib directive that reference libraries with similar cell names. When simulations are run on the individual Verilog netlists by themselves, SDF Annotate operates properly, but doing a complete board level simulation with multiple netlists and their associated SDF files causes this error to appear. In the multiple Verilog netlist situation (such as in a board level simulation), the `uselib compiler directive changes the duplicate module or primitive names to make them unique. The side effect of this is that once the module and primitve names have been changed, the SDF Annotator is no longer able to match up the original instance types to the cell types in the netlist. Invoke Verilog-XL with the command-line option, +sdf_nocheck_celltype. The +sdf_nocheck_celltype plus option disables celltype validation between the SDF Annotator and the Verilog description. By default, the SDF Annotator validates the type specified in the CELLTYPE construct against the type of the cell instance that is specified in the INSTANCE keyword construct. End of Record #1895 - Last Modified: 10/14/99 15:35

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