Answers Database
FPGA Configuration: What are the thresholds for the Configuration Pins?
Record #2098
Product Family: Hardware
Product Line: 4000E
Product Part: 4000E
Problem Title:
FPGA Configuration: What are the Thresholds for the Configuration Pins?
Problem Description:
Urgency: Standard
General Description: What are the input and output thresholds
of the configuration pins of the XC4000 and Spartan family of
devices before and during configuration, CMOS or TTL?
Note: All user I/O on our 5V parts (4000E and 4000EX) families
have programmable thresholds on all of the inputs and outputs
after the device is configured but the configuration pins have
a defined threshold (see below) since the device is not yet
configured.
The I/O on our 3V parts (XC4000L and XC4000XL) have CMOS level
I/O and do not have programmable thresholds. See Solution 2760:
http:/www.xilinx.com/techdocs/2760.htm
Solution 1:
In all our 5-V parts (XC4000, XC4000E, XC400EX, Spartan) the
input and output thresholds are TTL on all configuration pins,
until the configuration has been loaded into the device and
specifies to use otherwise.
In all our 3-V parts (XC4000L, XC4000XL, SpartanXL), everything
is CMOS thresholds in and CMOS levels out.
In Virtex-E and Spartan-II, all banks are in the LVTTL standard
until they are configured otherwise.
End of Record #2098 - Last Modified: 01/12/00 15:04 |
